The ADS41B29/B49 are members of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers

ADS41B29

Manufacturer Part NumberADS41B29
DescriptionThe ADS41B29/B49 are members of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers
ManufacturerTexas Instruments
ADS41B29 datasheet
 


Specifications of ADS41B29

Resolution(bits)12Sample Rate (max)(sps)250MSPS
# Input Channels1Snr(db)69.2
Sfdr(db)89Power Consumption(typ)(mw)350
Operating Temperature Range(c)-40 to 85InterfaceParallel CMOS,Parallel LVDS
Analog Voltage Av/dd(min)(v)1.7Analog Voltage Av/dd(max)(v)1.9
Digital Supply(min)(v)1.7Digital Supply(max)(v)1.9
ArchitecturePipelineInl(max)(+/-lsb)3.5
Sinad(db)68.3Enob(bits)11.07
Input Range1.5V (p-p)Reference ModeInt
Analog Input Bw(mhz)800Pin/package48VQFN
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14-/12-Bit, 250MSPS, Ultralow-Power ADC
FEATURES
1
• ADS41B49: 14-Bit, 250MSPS
23
ADS41B29: 12-Bit, 250MSPS
Integrated High-Impedance
Analog Input Buffer:
– Input Capacitance: 2pF
– 200MHz Input Resistance: 3kΩ
Maximum Sample Rate: 250MSPS
Ultralow Power:
– 1.8V Analog Power: 180mW
– 3.3V Buffer Power: 96mW
– I/O Power: 135mW (DDR LVDS)
High Dynamic Performance:
– SNR: 69dBFS at 170MHz
– SFDR: 82.5dBc at 170MHz
Output Interface:
– Double Data Rate (DDR) LVDS with
Programmable Swing and Strength:
– Standard Swing: 350mV
– Low Swing: 200mV
– Default Strength: 100Ω Termination
– 2x Strength: 50Ω Termination
– 1.8V Parallel CMOS Interface Also
Supported
Programmable Gain for SNR/SFDR Trade-Off
DC Offset Correction
Supports Low Input Clock Amplitude
Package: QFN-48 (7mm × 7mm)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments, Incorporated.
2
All other trademarks are the property of their respective owners.
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SBAS486D – NOVEMBER 2009 – REVISED DECEMBER 2010
with Analog Buffers
Check for Samples: ADS41B29,
ADS41B49
DESCRIPTION
The
ADS41B29/B49
ultralow-power ADS4xxx analog-to-digital converter
(ADC) family, featuring integrated analog input
buffers.
These
techniques to achieve high dynamic performance,
while consuming extremely low power. The analog
input pins have buffers, with benefits of constant
performance and input impedance across a wide
frequency range. The devices are well-suited for
multi-carrier,
applications such as PA linearization.
The ADS41B49/29 have features such as digital gain
and offset correction. The gain option can be used to
improve SFDR performance at lower full-scale input
ranges, especially at high input frequencies. The
integrated dc offset correction loop can be used to
estimate and cancel the ADC offset. At lower
sampling rates, the ADC automatically operates at
scaled-down power with no loss in performance.
The devices support both double data rate (DDR)
low-voltage differential signaling (LVDS) and parallel
CMOS digital output interfaces. The low data rate of
the DDR LVDS interface (maximum 500MBPS)
makes it possible to use low-cost field-programmable
gate array (FPGA)-based receivers. The devices
have a low-swing LVDS mode that can be used to
further reduce the power consumption. The strength
of the LVDS output buffers can also be increased to
support 50Ω differential termination.
The devices are available in a compact QFN-48
package and are specified over the industrial
temperature range (–40°C to +85°C).
ADS41B29
ADS41B49
are
members
of
devices
use
innovative
wide
bandwidth
communications
Copyright © 2009–2010, Texas Instruments Incorporated
the
design

ADS41B29 Summary of contents

  • Page 1

    ... Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. SBAS486D – NOVEMBER 2009 – REVISED DECEMBER 2010 with Analog Buffers Check for Samples: ADS41B29, ADS41B49 DESCRIPTION The ADS41B29/B49 ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers ...

  • Page 2

    ... ADS41B29 ADS41B49 www.ti.com PACKAGE ORDERING TRANSPORT MARKING NUMBER MEDIA ADS41B29IRGZR Tape and reel AZ41B29 ADS41B29IRGZT Tape and reel ADS41B49IRGZR Tape and reel AZ41B49 ADS41B49IRGZT Tape and reel web site for more ADS41B29, ADS41B49 MIN MAX UNIT –0.3 2.1 V –0.3 3.9 V –0.3 2.1 V –0.3 0.3 V –2.4 2.4 V – ...

  • Page 3

    ... Application Information Application Information. Product Folder Link(s): ADS41B29 ADS41B49 ADS41B29 ADS41B49 ADS41B29, ADS41B49 UNITS RGZ 48 PINS 29 n/a 10 °C/W 0.3 9 1.13 ADS41B29, ADS41B49 TYP MAX UNIT 1.8 1.9 V 3.3 3.6 V 1.8 1 1.7 ± 0.05 V 400 MHz 600 MHz 80 MSPS 250 MSPS 1 1 ...

  • Page 4

    ... ADS41B29 ADS41B49 SBAS486D – NOVEMBER 2009 – REVISED DECEMBER 2010 ELECTRICAL CHARACTERISTICS: ADS41B29, ADS41B49 Typical values are at +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, 1.5V cycle, –1dBFS differential analog input, and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are across the full temperature range – ...

  • Page 5

    ... In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the supply voltage (see the CMOS Interface Power Dissipation Copyright © 2009–2010, Texas Instruments Incorporated SBAS486D – NOVEMBER 2009 – REVISED DECEMBER 2010 MIN ADS41B29, ADS41B49 MIN VCM –15 E –2 ...

  • Page 6

    ... ODH V Standard swing LVDS –430 ODL V Low swing LVDS ODH V Low swing LVDS ODL V 0.85 OCM Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS41B29 ADS41B49 www.ti.com ADS41B29, ADS41B49 TYP MAX UNIT µA 0 µA 0 µA –10 µA ...

  • Page 7

    ... SBAS486D – NOVEMBER 2009 – REVISED DECEMBER 2010 (1) RGZ PACKAGE QFN-48 (TOP VIEW Figure 1. ADS41B49 LVDS Pinout Product Folder Link(s): ADS41B29 ADS41B49 ADS41B29 ADS41B49 37 36 DRGND 35 DRVDD 34 D0_D1_P 33 D0_D1_M RESET 29 SCLK 28 SDATA 27 SEN 26 AVDD 25 AGND 24 ...

  • Page 8

    ... OVR_SDOUT 3 CLKOUTM 4 CLKOUTP 5 DFS AVDD 8 AGND 9 CLKP 10 CLKM 11 AGND 12 (2) The PowerPAD™ is connected to DRGND. ADS41B49, ADS41B29 Pin Descriptions (LVDS Mode) PIN NAME PIN NUMBER AVDD 8, 18, 20, 22, 24, 26 AVDD_BUF 21 AGND 9, 12, 14, 17, 19, 25 CLKP 10 CLKM 11 INP 15 INM 16 VCM 13 RESET 30 ...

  • Page 9

    ... ADS41B49, ADS41B29 Pin Descriptions (LVDS Mode) (continued) PIN NAME PIN NUMBER SEN DFS 6 RESERVED 23 CLKOUTP 5 CLKOUTM 4 D0_D1_P Refer to Figure 1 D0_D1_M Refer to Figure 1 D2_D3_P Refer to Figure 1 D2_D3_M Refer to Figure 1 D4_D5_P Refer to Figure 1 D4_D5_M Refer to Figure 1 D6_D7_P Refer to Figure 1 D6_D7_M ...

  • Page 10

    ... CLOCKGEN Common 14-Bit Digital Functions ADC Control Reference Interface Figure 3. ADS41B49 Block Diagram Logic 0 V ODL Figure 4. LVDS Output Voltage Levels Product Folder Link(s): ADS41B29 ADS41B49 www.ti.com DDR LVDS Interface CLKOUTP CLKOUTM D0_D1_P D0_D1_M D2_D3_P D2_D3_M D4_D5_P D4_D5_M DDR Serializer ...

  • Page 11

    ... Duty cycle of output clock, CLKOUT 1MSPS ≤ sampling frequency ≤ 200MSPS 1 ≤ sampling frequency ≤ 250MSPS 1 ≤ sampling frequency ≤ 200MSPS Time to valid data after OE becomes active Product Folder Link(s): ADS41B29 ADS41B49 ADS41B29 ADS41B49 MIN TYP MAX UNIT ...

  • Page 12

    ... MIN TYP MAX 2 2.8 2.2 3 2.5 3.3 3.5 4.3 5.7 6.5 TIMING SPECIFIED WITH RESPECT TO INPUT CLOCK t (ns) START TYP MAX 1.6 1.1 0.3 0 –1.3 Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS41B29 ADS41B49 www.ti.com HOLD TIME (ns) TYP MAX 0.6 0.6 0.6 0.6 0.6 0.6 t (ns) PDI MIN TYP MAX ...

  • Page 13

    ... (1) 21 Clock Cycles Figure 5. Latency Diagram Product Folder Link(s): ADS41B29 ADS41B49 ADS41B29 ADS41B49 PDI PDI ...

  • Page 14

    ... Dn_Dn + 1_M Figure 6. LVDS Mode Timing PDI CLKOUT ( START Figure 7. CMOS Mode Timing Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS41B29 ADS41B49 www.ti.com t H (1) ...

  • Page 15

    ... The ADS41B29/49 have several modes that can be configured using a serial programming interface, as described in Table 4, Table 5, and configuring commonly used functions. The parallel pins are DFS (analog 4-level control pin) and OE (digital control pin). The analog control pins can be easily configured using a simple resistor divider (with 10% tolerance resistors) ...

  • Page 16

    ... SCLK Figure 9. Serial Interface Timing MIN ) > DC SCLK Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS41B29 ADS41B49 www.ti.com Register Data DSU t SLOADH = –40° +85°C, MIN MAX ...

  • Page 17

    ... SBAS486D – NOVEMBER 2009 – REVISED DECEMBER 2010 Enable Serial Readout (READOUT = 1) Register Data D[7: (don’t care Product Folder Link(s): ADS41B29 ADS41B49 ADS41B29 ADS41B49 Register Data D[7:0] = 0x01 ...

  • Page 18

    ... Submit Documentation Feedback Figure 11. Reset Timing Diagram TEST CONDITIONS MIN pulse active serial registers 100 Product Folder Link(s): ADS41B29 ADS41B49 www.ti.com –40° +85°C, MIN MAX TYP MAX UNIT ...

  • Page 19

    ... PDN OBUF GLOBAL OFFSET PEDESTAL 0 OFFSET CORR TIME CONSTANT 0 0 LOW SPEED Register Address 00h (Default = 00h Product Folder Link(s): ADS41B29 ADS41B49 ADS41B29 ADS41B49 ( RESET READOUT HIGH PERF MODE 1 0 TEST PATTERNS ...

  • Page 20

    ... MODE 1 bits 20 Submit Documentation Feedback Register Address 01h (Default = 00h LVDS SWING (1) Register Address 03h (Default = 00h Product Folder Link(s): ADS41B29 ADS41B49 www.ti.com PERF MODE 1 Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 21

    ... Outputs toggle pattern In the ADS41B49, output data D[13: alternating sequence of 01010101010101 and 10101010101010. In the ADS41B29, output data D[11: alternating sequence of 010101010101 and 101010101010. 100 = Outputs digital ramp In ADS41B46, output data increments by one LSB (14-bit) every clock cycle from code 0 to ...

  • Page 22

    ... Register Address 3Fh (Default = 00h CUSTOM CUSTOM PATTERN D12 PATTERN D11 PATTERN D10 Register Address 40h (Default = 00h CUSTOM CUSTOM PATTERN D4 PATTERN D3 Product Folder Link(s): ADS41B29 ADS41B49 www.ti.com LVDS CLKOUT LVDS DATA 0 STRENGTH STRENGTH ...

  • Page 23

    ... Enables control of output clock fall edge Copyright © 2009–2010, Texas Instruments Incorporated SBAS486D – NOVEMBER 2009 – REVISED DECEMBER 2010 Register Address 41h (Default = 00h CLKOUT RISE Product Folder Link(s): ADS41B29 ADS41B49 ADS41B29 ADS41B49 CLKOUT CLKOUT RISE POSN FALL ...

  • Page 24

    ... Only the ADC and output buffers are powered down; internal reference is active; wake-up time from standby is fast Bits[1:0] Always write '0' 24 Submit Documentation Feedback Register Address 42h (Default = 00h Product Folder Link(s): ADS41B29 ADS41B49 www.ti.com STBY 0 0 Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 25

    ... Copyright © 2009–2010, Texas Instruments Incorporated SBAS486D – NOVEMBER 2009 – REVISED DECEMBER 2010 Register Address 43h (Default = 00h PDN OBUF 0 Register Address 4Ah (Default = 00h Product Folder Link(s): ADS41B29 ADS41B49 ADS41B29 ADS41B49 LVDS SWING PERF 0 ...

  • Page 26

    ... Bits[1:0] Always write '0' 26 Submit Documentation Feedback Register Address BFh (Default = 00h — — — Product Folder Link(s): ADS41B29 ADS41B49 www.ti.com PEDESTAL 31LSB 30LSB 29LSB — 0LSB — –1LSB –2LSB — ...

  • Page 27

    ... SBAS486D – NOVEMBER 2009 – REVISED DECEMBER 2010 Register Address CFh (Default = 00h OFFSET CORR TIME CONSTANT TIME CONSTANT (Number of Clock Cycles) Register Address DFh (Default = 00h LOW SPEED 0 Product Folder Link(s): ADS41B29 ADS41B49 ADS41B29 ADS41B49 OFFSET ...

  • Page 28

    ... SFDR = 70.7dBc SNR = 68.4dBFS SINAD = 66.3dBFS −20 THD = 69.3dBc −40 −60 −80 −100 −120 100 125 0 Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS41B29 ADS41B49 www.ti.com 100 125 Frequency (MHz) Figure 13. Each Tone at −7dBFS Amplitude f = 185MHz IN1 f ...

  • Page 29

    ... SFDR ACROSS GAIN AND INPUT FREQUENCY 250 300 350 400 0 Product Folder Link(s): ADS41B29 ADS41B49 ADS41B29 ADS41B49 SFDR vs INPUT FREQUENCY 50 100 150 200 250 300 350 Input Frequency (MHz) Figure 17. 150MHz 300MHz 170MHz 400MHz 220MHz 0 ...

  • Page 30

    ... PERFORMANCE vs INPUT COMMON-MODE VOLTAGE 73 92 SFDR(dBFS) Input Frequency = 170MHz SFDR(dBc) 72.5 SNR −20 −10 0 1.5 1.55 Product Folder Link(s): ADS41B29 ADS41B49 www.ti.com (Single Tone) 73 SFDR(dBFS) SFDR(dBc) 72.5 SNR 72 71.5 71 70.5 70 69.5 69 68.5 −50 −40 −30 −20 −10 0 Amplitude (dBFS) Figure 21. 70 SFDR SNR 69 ...

  • Page 31

    ... PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE 69 95 SNR Input Frequency = 170MHz SFDR 1.9 1.95 0.1 0.4 0.7 Product Folder Link(s): ADS41B29 ADS41B49 ADS41B29 ADS41B49 −40 55 − 1.75 1.8 1.85 1.9 AVDD Supply (V) Figure 25. 71 SFDR SNR 1.3 1.6 1.9 2.2 2.5 2.8 3.1 3.4 Differential Clock Amplitude (V ...

  • Page 32

    ... Submit Documentation Feedback 71 2.5 THD SNR 2 1.5 70 −0.5 69.5 −1 −1.5 − −2.5 0 2048 Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS41B29 ADS41B49 www.ti.com INTEGRAL NONLINEARITY 4096 6144 8192 10240 12288 14336 16384 Output Code (LSB) Figure 29. ...

  • Page 33

    ... TYPICAL CHARACTERISTICS: ADS41B29 At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5V differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and PP FFT FOR 20MHz INPUT SIGNAL 0 −20 −40 −60 − ...

  • Page 34

    ... ADS41B29 ADS41B49 SBAS486D – NOVEMBER 2009 – REVISED DECEMBER 2010 TYPICAL CHARACTERISTICS: ADS41B29 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5V differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and PP 32k-point FFT, unless otherwise noted ...

  • Page 35

    ... TYPICAL CHARACTERISTICS: ADS41B29 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5V differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and PP 32k-point FFT, unless otherwise noted. SINAD ACROSS GAIN AND INPUT FREQUENCY ...

  • Page 36

    ... ADS41B29 ADS41B49 SBAS486D – NOVEMBER 2009 – REVISED DECEMBER 2010 TYPICAL CHARACTERISTICS: ADS41B29 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5V differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and PP 32k-point FFT, unless otherwise noted ...

  • Page 37

    ... TYPICAL CHARACTERISTICS: ADS41B29 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5V differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and PP 32k-point FFT, unless otherwise noted. PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE ...

  • Page 38

    ... PSRR PSRR 100 - 120 - 100 0 5 Product Folder Link(s): ADS41B29 ADS41B49 www.ti.com CMRR FFT f = 170MHz 93 78 180MHz 160MHz 25 50 ...

  • Page 39

    ... Copyright © 2009–2010, Texas Instruments Incorporated SBAS486D – NOVEMBER 2009 – REVISED DECEMBER 2010 DRVDD CURRENT ACROSS SAMPLING FREQUENCY Product Folder Link(s): ADS41B29 ADS41B49 ADS41B29 ADS41B49 50 75 100 125 150 175 200 225 250 Sampling Speed (MSPS) Figure 52. Submit Documentation Feedback 39 ...

  • Page 40

    ... In put ncy (MHz SFDR (dBc) Figure 53. SFDR CONTOUR (3.5dB Gain, Applies to ADS41B29/B49 150 200 250 300 In put ncy (MHz ...

  • Page 41

    ... SNR (dBFS) Figure 55. SNR CONTOUR (3.5dB Gain, Applies to ADS41B49) 66.5 66 150 200 250 300 In put ncy (MHz) 63.5 64 64.5 65 SNR (dBFS) Figure 56. Product Folder Link(s): ADS41B29 ADS41B49 ADS41B29 ADS41B49 350 400 450 500 350 ...

  • Page 42

    ... In put ncy (MHz) 64.5 65 65.5 66 66.5 SNR (dBFS) Figure 57. SNR CONTOUR (0dB Gain, Applies to ADS41B29 65.5 65 150 200 250 300 In put ncy (MHz) 63.5 64 64.5 SNR (dBFS) Figure 58. Product Folder Link(s): ADS41B29 ADS41B49 www.ti.com ...

  • Page 43

    ... Copyright © 2009–2010, Texas Instruments Incorporated SBAS486D – NOVEMBER 2009 – REVISED DECEMBER 2010 APPLICATION INFORMATION differential input swing ( 5kW ( 1.7V ( 5kW ( Product Folder Link(s): ADS41B29 ADS41B49 ADS41B29 ADS41B49 Buffer Sampling Circuit Buffer Submit Documentation Feedback 43 ...

  • Page 44

    ... Figure 61. ADC Analog Input Capacitance (C 44 Submit Documentation Feedback = .00 .00 1.00 0.10 0.01 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Input Frequency (GHz) ) Across Frequency IN 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Input Frequency (GHz) ) Across Frequency IN Product Folder Link(s): ADS41B29 ADS41B49 www.ti.com ) seen by looking into the ADC input IN 0.8 0.9 1.0 0.9 1.0 Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 45

    ... SBAS486D – NOVEMBER 2009 – REVISED DECEMBER 2010 Figure 62 and Figure 5W INP T1 25W 0 25W INM 1 50W 50W 0 50W 50W 1:1 5W Figure 62 and Figure Product Folder Link(s): ADS41B29 ADS41B49 ADS41B29 ADS41B49 63—one optimized for low input INP INM 63. The center point of this termination Submit Documentation Feedback 45 ...

  • Page 46

    ... SBAS486D – NOVEMBER 2009 – REVISED DECEMBER 2010 CLOCK INPUT The ADS41B29/49 clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using internal 5kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave clock or ac-coupling for LVPECL and LVDS clock sources ...

  • Page 47

    ... GAIN FOR SFDR/SNR TRADE-OFF The ADS41B29/49 include gain settings that can be used to get improved SFDR performance. The gain is programmable from 0dB to 3.5dB (in 0.5dB steps) using the GAIN register bits. For each gain setting, the analog input full-scale range scales proportionally, as shown in The SFDR improvement is achieved at the expense of SNR ...

  • Page 48

    ... Figure 67. Time Response of Offset Correction POWER DOWN The ADS41B29/49 has three power-down modes: power-down global, standby, and output buffer disable. Power-Down Global In this mode, the entire chip (including the ADC, internal reference, and the output buffers) is powered down, resulting in reduced total power dissipation of about 7mW. The output buffers are in a high-impedance state. The wake-up time from the global power-down to data becoming valid in normal mode is typically 100µ ...

  • Page 49

    ... DIGITAL OUTPUT INFORMATION The ADS41B29/49 provide either 14-bit data or 12-bit data, respectively, and an output clock synchronized with the data. Output Interface Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be selected using the LVDS CMOS serial interface register bit or using the DFS pin. ...

  • Page 50

    ... D2_D3_M D4_D5_P , D4_D5_M D6_D7_P , D6_D7_M D8_D9_P , D8_D9_M D10 D11 D10 D12 D13 D12 Sample N Sample Figure 70. DDR LVDS Interface Product Folder Link(s): ADS41B29 ADS41B49 www.ti.com D11 D13 Copyright © 2009–2010, Texas Instruments Incorporated ...

  • Page 51

    ... After reset, the buffer presents an High Low OUTP OUTM High Low = 100Ω). To match with a 50Ω external termination, set the OUT Figure 73. Product Folder Link(s): ADS41B29 ADS41B49 ADS41B29 ADS41B49 External 100 Load W R OUT Figure 72 depicts the CMOS Submit Documentation Feedback 51 ...

  • Page 52

    ... SBAS486D – NOVEMBER 2009 – REVISED DECEMBER 2010 52 Submit Documentation Feedback Pins OVR CLKOUT 14-Bit ADC Data D11 D12 D13 ADS41B49 Figure 72. CMOS Output Interface Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS41B29 ADS41B49 www.ti.com ...

  • Page 53

    ... CLKOUT D0 D0_In D1 D1_In D2 D2_In D12 D12_In D13 D13_In Use short traces between ADC output and receiver pins ( inches). × DRVDD × (N × AVG Product Folder Link(s): ADS41B29 ADS41B49 ADS41B29 ADS41B49 Receiver (FPGA, ASIC, etc.) CLKIN Submit Documentation Feedback (1) 53 ...

  • Page 54

    ... Supply Decoupling Because the ADS41B29/49 already include internal decoupling, minimal external decoupling can be used without loss in performance. Note that decoupling capacitors can help filter external power-supply noise, so the optimum number of capacitors depends on the actual application. The decoupling capacitors should be placed very close to the converter supply pins ...

  • Page 55

    ... GREF GCHAN calculated by dividing the maximum deviation MIN MAX range by the difference T – T MAX MAX ) and distortion (P N Product Folder Link(s): ADS41B29 ADS41B49 ADS41B29 ADS41B49 . 0.5/100 ideal ideal . MIN ) to the noise floor power ( the power S ), but excluding dc. ...

  • Page 56

    ... It is typically expressed in dBc. 56 Submit Documentation Feedback is the change in supply voltage and ΔV is the change in the common-mode voltage of the input pins and ΔV Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS41B29 ADS41B49 www.ti.com ( the power of the S (5) – – ...

  • Page 57

    ... PACKAGING INFORMATION Orderable Device (1) Package Type Package Status ADS41B29IRGZ25 ACTIVE VQFN ADS41B29IRGZR ACTIVE VQFN ADS41B29IRGZT ACTIVE VQFN ADS41B49IRGZ25 ACTIVE VQFN ADS41B49IRGZR ACTIVE VQFN ADS41B49IRGZT ACTIVE VQFN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. ...

  • Page 58

    In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold Customer on an annual basis. PACKAGE OPTION ADDENDUM Addendum-Page 2 ...

  • Page 59

    ... TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing ADS41B29IRGZR VQFN RGZ ADS41B29IRGZT VQFN RGZ ADS41B49IRGZR VQFN RGZ ADS41B49IRGZT VQFN RGZ PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 48 2500 330.0 16.4 7.3 48 250 330 ...

  • Page 60

    ... Device Package Type ADS41B29IRGZR VQFN ADS41B29IRGZT VQFN ADS41B49IRGZR VQFN ADS41B49IRGZT VQFN PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) RGZ 48 2500 RGZ 48 250 RGZ 48 2500 RGZ 48 250 Pack Materials-Page 2 10-Mar-2012 Width (mm) Height (mm) 336.6 336.6 28.6 336.6 336 ...

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    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...