IC BUS BUFF TRI-ST N-INV SC705

 

SN74LVC1G125DCKR

Manufacturer Part NumberSN74LVC1G125DCKR
DescriptionIC BUS BUFF TRI-ST N-INV SC705
ManufacturerTexas Instruments
Series74LVC
SN74LVC1G125DCKR datasheets

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Specifications of SN74LVC1G125DCKR

Logic TypeBuffer/Line Driver, Non-InvertingNumber Of Elements1
Number Of Bits Per Element1Current - Output High, Low32mA, 32mA
Voltage - Supply1.65 V ~ 5.5 VOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / CaseSC-70-5, SC-88A, SOT-323-5, SOT-353, 5-TSSOP
Logic Family74LVCNumber Of Channels Per ChipSingle
PolarityNon-InvertingSupply Voltage (max)5.5 V
Supply Voltage (min)1.65 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTHigh Level Output Current- 32 mA
Low Level Output Current32 mAMinimum Operating Temperature- 40 C
Output Type3-StatePropagation Delay Time4.5 ns @ 3.3 V or 4 ns @ 5 V
Number Of Lines (input / Output)1 / 1Lead Free Status / RoHS StatusLead free / RoHS Compliant
Other names296-11604-2  
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PARAMETER MEASUREMENT INFORMATION
S1
R
From Output
L
Under Test
C
L
R
(see Note A)
L
LOAD CIRCUIT
V
CC
V
V
1.8 V
±
0.15 V
CC
V
2.5 V
0.2 V
±
CC
3.3 V
±
0.3 V
3 V
5 V
0.5 V
V
±
CC
t
W
Input
V
V
M
VOLTAGE WAVEFORMS
PULSE DURATION
V
V
Input
M
M
t
PLH
V
Output
M
t
PHL
V
Output
M
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
D. The outputs are measured one at a time, with one transition per measurement.
E. t
and t
are the same as t .
PLZ
PHZ
dis
F. t
and t
are the same as t .
PZL
PZH
en
G. t
and t
are the same as t .
PLH
PHL
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
V
LOAD
Open
GND
INPUTS
V
V
M
LOAD
t /t
I
r
f
£2 ns
V
/2
2 × V
15 pF
CC
CC
£2 ns
V
/2
2 × V
15 pF
CC
CC
£2.5 ns
1.5 V
6 V
15 pF
£2.5 ns
V
/2
2 × V
15 pF
CC
CC
Timing Input
V
I
Data Input
M
0 V
V
I
Output
Control
0 V
t
t
PHL
Output
V
OH
Waveform 1
V
M
S1 at V
V
LOAD
OL
(see Note B)
t
t
PLH
V
Output
OH
Waveform 2
V
M
S1 at GND
V
OL
(see Note B)
Submit Documentation Feedback
SN74LVC1G125
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES223O – APRIL 1999 – REVISED FEBRUARY 2007
TEST
S1
t /t
Open
PLH
PHL
t /t
V
PLZ
PZL
LOAD
t /t
GND
PHZ
PZH
C
R
V
L
L
D
1 MW
0.15 V
1 MW
0.15 V
1 MW
0.3 V
1 MW
0.3 V
V
I
V
M
0 V
t
t
su
h
V
I
V
V
M
M
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
V
M
M
0 V
t
PZL
PLZ
V
LOAD
V
M
V + V
OL
D
V
OL
t
PZH
PHZ
V
V – V
OH
OH
D
V
M
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
£
10 MHz, Z = 50 .
W
O
/2
7

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