The ADS5474 is a 14-bit, 400-MSPS analog-to-digital converter (ADC) that operates from both a 5-V supply and 3

ADS5474

Manufacturer Part NumberADS5474
DescriptionThe ADS5474 is a 14-bit, 400-MSPS analog-to-digital converter (ADC) that operates from both a 5-V supply and 3
ManufacturerTexas Instruments
ADS5474 datasheet
 


Specifications of ADS5474

Resolution(bits)14Sample Rate (max)(sps)400MSPS
# Input Channels1Snr(db)70.2
Sfdr(db)86Power Consumption(typ)(mw)2500
Operating Temperature Range(c)-40 to 85InterfaceParallel LVDS
Analog Voltage Av/dd(min)(v)4.75Analog Voltage Av/dd(max)(v)5.25
Digital Supply(min)(v)3Digital Supply(max)(v)3.6
ArchitecturePipelineInl(max)(+/-lsb)1
Sinad(db)68.9Enob(bits)11.2
Input Range2.2V (p-p)Reference ModeInt , Ext
Dnl(max)(+/-lsb)0.7Analog Input Bw(mhz)1440
Pin/package80HTQFP  
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14-Bit, 400-MSPS Analog-to-Digital Converter
FEATURES
1
• 400-MSPS Sample Rate
23
14-Bit Resolution, 11.2-Bits ENOB
1.4-GHz Input Bandwidth
SFDR = 80 dBc at 230 MHz and 400 MSPS
SNR = 69.8 dBFS at 230 MHz and 400 MSPS
2.2-V
Differential Input Voltage
PP
LVDS-Compatible Outputs
Total Power Dissipation: 2.5 W
Power Down Mode: 50 mW
Offset Binary Output Format
Output Data Transitions on the Rising and
Falling Edges of a Half-Rate Output Clock
On-Chip Analog Buffer, Track-and-Hold, and
Reference Circuit
DESCRIPTION
The ADS5474 is a 14-bit, 400-MSPS analog-to-digital converter (ADC) that operates from both a 5-V supply and
3.3-V supply while providing LVDS-compatible digital outputs. This ADC is one of a family of 12-, 13-, and 14-bit
ADCs that operate from 210 MSPS to 500 MSPS. The ADS5474 input buffer isolates the internal switching of the
onboard track and hold (T&H) from disturbing the signal source while providing a high-impedance input. An
internal reference generator is also provided to simplify the system design.
Designed with a 1.4-GHz input bandwidth for the conversion of wide-bandwidth signals that exceed 400 MHz of
input frequency at 400 MSPS, the ADS5474 has outstanding low-noise performance and spurious-free dynamic
range over a large input frequency range.
The ADS5474 is available in an TQFP-80 PowerPAD package. The device is built on Texas Instruments
complementary bipolar process (BiCom3) and is specified over the full industrial temperature range (–40°C to
+85°C).
VIN
A1
TH1
VIN
ADC1
VREF
Reference
CLK
Timing
CLK
OVR
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
2
All other trademarks are the property of their respective owners.
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Check for Samples:
ADS5474
TQFP-80 PowerPAD™ Package
(14 mm × 14 mm footprint)
Industrial Temperature Range:
–40°C to +85°C
Pin-Similar/Compatible with 12-, 13-, and 14-Bit
Family:
ADS5463
APPLICATIONS
Test and Measurement Instrumentation
Software-Defined Radio
Data Acquisition
Power Amplifier Linearization
Communication Instrumentation
Radar
+
S
TH2
A2
DAC1
ADC2
5
Digital Error Correction
OVR
DRY
DRY
D[13:0]
ADS5474
SLAS525B – JULY 2007 – REVISED FEBRUARY 2012
and
ADS5440/ADS5444
+
S
TH3
A3
ADC3
DAC2
5
Copyright © 2007–2012, Texas Instruments Incorporated
6

ADS5474 Summary of contents

  • Page 1

    ... LVDS-compatible digital outputs. This ADC is one of a family of 12-, 13-, and 14-bit ADCs that operate from 210 MSPS to 500 MSPS. The ADS5474 input buffer isolates the internal switching of the onboard track and hold (T&H) from disturbing the signal source while providing a high-impedance input. An internal reference generator is also provided to simplify the system design ...

  • Page 2

    ... ADS5474I (1) (1) TEST CONDITIONS PowerPAD Package in the Application Information Product Folder Link(s): ADS5474 www.ti.com (1) ORDERING TRANSPORT NUMBER MEDIA, QUANTITY ADS5474IPFP Tray, 96 ADS5474IPFPR Tape and Reel, 1000 ADS5474 UNIT –0.3 to (AVDD5 + 0.3) V –0.3 to (AVDD5 + 0.3) V ±2.5 V –0.3 to (DVDD3 + 0.3) V – ...

  • Page 3

    ... MAX 4.75 5 5.25 V 3.1 3.3 3 3.3 3 400 MSPS 0 –40 +85 °C = –40° +85°C, MIN MAX ADS5474 UNIT MIN TYP MAX 14 Bits 2 3.1 V 500 Ω 2.3 pF 1.44 GHz 100 dB 2.4 V 2.9 3.1 3.3 V –0.8 mV/°C Assured –0.99 ±0.7 1.5 LSB –3 ±1 3 LSB –11 ...

  • Page 4

    ... 651 MHz 751 MHz 999 MHz IN Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 www.ti.com = –40° +85°C, MIN MAX ADS5474 UNIT MIN TYP MAX 338 372 mA 185 201 2.5 2.797 W 50 μ ...

  • Page 5

    ... MHz 351 MHz 451 MHz 651 MHz 751 MHz 999 MHz IN Product Folder Link(s): ADS5474 ADS5474 = –40° +85°C, MIN MAX ADS5474 UNIT MIN TYP MAX dBc dBc ...

  • Page 6

    ... IN2 each tone at –16 dBFS MHz 230 MHz IN Inputs tied to common-mode PWD (pin 33) Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 www.ti.com = –40° +85°C, MIN MAX ADS5474 UNIT MIN TYP MAX 69.2 67 68.9 68.5 65.5 68.2 67.3 dBc 64.8 58.5 54 45.4 93 ...

  • Page 7

    ... Copyright © 2007–2012, Texas Instruments Incorporated N+2 N N+1 t CLKL Latency = 3.5 Clock Cycles Digital Outputs Figure 1. Timing Diagram TEST CONDITIONS – 10-pF parasitic loading to GND on each output DRY Product Folder Link(s): ADS5474 ADS5474 SLAS525B – JULY 2007 – REVISED FEBRUARY 2012 N+4 N+3 N+5 t DRY t DATA N–1 N N+1 section. = –40° +85°C, ...

  • Page 8

    ... Submit Documentation Feedback PIN CONFIGURATION PFP PACKAGE (TOP VIEW ADS5474 Product Folder Link(s): ADS5474 www.ti.com ...

  • Page 9

    ... Reference voltage input/output (2.4 V nominal). A 0.1μF capacitor from VREF to AGND is VREF 6 recommended, but not required. Copyright © 2007–2012, Texas Instruments Incorporated Table 2. TERMINAL FUNCTIONS DESCRIPTION 13-bit compatibility) Product Folder Link(s): ADS5474 ADS5474 SLAS525B – JULY 2007 – REVISED FEBRUARY 2012 Submit Documentation Feedback 9 ...

  • Page 10

    ... THD = 76.9 dBc -40 -60 -80 -100 -120 160 180 200 0 20 Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 www.ti.com SPECTRAL PERFORMANCE FFT FOR 70 MHz INPUT SIGNAL SFDR = 86.6 dBc SNR = 70.1 dBFS SINAD = 69.9 dBFS THD = 82.9 dBc 100 120 140 ...

  • Page 11

    ... THD = 54.4 dBc -40 -60 -80 -100 -120 160 180 200 0 20 Product Folder Link(s): ADS5474 ADS5474 SLAS525B – JULY 2007 – REVISED FEBRUARY 2012 SPECTRAL PERFORMANCE SFDR = 71.4 dBc SNR = 68.4 dBFS SINAD = 65.8 dBFS THD = 68.3 dBc 100 120 140 160 180 200 Frequency ...

  • Page 12

    ... MHz, 16 dBFS - IN1 MHz, 16 dBFS - IN2 IMD3 = 98 dBFS -20 SFDR = 95.7 dFBS -40 -60 -80 -100 -120 140 160 180 200 0 Product Folder Link(s): ADS5474 www.ti.com - - 100 120 140 160 180 Frequency - MHz Figure 11 297.5 MHz, 16 dBFS - IN1 f = 302.5 MHz, 16 dBFS ...

  • Page 13

    ... NOISE HISTOGRAM WITH INPUTS SHORTED 400 MSPS MHz Product Folder Link(s): ADS5474 ADS5474 f = 400 MSPS MHz IN 6144 8192 10240 12288 14336 16384 Code Figure 15 400 MSPS VCM IN Output Code Figure 17. ...

  • Page 14

    ... MHz +40 C ° -40 C ° 4.7 0 -30 -20 -10 Product Folder Link(s): ADS5474 www.ti.com AC PERFORMANCE vs SNR (dBFS) SNR (dBc 400 MSPS 230 MHz IN -80 -70 -60 -50 -40 -30 -20 -10 Input Amplitude dBFS - Figure 19. SFDR vs AVDD5 OVER TEMPERATURE ...

  • Page 15

    ... C ° ° +65 C ° +100 C ° 3.4 3.5 3.6 3.0 3 Product Folder Link(s): ADS5474 ADS5474 SLAS525B – JULY 2007 – REVISED FEBRUARY 2012 SFDR vs AVDD3 OVER TEMPERATURE +25 C +40 C ° ° +85 C ° ° +100 C ° ° 3.2 3.3 3.4 3.5 3.6 AVDD3 ...

  • Page 16

    ... Wake from 5 V Supply Time Figure 28. Product Folder Link(s): ADS5474 www.ti.com CMRR vs COMMON-MODE INPUT FREQUENCY 400 MSPS 300 MSPS 100 Frequency Hz - Figure 27. 90 100 Copyright © 2007–2012, Texas Instruments Incorporated ...

  • Page 17

    ... SNR vs INPUT FREQUENCY AND SAMPLING FREQUENCY 200 300 f Input Frequency MHz - - SNR dBFS - Figure 29. Product Folder Link(s): ADS5474 ADS5474 SLAS525B – JULY 2007 – REVISED FEBRUARY 2012 400 500 600 Submit Documentation Feedback 17 ...

  • Page 18

    ... Input Configuration The analog input for the ADS5474 consists of an analog pseudo-differential buffer followed by a bipolar transistor T&H. The analog buffer isolates the source driving the input of the ADC from any internal switching and presents a high impedance that is easy to drive at high input frequencies, compared to an ADC without a buffered input. ...

  • Page 19

    ... Bond Pad VCM AVDD5 500 W ~ 200 fF Bond Pad PP , refer to the SNR and SFDR at –6 dBFS (0 dBFS = rather than 2 Product Folder Link(s): ADS5474 ADS5474 SLAS525B – JULY 2007 – REVISED FEBRUARY 2012 Buffer 1.6 pF 1.6 pF GND Buffer S0293-01 . Operation below 2 allowable, PP Figure 18 ...

  • Page 20

    ... The component values can be tuned for different intermediate frequencies. The example shown in located on the evaluation module and is tuned for 170 MHz. More information regarding this configuration can be found in the ADS5474 EVM User Guide (SLAU194) and the THS9001 50-MHz to 350-MHz Cascadeable Amplifier data sheet (SLOS426), both available for download at www.ti.com. ...

  • Page 21

    ... In this configuration, the THS4509 amplifier circuit provides gain, converts the single-ended input to differential, and sets the proper input common-mode voltage to the ADS5474 by utilizing the VCM output pin of the ADC. The 50-Ω resistors and 18-pF capacitor between the THS4509 outputs and ADS5474 inputs (along with the input capacitance of the ADC) limit the bandwidth of the signal to about 70 MHz (– ...

  • Page 22

    ... Because it is pin-compatible important to note that the ADS5463 does not have a VCM pin and primarily uses the VREF pin to provide the common-mode voltage in dc-coupled applications. The V) and ADS5474 (VCM = 3.1V) do not have the same common-mode voltage. To create a board layout that may accommodate both devices in dc-coupled applications, route VCM and VREF both to a common point that can be selected via a switch, jumper Ω ...

  • Page 23

    ... dBFS - MHz IN 3.2 3.0 2.8 2 dBFS - IN 2.2 2.0 3.15 2.05 2.15 2.25 2.35 2. Figure 38. Total Power Consumption versus 400 MSPS MHz IN 2.05 2.15 2.25 2.35 2.45 2.55 2.65 2.75 2.85 2.95 3.05 External VREF Applied V - Product Folder Link(s): ADS5474 ADS5474 SLAS525B – JULY 2007 – REVISED FEBRUARY 2012 2.55 2.65 2.75 2.85 2.95 3.05 3.15 External VREF Applied - V External VREF 3.15 Submit Documentation Feedback 23 ...

  • Page 24

    ... ADS5474 SLAS525B – JULY 2007 – REVISED FEBRUARY 2012 Clock Inputs The ADS5474 clock input can be driven with either a differential clock signal or a single-ended clock input. The characterization of the ADS5474 is typically performed with a 3-V with a differential clock amplitude down to ~0 factor in performance as the analog input frequency increases. In low-input-frequency applications, where jitter may not be a big concern, the use of a single-ended clock could save cost and board space without much performance tradeoff. When clocked with this configuration best to connect CLK to ground with a 0.01-μ ...

  • Page 25

    ... See also Clocking High Speed Data Converters (SLYT075) for more details. The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-kΩ resistors recommended to use ac coupling, but if this scheme is not possible, the ADS5474 features good tolerance to clock common-mode variation (as shown in both edges of the clock for the conversion process ...

  • Page 26

    ... The ADS5474 is capable of achieving 69.2 dBFS SNR at 350 MHz of analog input frequency. In order to achieve the SNR at 350 MHz the clock source rms jitter must be at least 144 fsec in order for the total rms jitter to be 177 fsec. A summary of maximum recommended rms clock jitter as a function of analog input frequency is provided ...

  • Page 27

    ... VCXO selected, as well as the CDCM7005, and typically has 50–100 fs of rms jitter determined that the jitter from the CDCM7005 with a VCXO is sufficient without further conditioning possible to clock the ADS5474 directly from the CDCM7005 using differential LVPECL outputs, as illustrated in (see the CDCM7005 data sheet for the exact schematic) ...

  • Page 28

    ... DRY could invert when power is cycled off/on or when the power-down pin is cycled. Data capture from the transition and not the polarity of DRY is recommended, but not required. If the synchronization of multiple ADS5474 devices is required, it might be necessary to use a form of the CLKIN signal rather than DRY to capture the data. ...

  • Page 29

    ... Power Supplies The ADS5474 uses three power supplies. For the analog portion of the design, a 5-V and 3.3-V supply (AVDD5 and AVDD3) are used, while the digital portion uses a 3.3-V supply (DVDD3). The use of low-noise power supplies with adequate decoupling is recommended. Linear supplies are preferred to switched supplies; switched supplies tend to generate more noise components that can be coupled to the ADS5474 ...

  • Page 30

    ... W of normal power dissipation maximum ambient of +85°C with no airflow, the junction temperature of the ADS5474 reaches approximately +85°C + 23.7°C/W × 2 +144°C. Being even more conservative and accounting for the maximum possible power dissipation that is ensured (2.797 W), the junction temperature becomes nearly +150° ...

  • Page 31

    ... The evaluation board represents a good model of how to lay out the printed circuit board (PCB) to obtain the maximum performance from the ADS5474. Follow general design rules, such as the use of multilayer boards, a single ground plane for ADC ground connections, and local decoupling ceramic chip capacitors. The analog input traces should be isolated from any external source of interference or noise, including the digital outputs as well as the clock traces ...

  • Page 32

    ... IMD3 is given in units of either dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 www.ti.com ), excluding the power ...

  • Page 33

    ... Changed (where DRY equals the CLK frequency) to (where DRY equals ½ the CLK frequency) in Digital Outputs section ................................................................................................................................................................................. Copyright © 2007–2012, Texas Instruments Incorporated SLAS525B – JULY 2007 – REVISED FEBRUARY 2012 REVISION HISTORY Product Folder Link(s): ADS5474 ADS5474 Page 3 28 Submit Documentation Feedback 33 ...

  • Page 34

    ... ADS5474IPFP ACTIVE ADS5474IPFPG4 ACTIVE ADS5474IPFPR ACTIVE ADS5474IPFPRG4 ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design ...

  • Page 35

    ... TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing ADS5474IPFPR HTQFP PFP PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 80 1000 330.0 24.4 15.0 Pack Materials-Page 1 2-Sep-2009 Pin1 (mm) (mm) (mm) (mm) Quadrant 15.0 1.5 20.0 24.0 Q2 ...

  • Page 36

    ... Device Package Type ADS5474IPFPR HTQFP PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) PFP 80 1000 Pack Materials-Page 2 2-Sep-2009 Width (mm) Height (mm) 346.0 346.0 41.0 ...

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    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...