ADS614X (ADS612X) is a family of 14-bit (12-bit) A/D converters with sampling rates up to 250 MSPS

ADS6149

Manufacturer Part NumberADS6149
DescriptionADS614X (ADS612X) is a family of 14-bit (12-bit) A/D converters with sampling rates up to 250 MSPS
ManufacturerTexas Instruments
ADS6149 datasheet
 


Specifications of ADS6149

Resolution(bits)14Sample Rate (max)(sps)250MSPS
# Input Channels1Snr(db)72.7
Sfdr(db)86Power Consumption(typ)(mw)687
Operating Temperature Range(c)-40 to 85InterfaceParallel LVDS, Serial SPI Interface, Parallel CMOS
Analog Voltage Av/dd(min)(v)3Analog Voltage Av/dd(max)(v)3.6
Digital Supply(min)(v)1.7Digital Supply(max)(v)1.9
ArchitecturePipelineInl(max)(+/-lsb)5
Sinad(db)72.4Enob(bits)11.73
Input Range2V (p-p)Reference ModeInt , Ext
Dnl(max)(+/-lsb)2Analog Input Bw(mhz)700
Pin/package48VQFN  
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.....................................................................................................................................................
14/12-Bit, 250/210 MSPS ADCs With DDR LVDS and Parallel CMOS Outputs
FEATURES
1
Maximum Sample Rate: 250 MSPS
14-Bit Resolution – ADS614X
12-Bit Resolution – ADS612X
687 mW Total Power Dissipation at 250 MSPS
Double Data Rate (DDR) LVDS and Parallel
CMOS Output Options
Programmable Fine Gain up to 6dB for
SNR/SFDR Trade-Off
DC Offset Correction
Supports Input Clock Amplitude Down to 400
mV
Differential
PP
Internal and External Reference Support
48-QFN Package (7mm × 7mm)
Pin Compatible with ADS5547 Family
APPLICATIONS
Multicarrier, Wide Band-Width
Communications
Wireless Multi-carrier Communications
Infrastructure
Software Defined Radio
Power Amplifier Linearization
802.16d/e
Test and Measurement Instrumentation
High Definition Video
Medical Imaging
Radar Systems
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008
DESCRIPTION
ADS614X (ADS612X) is a family of 14-bit (12-bit) A/D
converters with sampling rates up to 250 MSPS. It
combines high dynamic performance and low power
consumption in a compact 48 QFN package. This
makes it well-suited for multicarrier, wide band-width
communications applications.
ADS614X/2X has fine gain options that can be used
to improve SFDR performance at lower full-scale
input ranges. It includes a dc offset correction loop
that can be used to cancel the ADC offset. Both DDR
LVDS (Double Data Rate) and parallel CMOS digital
output interfaces are available. At lower sampling
rates, the ADC automatically operates at scaled down
power with no loss in performance.
It includes internal references while the traditional
reference pins and associated decoupling capacitors
have been eliminated. Nevertheless, the device can
also be driven with an external reference. The device
is specified over the industrial temperature range
(–40°C to 85°C).
250 MSPS
ADS614X
ADS6149
14-Bit Family
ADS612X
ADS6129
12-Bit Family
Copyright © 2008, Texas Instruments Incorporated
210 MSPS
ADS6148
ADS6128

ADS6149 Summary of contents

  • Page 1

    ... Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C). 250 MSPS ADS614X ADS6149 14-Bit Family ADS612X ADS6129 12-Bit Family Copyright © 2008, Texas Instruments Incorporated 210 MSPS ...

  • Page 2

    ... Sample and Hold INM VCM ADS6149/48 2 Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... CLOCKGEN DDR 14-Bit ADC Serializer Control Reference Interface ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com DDR LVDS Interface CLKOUTP CLKOUTM D0_D1_P D0_D1_M D2_D3_P D2_D3_M D4_D5_P D4_D5_M D6_D7_P D6_D7_M D8_D9_P D8_D9_M D10_D11_P D10_D11_M ...

  • Page 3

    ... VCM ADS6129/28 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): CLOCKGEN DDR 12-Bit ADC Serializer Control Reference Interface ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 DDR LVDS Interface CLKOUTP CLKOUTM D0_D1_P D0_D1_M D2_D3_P D2_D3_M D4_D5_P ...

  • Page 4

    ... PACKAGE/ORDERING INFORMATION SPECIFIED LEAD/BALL TEMPERATURE FINISH RANGE –40°C to 85°C Cu NiPdAu –40°C to 85°C Cu NiPdAu (1) (2) , RESET, SCLK, SDATA, SEN, DFS and ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com (1) (2) PACKAGE ORDERING TRANSPORT MARKING NUMBER MEDIA, QUANTITY ADS6149IRGZR AZ6149 ADS6149IRGZT Tape and reel ...

  • Page 5

    ... Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SLWS211B – JULY 2008 – REVISED OCTOBER 2008 (1) input amplitude PP (1) input amplitude PP ADS6149 / ADS6129 ADS6148 / ADS6128 Sine wave, ac-coupled LVPECL, ac-coupled LVDS, ac-coupled LVCMOS, single-ended, ac-coupled ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 MIN ...

  • Page 6

    ... Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... = –40° MIN MAX ADS6149/ADS6129 250 MSPS MIN Figure 97 Figure 98 –15 –1.25 (1) , (2) , 10-pF external ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com = 85°C, AVDD = 3.3 V, DRVDD = 1.8 V ADS6148/ADS6128 210 MSPS TYP MAX MIN TYP MAX 2 2 >1 >1 3.5 3.5 700 700 2 2 A/MSPS 1 ...

  • Page 7

    ... ELECTRICAL CHARACTERISTICS – ADS6149 and ADS6148 Typical values are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode unless otherwise noted. Min and max values are across the full temperature range T PARAMETER SNR ...

  • Page 8

    ... AC power supply rejection ratio 8 Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... = –40° MIN MAX ADS6149/ADS6129 250 MSPS MIN signal on AVDD supply PP ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com = 85°C, AVDD = 3.3 V, DRVDD = 1.8 V ADS6148/ADS6128 210 MSPS TYP MAX MIN TYP MAX ...

  • Page 9

    ... VHIGH = 3.3V VHIGH = 3.3V VLOW = 0V VLOW = 0V (4) Capacitance inside the device, from either output to ground Logic 0 ( –350 mV ODL Figure 1. LVDS Voltage Levels ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ADS6149/ADS6148/ ADS6129/ADS6128 UNIT MIN TYP MAX 1 ...

  • Page 10

    ... MSPS ≤ Sampling frequency ≤ 250 MSPS Rise time measured from 20% to 80% of DRVDD, Fall time measured from 80% to 20% of DRVDD, 1 MSPS ≤ Sampling frequency ≤ 150 MSPS Time to valid data after OE becomes active ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com = 85°C, AVDD = 3.3V, DRVDD = 1.7V to MIN TYP MAX 0 ...

  • Page 11

    ... Timings specified with respect to input clock START MIN TYP MAX 1.7 0.4 5.1 4.8 Timings specified with respect to CLKOUT SETUP TIME, ns MIN TYP MAX 2.0 3.2 2.9 4 5.0 Submit Documentation Feedback ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 HOLD TIME, ns MIN TYP MAX 0.4 0.8 0.5 0.9 0.7 1.1 0.9 1.2 1.1 1.4 2.0 ( PDI MIN TYP MAX 8.2 DATA VALID TIME, ns ...

  • Page 12

    ... ADC latency is 14 clock cycles in low-latency mode. 12 Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... N+4 N+3 N+2 18 Clock Cycles N–17 N–16 N–15 18 Clock Cycles* N–17 N–16 N–15 N–14 Figure 2. Latency Diagram ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com N+20 N+19 N+ PDI N+1 N+2 t PDI t ...

  • Page 13

    ... Bits D0, D2, D4,... Figure 3. LVDS Mode Timing CLKM CLKP t PDI CLKOUT Dn* CLKM CLKP t START t Dn Dn* Figure 4. CMOS Mode Timing ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 t PDI (2) Dn+1 T0106- T0107-05 Submit Documentation Feedback 13 ...

  • Page 14

    ... CONTROLS MODES Data format and LVDS/CMOS output interface. Internal or external reference, low speed mode enable CLKOUT edge programmability. Global power-down (ADC, internal references and output buffers are powered down) ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com Table 3 to Copyright © 2008, Texas Instruments Incorporated ...

  • Page 15

    ... Table 3. SDATA – DIGITAL CONTROL PIN DESCRIPTION Table 4. SEN – ANALOG CONTROL PIN DESCRIPTION – Output Clock Edge Programmability Table 5. DFS – ANALOG CONTROL PIN DESCRIPTION ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 (1) Submit Documentation Feedback ...

  • Page 16

    ... This initializes internal registers to their default values and then self-resets the <RESET> bit to LOW. In this case the RESET pin is kept LOW. 16 Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... Table 6. MODE – ANALOG CONTROL PIN DESCRIPTION (5/8) AVDD GND (3/8) AVDD ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com AVDD To Parallel Pin S0321-01 th SCLK falling edge Copyright © 2008, Texas Instruments Incorporated ...

  • Page 17

    ... To enable register writes, reset register bit <SERIAL READOUT> Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): Register Address (SCLK) Figure 6. Serial Interface Timing PARAMETER ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 Register Data (DH) ...

  • Page 18

    ... Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... Register Data (D7:D0 (Don't Care Figure 7. Serial Readout ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com Register Data (D7:D0) = 0x01 Copyright © 2008, Texas Instruments Incorporated ...

  • Page 19

    ... Output interface <CLKOUT POSN> Output clock position control <CUSTOM PATTERN LOW> 0 ENABLE OFFSET CORR> <FINE GAIN > ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 MIN TYP MAX 100 t 3 T0108-01 ( < ...

  • Page 20

    ... DDR LVDS interface 11 Parallel CMOS interface 20 Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... <RESET> 0 Software Reset <REF> ADS6149/ADS6129 ADS6148/ADS6128 <ENABLE 0 LOW SPEED 0 MODE> <PDN 0 <STANDBY> GLOBAL> Copyright © ...

  • Page 21

    ... POSN> Output clock position control <DATA FORMAT> 2s complement or offset binary <Custom Pattern> ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 <Custom Pattern> Submit Documentation Feedback D0 0 ...

  • Page 22

    ... Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... D6 <ENABLE OFFSET CORR> Offset correction enable <FINE GAIN> ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com <OFFSET CORR TC> Offset correction time constant Copyright © 2008, Texas Instruments Incorporated ...

  • Page 23

    ... ADS6129/8: Output data <D11:D0> alternates between 101010101010 and 010101010101 every clock cycle. 100 Outputs digital ramp ADS6149/8: Output data increments by one LSB (14-bit) every clock cycle from code 0 to code 16383 ADS6129/8: Output data increments by one LSB (124-bit) every 4 101 Outputs custom pattern as specified in registers 0x51 and 0x52. ...

  • Page 24

    ... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 DRGND DRVDD OVR_SDOUT CLKOUTM CLKOUTP DFS OE AVDD AGND CLKP CLKM AGND Figure 9. PIN CONFIGURATION (LVDS MODE) — ADS6149/48 DRGND DRVDD OVR_SDOUT CLKOUTM CLKOUTP DFS OE AVDD AGND CLKP CLKM AGND Figure 10. PIN CONFIGURATION (LVDS MODE) — ADS6129/28 ...

  • Page 25

    ... Table 8. PIN ASSIGNMENTS (LVDS MODE) — ADS6149/48 and ADS6129/28 PIN NO. I/O of NAME NO. PINS 8, 18, 20, AVDD I 6 3.3-V Analog power supply 22, 24 12, 14, AGND I 6 Analog ground 17, 19, 25 CLKP, CLKM 10 Differential clock input INP, INM 15 Differential analog input Internal reference mode – ...

  • Page 26

    ... ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 Table 8. PIN ASSIGNMENTS (LVDS MODE) — ADS6149/48 and ADS6129/28 (continued) PIN NO. I/O of NAME NO. PINS DRVDD 1.8 V Digital and output buffer supply DRGND 1, 36, PAD I 2 Digital and output buffer ground ...

  • Page 27

    ... DRGND DRVDD OVR_SDOUT UNUSED CLKOUT DFS OE AVDD AGND CLKP CLKM AGND Figure 11. PIN CONFIGURATION (CMOS MODE) – ADS6149/48 DRGND DRVDD OVR_SDOUT UNUSED CLKOUT DFS OE AVDD AGND CLKP CLKM AGND Figure 12. PIN CONFIGURATION (CMOS MODE) – ADS6129/28 Copyright © 2008, Texas Instruments Incorporated ...

  • Page 28

    ... ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 PIN ASSIGNMENTS (CMOS MODE) – ADS6149/48 and ADS6129/28 PIN NO. of I/O PINS NAME NO. 8, 18, 20, AVDD I 6 22, 24 12, 14, AGND I 6 17, 19, 25 CLKP, CLKM 10 INP, INM 15 VCM ...

  • Page 29

    ... TYPICAL CHARACTERISTICS - ADS6149 All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode gain, LVDS output interface, 32K point FFT (unless otherwise noted) ...

  • Page 30

    ... ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 TYPICAL CHARACTERISTICS - ADS6149 (continued) All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode gain, ...

  • Page 31

    ... TYPICAL CHARACTERISTICS - ADS6149 (continued) All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode gain, LVDS output interface, 32K point FFT (unless otherwise noted) ...

  • Page 32

    ... ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 TYPICAL CHARACTERISTICS - ADS6149 (continued) All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode gain, ...

  • Page 33

    ... G024 ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 FFT for 60 MHz INPUT SIGNAL 100 f − Frequency − MHz Figure 33. FFT for 300 MHz INPUT SIGNAL ...

  • Page 34

    ... Input adjusted to get −1dBFS input G028 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com SNR vs INPUT FREQUENCY LVDS CMOS 100 150 200 250 300 350 400 450 500 f − Input Frequency − MHz IN Figure 39. SINAD vs GAIN 2 dB ...

  • Page 35

    ... SFDR 3.5 3.6 3.7 1.6 G032 ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 PERFORMANCE vs INPUT COMMON-MODE VOLTAGE SFDR SNR 1.45 1.50 1.55 1.60 1.65 − Common-Mode Voltage of Analog Inputs − V Figure 43. PERFORMANCE vs DRVDD SUPPLY SFDR SNR 1.7 1.8 1.9 2 ...

  • Page 36

    ... G036 OUTPUT NOISE HISTOGRAM 40 RMS (LSB 8203 8204 8205 8206 8207 8208 8209 8210 8211 8212 Output Code Figure 50. ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com PERFORMANCE vs INPUT CLOCK AMPLITUDE SFDR SNR 0.70 1.20 1.70 2.20 Input Clock Amplitude − Figure 47. PERFORMANCE vs VCM VOLTAGE ...

  • Page 37

    ... SFDR = –97 dBFS −40 −60 −80 −100 −120 −140 −160 100 125 0 G043 ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 FFT for 60 MHz INPUT SIGNAL 100 f − Frequency − MHz Figure 52. FFT for 300 MHz INPUT SIGNAL SFDR = 76 ...

  • Page 38

    ... Input adjusted to get −1dBFS input G047 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com SNR vs INPUT FREQUENCY LVDS CMOS 100 150 200 250 300 350 400 450 500 f − Input Frequency − MHz IN Figure 58. SINAD vs GAIN 0 dB ...

  • Page 39

    ... MHz 3 1.6 3.5 3.6 3.7 G051 ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 PERFORMANCE vs INPUT COMMON-MODE VOLTAGE 74 73 SFDR 72 71 SNR 70 69 1.45 1.50 1.55 1.60 1.65 Figure 62. PERFORMANCE vs DRVDD SUPPLY SFDR ...

  • Page 40

    ... G055 OUTPUT NOISE HISTOGRAM 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 Output Code Figure 69. ADS6149/ADS6129 ADS6148/ADS6128 PERFORMANCE vs INPUT CLOCK AMPLITUDE SFDR SNR 0.70 1.20 1.70 2.20 2.70 Input Clock Amplitude − Figure 66. PERFORMANCE vs VCM VOLTAGE SFDR SNR 1 ...

  • Page 41

    ... G062 ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 FFT for 60 MHz INPUT SIGNAL 100 f − Frequency − MHz Figure 71. FFT for 300 MHz INPUT SIGNAL ...

  • Page 42

    ... Input adjusted to get −1dBFS input G066 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com SNR vs INPUT FREQUENCY LVDS CMOS 100 150 200 250 300 350 400 450 500 f − Input Frequency − MHz IN Figure 77. SINAD vs GAIN 0 dB ...

  • Page 43

    ... SFDR 3.5 3.6 3.7 1.6 G070 ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 PERFORMANCE vs INPUT COMMON-MODE VOLTAGE SFDR SNR 1.45 1.50 1.55 1.60 1.65 − Common-Mode Voltage of Analog Inputs − V Figure 81. PERFORMANCE vs DRVDD SUPPLY SFDR SNR 1.7 1.8 1.9 2 ...

  • Page 44

    ... G074 OUTPUT NOISE HISTOGRAM 2048 2049 2050 2051 2052 2053 2054 2055 2056 Output Code Figure 88. ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com PERFORMANCE vs INPUT CLOCK AMPLITUDE SFDR SNR 0.70 1.20 1.70 2.20 Input Clock Amplitude − Figure 85. PERFORMANCE vs VCM VOLTAGE SFDR SNR 1 ...

  • Page 45

    ... CMOS Disabled 100 150 f − Sampling Frequency − MSPS S Figure 91. ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 TOTAL POWER vs SAMPLING FREQUENCY = LVDS CMOS 50 100 150 200 f − Sampling Frequency − MSPS S Figure 90 ...

  • Page 46

    ... ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 CONTOUR PLOTS - ADS6149/ADS6148/ADS6129/ADS6128 Plots are at 25°C, AVDD = 3.3V, DRVDD = 1.8 V, sine wave input clock, 1.5 V cycle, –1 dBFS differential analog input, internal reference mode gain, LVDS output interface (unless otherwise noted) 250 ...

  • Page 47

    ... CONTOUR PLOTS - ADS6149/ADS6148 Plots are at 25°C, AVDD = 3.3V, DRVDD = 1.8 V, sine wave input clock, 1.5 V cycle, –1 dBFS differential analog input, internal reference mode gain, LVDS output interface (unless otherwise noted) 250 240 73 220 72 200 180 73 160 140 120 73 100 ...

  • Page 48

    ... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 THEORY OF OPERATION ADS6149/48 and ADS6129/ family of high performance, low power 14-bit and 12-bit pipeline A/D converters with maximum sampling rate up to 250 MSPS. At every rising edge of the input clock, the analog input signal is sampled and sequentially converted by a pipeline of low resolution stages ...

  • Page 49

    ... Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): Figure 98 show the impedance (Zin = Rin || Cin) looking into the ADC input 200 300 400 500 600 f - Frequency - MHz ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 Figure 99 and Figure 100). 700 800 ...

  • Page 50

    ... Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... 200 300 400 500 600 700 f - Frequency - MHz Figure 99 Figure 100), the capacitance used in the R-C-R is ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com 800 900 1000 and Figure 100 – one optimized for low Copyright © 2008, Texas Instruments Incorporated ...

  • Page 51

    ... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 1:1 0 ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 15 W INP INM 15 W VCM INP INM VCM Equation 1 describes the (1) Submit Documentation Feedback 51 ...

  • Page 52

    ... This allows using transformer-coupled drive circuits for sine wave clock or ac-coupling for LVPECL, LVDS clock sources. 52 Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... INTREF EXTREF Figure 101. Reference Section Equation 2. ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com Internal Reference REFM REFP S0165-09 Copyright © 2008, Texas Instruments Incorporated (2) ...

  • Page 53

    ... VCM 5 kW Ceq ~ pF, equivalent input capacitance of clock buffer Figure 102. Internal Clock Buffer CMOS Clock Input S0167-10 Figure 104. Single-Ended Clock Driving Circuit ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 Clock buffer Ceq 0 ...

  • Page 54

    ... Time constant (TCCLK), number of clock cycles 256 k 512 128 M 256 M 512 M RESERVED RESERVED RESERVED RESERVED ADS6149/ADS6129 ADS6148/ADS6128 Full-Scale 1.78 1.59 1.42 1.26 1.12 1.00 Time constant, sec (=TCCLK x 1/Fs) ( 134 ms 268 ms 536 ms 1 ...

  • Page 55

    ... Product Folder Link(s): Offset Correction Disabled Offset Correction Enabled Output Data With 36 LSB Offset − Time − s ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 Output Data With Offset Corrected G080 ...

  • Page 56

    ... Data bits D0, D1 Data bits D2, D3 Data bits D4 bit ADC data Data bits D6, D7 Data bits D8, D9 Data bits D10, D11 Data bits D12, D13 ADS612X ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com Pins CLKOUTP Output Clock CLKOUTM D0_D1_P Data bits D0, D1 D0_D1_M ...

  • Page 57

    ... D10 D11 D10 D10_D11_M D12_D13_P, D12 D13 D12 D12_D13_M Sample N Sample N+1 Figure 108. DDR LVDS Interface Figure ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 D11 D13 T0110-01 109. The buffer is designed to present an Submit Documentation Feedback ...

  • Page 58

    ... These timings can be used to delay the input clock appropriately and use it to capture the data (see 58 Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com OUTP External 100- Load W ...

  • Page 59

    ... Product Folder Link(s): Pins OVR_SDOUT CLKOUT • • • 14-Bit ADC Data D11 D12 D13 ADS614x Figure 110. CMOS Output Interface × DRVDD × (N × ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ), AVG Submit Documentation Feedback 59 ...

  • Page 60

    ... So necessary to solder the exposed pad to the ground plane for best thermal and electrical performance. For detailed information, see the application notes for QFN Layout Guidelines (SLOA122) and QFN/SON PCB Attachment (SLUA271). 60 Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com Copyright © 2008, Texas Instruments Incorporated ...

  • Page 61

    ... E TOTAL GREF calculated by dividing the maximum deviation MIN MAX range by the difference T –T MAX MAX ) and distortion (P N ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 GREF + E . GCHAN 0.5/100 ideal ideal . MIN ...

  • Page 62

    ... It is typically expressed in dBc. 62 Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... is the change in supply voltage and ΔVout is the resultant change of the SUP ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ( the power of the S (6) (7) OUT (8) Copyright © ...

  • Page 63

    ... ADS6148IRGZ25 ACTIVE VQFN ADS6148IRGZR ACTIVE VQFN ADS6148IRGZRG4 ACTIVE VQFN ADS6148IRGZT ACTIVE VQFN ADS6148IRGZTG4 ACTIVE VQFN ADS6149IRGZ25 ACTIVE VQFN ADS6149IRGZR ACTIVE VQFN Pins Package Qty (2) Eco Plan Drawing Ball Finish RGZ 48 25 Green (RoHS CU NIPDAU Level-3-260C-168 HR & no Sb/Br) RGZ 48 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR & ...

  • Page 64

    ... Status ADS6149IRGZRG4 ACTIVE VQFN ADS6149IRGZT ACTIVE VQFN ADS6149IRGZTG4 ACTIVE VQFN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. ...

  • Page 65

    ... Type Drawing ADS6128IRGZR VQFN RGZ ADS6128IRGZT VQFN RGZ ADS6129IRGZR VQFN RGZ ADS6129IRGZT VQFN RGZ ADS6148IRGZR VQFN RGZ ADS6148IRGZT VQFN RGZ ADS6149IRGZR VQFN RGZ ADS6149IRGZT VQFN RGZ PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 48 2500 330.0 16.4 7.3 48 250 330.0 16.4 7 ...

  • Page 66

    ... Device Package Type ADS6128IRGZR VQFN ADS6128IRGZT VQFN ADS6129IRGZR VQFN ADS6129IRGZT VQFN ADS6148IRGZR VQFN ADS6148IRGZT VQFN ADS6149IRGZR VQFN ADS6149IRGZT VQFN PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) RGZ 48 2500 RGZ 48 250 RGZ 48 2500 RGZ 48 250 ...

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  • Page 70

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...