The ADS7882 is a 12-bit 3-MSPS A-to-D converter with 2

ADS7882

Manufacturer Part NumberADS7882
DescriptionThe ADS7882 is a 12-bit 3-MSPS A-to-D converter with 2
ManufacturerTexas Instruments
ADS7882 datasheet
 


Specifications of ADS7882

Resolution(bits)12Sample Rate (max)(sps)3MSPS
# Input Channels1InterfaceParallel CMOS
Dnl(max)(+/-lsb)4Inl(max)(+/-lsb)4
Inl (+/-)(max)(%)0.09800Snr(db)71.5
Sinad(db)68.5Input RangeVref
Power Consumption(typ)(mw)85Reference ModeInt , Ext
ArchitectureSARAnalog Voltage Av/dd(min)(v)4.75
Analog Voltage Av/dd(max)(v)5.25Digital Supply(min)(v)2.7
Digital Supply(max)(v)5.25Operating Temperature Range(c)-40 to 85
Pin/package48TQFPIntegrated FeaturesInternal Reference
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...........................................................................................................................................................................................
LOW POWER SAR ANALOG-TO-DIGITAL CONVERTER
FEATURES
1
3-MHz Sample Rate, 12-Bit Resolution
Zero Latency
Unipolar, Pseudo Differential Input, Range:
– 0 V to 2.5 V
High-Speed Parallel Interface
69.5 dB SNR at 100 kHz I/P
Power Dissipation 85 mW at 3 MSPS
Nap Mode (10 mW Power Dissipation)
Power Down (10 W)
Internal Reference
Internal Reference Buffer
48-Pin TQFP Package
APPLICATIONS
Optical Networking (DWDM, MEMS Based
Switching)
Spectrum Analyzers
High Speed Data Acquisition Systems
High Speed Close-Loop Systems
Telecommunication
Ultra-Sound Detection
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
12-BIT, 3-MSPS
DESCRIPTION
The ADS7882 is a 12-bit 3-MSPS A-to-D converter
with 2.5-V internal reference. The device includes a
capacitor based SAR A/D converter with inherent
sample and hold. The device offers a 12-bit parallel
interface with an additional byte mode that provides
easy interface with 8-bit processors. The device has
a pseudo-differential input stage.
The –IN swing of ±200 mV is useful to compensate
for ground voltage mismatch between the ADC and
sensor and also to cancel common-mode noise. With
nap mode enabled, the device operates at lower
power when used at lower conversion rates. The
device is available in 48-pin TQFP package.
SAR
+IN
+
CDAC
_
−IN
Comparator
REFIN
CLOCK
REFOUT
Internal
Reference
Copyright © 2008, Texas Instruments Incorporated
ADS7882
SLAS630 – DECEMBER 2008
BYTE
Output
Latches
and
3-State
Drivers
12/8-Bit Parallel
Data Output Bus
CONVST
Conversion
BUSY
and
CS
Control Logic
2.5 V
RD
PWD/RST
A_PWD

ADS7882 Summary of contents

  • Page 1

    ... Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 12-BIT, 3-MSPS DESCRIPTION The ADS7882 is a 12-bit 3-MSPS A-to-D converter with 2.5-V internal reference. The device includes a capacitor based SAR A/D converter with inherent sample and hold. The device offers a 12-bit parallel interface with an additional byte mode that provides easy interface with 8-bit processors ...

  • Page 2

    ... ADS7882 www.ti.com TEMPERATURE ORDERING TRANSPORT RANGE INFORMATION MEDIA QUANTITY ADS7882IPFBT Tape and reel 250 –40°C to 85°C ADS7882IPFBR Tape and reel 1000 VALUE UNIT –0.3 to +VA + 0.1 –0.3 to 0.5 –0 –0 –0.3 to (+VBD + 0.3 V) –0.3 to (+VBD + 0.3 V) – –65 to 150 ...

  • Page 3

    ... MHz/2 p-p ref V = 2.496 V at 0.1 MHz/2 p-p ref From 95% (+VA), with 1- F storage capacitor on REFOUT to AGND IOUT = 0 Static load + 5.25 V IOUT = 0 Product Folder Link(s): ADS7882 ADS7882 SLAS630 – DECEMBER 2008 MIN TYP MAX UNIT ref –0.2 V +0.2 ref V –0.2 0 ...

  • Page 4

    ... TEST CONDITIONS TTL loads TTL loads OL + From simulation results 1- F storage capacitor on REFOUT to AGND Product Folder Link(s): ADS7882 www.ti.com MIN TYP MAX UNIT CMOS +V – –3 0 –0.6 +V ...

  • Page 5

    ... All timings are measured with 20 pF equivalent loads on all data bits and BUSY pin. Copyright © 2008, Texas Instruments Incorporated (1) (2) (3) ( (10% to 90% of +VBD) and timed from a voltage level Product Folder Link(s): ADS7882 ADS7882 SLAS630 – DECEMBER 2008 MIN TYP MAX UNIT REF FIG. ...

  • Page 6

    ... Refer to the timing diagrams for more details. Active low synchronization pulse for the parallel output. When CS is low, this serves as the output enable and puts the previous conversion results on the bus. Nap mode enable, active low Product Folder Link(s): ADS7882 www.ti.com 38 37 BUSY ...

  • Page 7

    ... Internal reference output shorted to REFIN pin when internal reference is used. Do not connect to REFIN pin when external reference is used. Always needs to be decoupled with AGND using 0.1- F bypass capacitor. Reference ground. Connect to analog ground plane. No connection Product Folder Link(s): ADS7882 ADS7882 SLAS630 – DECEMBER 2008 16-BIT BUS BYTE = 1 BYTE = 0 Table 3 for layout guidelines. ...

  • Page 8

    ... CS when CONVST is low (see (acq (acq (acq) Product Folder Link(s): ADS7882 Figure 3). Also refer to the section DEVICE Figure 2). A clean Copyright © 2008, Texas Instruments Incorporated www.ti.com ...

  • Page 9

    ... Figure 5 and Figure 6 illustrate the device read operation. The bus D11−4 & D3−0 Figure 5. Read Control via CS and RD Product Folder Link(s): ADS7882 ADS7882 SLAS630 – DECEMBER 2008 Figure 1111 1110 0000 (acq D3−0 Submit Documentation Feedback 4) ...

  • Page 10

    ... Sample Conversion (conv) d11 Data For Conversion N−1 (Data Read without Latency 333 ns for 3 MSPS Operation 0 Product Folder Link(s): ADS7882 www.ti.com (acq) t d10 D3−0 ). Note that care d2 Figure 7 for a 3-MHz operation. w4 Copyright © 2008, Texas Instruments Incorporated ...

  • Page 11

    ... Data For Conversion N−1 (Data Read without Latency 333 ns for 3 MSPS Operation (acq) Product Folder Link(s): ADS7882 ADS7882 SLAS630 – DECEMBER 2008 Figure 9. This provides substantial power Figure as defined in the timing (acq) Figure 10). This is useful when the system Submit Documentation Feedback 9) ...

  • Page 12

    ... Power Down Phase Figure 11. Device Power Down First 4 Invalid Conversions 1111 1110 0000 RESET Phase Figure 12. Device Reset Product Folder Link(s): ADS7882 period after a high-to-low transition Data is not valid for w7 Figure 12). The device is Valid Conversions ...

  • Page 13

    ... V = 2.5 V 11.20 11.18 11.16 11.14 11.12 11.10 308 11.08 29 −40 G001 71.0 70.5 70.0 69.5 69.0 68.5 68 −40 G003 Product Folder Link(s): ADS7882 ADS7882 SLAS630 – DECEMBER 2008 (1) EFFECTIVE NUMBER OF BITS vs FREE-AIR TEMPERATURE f = 100 kHz IN Throughput = 3 MSPS 2.5 V REF − − Free-Air temperature − Figure 14. SIGNAL-TO-NOISE RATIO vs ...

  • Page 14

    ... V V 80.0 − G005 72 T Throughput = 3 MSPS 100 G007 Product Folder Link(s): ADS7882 SPURIOUS-FREE DYNAMIC RANGE vs FREE-AIR TEMPERATURE = 2.5 V REF − − Free-Air temperature − Figure 18. SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY = 25 C ...

  • Page 15

    ... V = 2.5 V REF 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 −40 −20 100 T A G011 Product Folder Link(s): ADS7882 ADS7882 SLAS630 – DECEMBER 2008 vs INPUT FREQUENCY 10 100 − Input Frequency − kHz G010 Figure 22. OFFSET ERROR − Free-Air temperature − C G012 Figure 24. ...

  • Page 16

    ... G013 −1 − −40 G015 Product Folder Link(s): ADS7882 INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE = 2.5 V REF Max Min − − Free-Air temperature − Figure 26. REFERENCE OUTPUT DRIFT vs FREE-AIR TEMPERATURE Throughput = 3 MSPS ...

  • Page 17

    ... 2.5 V REF 0 0 500 1000 1500 2000 Sample Rate − KSPS Figure 29. DIFFERENTIAL NONLINEARITY 1024 2048 Code Figure 30. Product Folder Link(s): ADS7882 ADS7882 SLAS630 – DECEMBER 2008 2500 3000 G017 3072 4096 G018 Submit Documentation Feedback 17 ...

  • Page 18

    ... REFERENCE The ADS7882 has a built-in 2.5-V (nominal value) reference but can operate with an external reference. When an internal reference is used, pin 2 (REFOUT) should be connected to pin 1 (REFIN) with an 0.1- F decoupling capacitor and storage capacitor between pin 2 (REFOUT) and pins 47, 48 (REFM). The internal reference of the converter is buffered ...

  • Page 19

    ... The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, signal frequency, and source impedance. Essentially, the current into the ADS7882 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current (this may not happen when a signal is moving continuously) ...

  • Page 20

    ... Refer to the NAP MODE section in the DESCRIPTION AND TIMING DIAGRAMS section for information. 20 Submit Documentation Feedback Table 2. Conversion Data Read Out DATA READ OUT DB11–DB4 D3–D0, 0000 All zeroes D11–D4 D3–D0 Product Folder Link(s): ADS7882 www.ti.com DB3–DB0 . w7 after the PWD/RST input is d13 Copyright © 2008, Texas Instruments Incorporated ...

  • Page 21

    ... As with the AGND connections, +VA should be connected to a 5-V power supply plane that is separate from the connection for +VBD and digital logic until they are connected at the power entry point onto the PCB. Power to the ADS7882 should be clean and well bypassed. A 0.1- F ceramic bypass capacitor should be placed as close to the device as possible. See Table 3 capacitor is recommended ...

  • Page 22

    ... Analog Input 21 Circuit −IN Figure 34. Using Internal Reference 130 pF 604 604 _ 12 THS4031 100 + 150 AGND AGND THS4031 + 21 W 150 pF Product Folder Link(s): ADS7882 www.ti.com 21 +IN ADS7882 21 −IN +IN ADS7882 –IN Copyright © 2008, Texas Instruments Incorporated ...

  • Page 23

    ... Microcontroller Figure 37. Interfacing With Microcontroller Copyright © 2008, Texas Instruments Incorporated CS GPIO GPIO BYTE CONVST GPIO ADS7882 DB[11:4] P[7: INT BUSY Product Folder Link(s): ADS7882 ADS7882 SLAS630 – DECEMBER 2008 Submit Documentation Feedback 23 ...

  • Page 24

    ... PACKAGING INFORMATION (1) Orderable Device Status ADS7882IPFBR ACTIVE ADS7882IPFBT ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design ...

  • Page 25

    ... TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing ADS7882IPFBR TQFP PFB ADS7882IPFBT TQFP PFB PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 (mm) Diameter Width (mm) W1 (mm) 48 1000 330.0 16.4 9.6 48 250 330.0 16.4 9.6 Pack Materials-Page 1 20-Dec-2008 B0 (mm) ...

  • Page 26

    ... Device Package Type ADS7882IPFBR TQFP ADS7882IPFBT TQFP PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) PFB 48 1000 PFB 48 250 Pack Materials-Page 2 20-Dec-2008 Width (mm) Height (mm) 346.0 346.0 33.0 346.0 346.0 33.0 ...

  • Page 27

    PFB (S-PQFP-G48) 0, 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 1,05 0,95 1,20 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC ...

  • Page 28

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  • Page 29

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...