ADS8519 | |
|---|---|
| Manufacturer Part Number | ADS8519 |
| Description | The ADS8519 is a complete 16-bit sampling analog-to-digital (A/D) converter using state-of-the-art CMOS structures |
| Manufacturer | Texas Instruments |
| ADS8519 datasheets |
|
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Specifications of ADS8519 | |||
|---|---|---|---|
| Resolution(bits) | 16 | Sample Rate (max)(sps) | 250kSPS |
| # Input Channels | 1 | Interface | Serial SPI |
| Dnl(max)(+/-lsb) | 1 | Inl(max)(+/-lsb) | 2 |
| Inl (+/-)(max)(%) | 0.00300 | Snr(db) | 93 |
| Sinad(db) | 92 | Input Range | +8.192V; +/-5V, 10V |
| Power Consumption(typ)(mw) | 100 | Reference Mode | Int , Ext |
| Architecture | SAR | Analog Voltage Av/dd(min)(v) | 4.75 |
| Analog Voltage Av/dd(max)(v) | 5.25 | Digital Supply(min)(v) | 1.65 |
| Digital Supply(max)(v) | 5.25 | Operating Temperature Range(c) | -40 to 85 |
| Pin/package | 28SSOP | Integrated Features | Internal Reference |
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TIMING REQUIREMENTS, T
= –40°C to +85°C
A
t
Pulse duration, convert
w1
t
Delay time, BUSY from R/C low
d1
t
Pulse duration, BUSY low
w2
t
Delay time, BUSY, after end of conversion
d2
t
Delay time, aperture
d3
t
Conversion time
conv
t
Acquisition time
acq
t
+ t
Cycle time
conv
acq
t
Delay time, R/C Low to internal DATACLK output
d4
t
Cycle time, internal DATACLK
c1
t
Delay time, data valid to internal DATACLK high
d5
t
Delay time, data valid after internal DATACLK low
d6
t
Cycle time, external DATACLK
c2
t
Pulse duration, external DATACLK high
w3
t
Pulse duration, external DATACLK low
w4
t
Setup time, R/C rise/fall to external DATACLK high
su1
t
Setup time, R/C transition to CS transition
su2
t
Delay time, SYNC, after external DATACLK high
d7
t
Delay time, data valid from external DATACLK high
d8
t
Delay time, CS rising edge to external DATACLK rising edge
d9
t
Delay time, previous data available after CS, R/C low
d10
t
Setup time, BUSY transition to first external DATACLK
su3
t
Delay time, final external DATACLK to BUSY rising edge
d11
t
Setup time, TAG valid
su4
t
Hold time, TAG valid
h1
CS
R/C
t
su1
External
DATACLK
CS Set Low, Discontinuous Ext DATACLK
CS
t
su2
R/C
Setup Time, R/C to CS
Copyright © 2007–2010, Texas Instruments Incorporated
PARAMETER
TIMING DIAGRAMS
R/C
CS
t
t
su1
External
DATACLK
R/C Set Low, Discontinuous Ext DATACLK
BUSY
t
su2
External
DATACLK
CS Set Low, Discontinuous Ext DATACLK
Figure 1. Critical Timing
Product Folder Link(s):
ADS8519
ADS8519
SLAS462D – JUNE 2007 – REVISED SEPTEMBER 2010
MIN
TYP
MAX
UNIT
40
6
20
2.2
5
5
2.2
1.8
4
270
110
15
35
20
35
35
15
15
15
10
3
35
2
13
10
2
5
1
0
2
t
su1
su1
t
su3
1
2
Submit Documentation Feedback
ns
ns
ms
ns
ns
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
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ms
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7
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