ADS8519 | |
|---|---|
| Manufacturer Part Number | ADS8519 |
| Description | The ADS8519 is a complete 16-bit sampling analog-to-digital (A/D) converter using state-of-the-art CMOS structures |
| Manufacturer | Texas Instruments |
| ADS8519 datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
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Specifications of ADS8519 | |||
|---|---|---|---|
| Resolution(bits) | 16 | Sample Rate (max)(sps) | 250kSPS |
| # Input Channels | 1 | Interface | Serial SPI |
| Dnl(max)(+/-lsb) | 1 | Inl(max)(+/-lsb) | 2 |
| Inl (+/-)(max)(%) | 0.00300 | Snr(db) | 93 |
| Sinad(db) | 92 | Input Range | +8.192V; +/-5V, 10V |
| Power Consumption(typ)(mw) | 100 | Reference Mode | Int , Ext |
| Architecture | SAR | Analog Voltage Av/dd(min)(v) | 4.75 |
| Analog Voltage Av/dd(max)(v) | 5.25 | Digital Supply(min)(v) | 1.65 |
| Digital Supply(max)(v) | 5.25 | Operating Temperature Range(c) | -40 to 85 |
| Pin/package | 28SSOP | Integrated Features | Internal Reference |
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t
w1
R/C
t
t
d1
w2
BUSY
t
t
d3
d11
Error
STATUS
Nth Conversion
Correction
t
conv
External
t
DATACLK
SYNC = 0
DATA
t
su4
TAG
EXT/INT tied high, CS tied low
Figure 4. Read After Conversion (Discontinuous External DATACLK)
t
w1
R/C
t
d1
BUSY
t
d3
STATUS
t
su3
t
w3
t
su1
External
DATACLK
SYNC = 0
t
d8
DATA
EXT/INT tied high, CS and TAG tied low
Figure 5. Read During Conversion (Discontinuous External DATACLK)
Copyright © 2007–2010, Texas Instruments Incorporated
TIMING DIAGRAMS (continued)
t
su1
t
d2
(N+1) th Accquisition
t
su3
t
acq
t
c2
t
w4
w3
0
1
2
3
4
5
10
t
Nth Conversion Data
d8
D15
D14
D13
D12
D11
D10
D05
t
h1
T01
T02
T03
T00
T04
T05
T06
T11
t
+ t
starts READ
w1
su1
t
w2
t
d10
Nth Conversion
t
conv
t
c2
t
w4
1
2
3
4
5
10
0
Nth Conversion Data
D15
D14
D13
D12
D11
D10
D05
Rising DATACLK change DATA, t
TAG is not recommended for this mode. There is not enough
time to do so without violating t
d11
Product Folder Link(s):
ADS8519
ADS8519
SLAS462D – JUNE 2007 – REVISED SEPTEMBER 2010
t
d1
t
d3
t
su1
11
12
13
14
15
16
t
d8
Null
D04
D03
D02
D01
D00
T00
Txx
Null
Tyy
T12
T13
T14
T15
T16
T17
t
d2
Error
Correction
t
d11
11
12
13
14
15
16
t
d8
D04
D03
D02
D01
D00
+ t
Starts READ
w1
su1
.
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