DAC1221

Manufacturer Part NumberDAC1221
ManufacturerTexas Instruments
DAC1221 datasheet
 


Specifications of DAC1221

Resolution(bits)16Dac: Channels1
InterfaceSerial SPIOutput TypeVoltage
Output Range Max.(v Or Ma)2.8Settling Time(µs)2000
Reference: TypeExtPower Consumption(typ)(mw)1.2
Dnl(max)(+/-lsb)1Inl(max)(+/-lsb)2
Pin/package16SSOP/QSOP  
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DIGITAL-TO-ANALOG CONVERTER
FEATURES
16-BIT MONOTONICITY GUARANTEED
OVER –40 C TO +85 C
LOW POWER: 1.2mW
VOLTAGE OUTPUT
SETTLING TIME: 2ms to 0.012%
MAX LINEARITY ERROR: 30ppm
ON-CHIP CALIBRATION
DESCRIPTION
The DAC1221 is a Digital-to-Analog (D/A) converter
offering 16-bit monotonic performance over the speci-
fied temperature range. It utilizes delta-sigma technol-
ogy to achieve inherently linear performance in a
small package at very low power. The output range is
two times the external reference voltage. On-chip
calibration circuitry dramatically reduces offset and
gain errors.
SDIO
SCLK
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1999 Burr-Brown Corporation
SBAS113
®
16-Bit Low Power
APPLICATIONS
PROCESS CONTROL
ATE PIN ELECTRONICS
CLOSED-LOOP SERVO-CONTROL
SMART TRANSMITTERS
PORTABLE INSTRUMENTS
VCO CONTROL
The DAC1221 features a synchronous serial interface.
In single converter applications, the serial interface can
be accomplished with just two wires, allowing low-
cost isolation. For multiple converters, a CS signal
allows for selection of the appropriate D/A converter.
The DAC1221 has been designed for closed-loop
control applications in the industrial process control
market, and high resolution applications in the test and
measurement market. It is also ideal for remote appli-
cations, battery-powered instruments, and isolated sys-
tems. The DAC1221 is available in a SSOP-16 package.
X
X
V
IN
OUT
REF
Clock Generator
Microcontroller
Second-Order
First-Order
Instruction Register
Command Register
Modulator
Capacitor Filter
Data Register
Offset Register
Full-Scale Register
Modulator Control
Serial
Interface
CS
DV
DGND
DD
PDS-1519B
1
DAC1221
C
C
C
C
1
2A
2B
3
Second-Order
Switched
Continuous
V
OUT
Time Post Filter
AV
AGND
DD
Printed in U.S.A. May, 2000
DAC1221
®

DAC1221 Summary of contents

  • Page 1

    ... The DAC1221 has been designed for closed-loop control applications in the industrial process control market, and high resolution applications in the test and measurement market also ideal for remote appli- cations, battery-powered instruments, and isolated sys- tems. The DAC1221 is available in a SSOP-16 package ...

  • Page 2

    ... DC –20log OUT DD GND 0.012% 1Hz to 2kHz 1.125 –0 –0.8mA 1.6mA OL User Programmable Normal Mode Sleep Mode 2 = 6.8nF, unless otherwise noted. 3 DAC1221E TYP MAX UNITS 16 Bits 30 ppm of FSR 190 0.015 % 3 ppm • ...

  • Page 3

    ... NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “DAC1221E/2K5” will get a single 2500-piece Tape and Reel. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’ ...

  • Page 4

    ... SETTLING TIME: 20mV to FS 300 0 –300 –600 –900 –1200 –1500 Time (ms) OUTPUT NOISE VOLTAGE vs FREQUENCY 10000 1000 100 100 1000 Frequency (Hz) ® DAC1221 = 1.25V 2.2nF 150pF and C = 6.8nF. REF 3.0 2.5 2.0 1.5 1.0 0 10000 100000 1500 1200 900 600 300 0 – ...

  • Page 5

    ... Temperature ( C) = 1.25V 2.2nF 150pF and C = 6.8nF. REF – 100 0 5 LINEARITY ERROR vs CODE 0.2 0.4 0.6 0.8 1 16-Bit Input Code Normalized DAC1221 ® ...

  • Page 6

    ... The calibration registers are fully readable and writable. This feature allows for system calibration. The various settings, modes, and registers of the DAC1221 are read or written via a synchronous serial interface. This interface operates as an externally clocked interface. ...

  • Page 7

    ... F REF1004-1.2 FIGURE 2. Recommended External Voltage Reference Circuit for Best Low Noise Operation with the DAC1221. REFERENCE INPUT The reference input voltage of 1.25V can be directly con- nected to V REF The recommended reference circuit for the DAC1221 is shown in Figure 2. DIGITAL OPERATION ...

  • Page 8

    ... For small changes in the data, fast settling is not necessary. When ADPT = 1, the Adaptive Filter is disabled and the DAC1221 will not look at the size of a step to determine the necessity of using fast settling. In either case, fast settling can be defeated if DISF = 1. ...

  • Page 9

    ... MD1 – MD0 (Operating Mode) Bits—The Operating Mode bits control the calibration functions of the DAC1221. The Normal Mode is used to perform conversions. The Self- Calibration Mode is a one-step calibration sequence that calibrates both the offset and full scale. ...

  • Page 10

    ... Due to oscillator settling considerations, commu- nication to and from the DAC1221 should not occur for at least 25ms after power is stable. If this requirement cannot be met or if the circuit has brown- out considerations, the timing diagram of Figure 3 can be used to reset the DAC1221 ...

  • Page 11

    ... The maximum serial clock frequency cannot exceed the DAC1221 X Figures 5 through 9 define the basic digital timing character- istics of the DAC1221. Figure 5 and the associated timing symbols apply to the X and associated timing symbols apply to the serial interface signals (SCLK, SDIO, and CS). The serial interface is discussed in detail in the Serial Interface section ...

  • Page 12

    ... IN SCLK SDIO IN7 SDIO IN7 FIGURE 7. Serial Interface Timing (CS always LOW SCLK SDIO IN7 IN7 SDIO FIGURE 8. Serial Interface Timing (using CS). ® DAC1221 DESCRIPTION Clock Frequency IN X Clock Period IN X Clock High IN X Clock LOW IN SCLK HIGH SCLK LOW ( ...

  • Page 13

    ... SDIO transitions to a read? tri-state condition Yes To Read More flowchart instructions? No End 13 OUT MSB OUT0 SDIO is an output To Write flowchart CS taken HIGH for t periods 15 minimum (or CS tied LOW) HIGH CS state HIGH LOW Yes No Is next instruction a Write? Yes To Write flowchart DAC1221 t 13 ® ...

  • Page 14

    ... However, high frequency noise on DV couple into the analog portion of the DAC1221. This noise can originate from switching power supplies, very fast microprocessors, or digital signal processors. If one supply must be used to power the DAC1221, the AV supply should be used to power DV DD tion can be made via a 10 ...

  • Page 15

    ... PACKAGING INFORMATION (1) Orderable Device Status DAC1221E ACTIVE DAC1221EG4 ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design ...

  • Page 16

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...