DAC128S085

Manufacturer Part NumberDAC128S085
ManufacturerTexas Instruments
DAC128S085 datasheet
 


Specifications of DAC128S085

Resolution(bits)12Dac: Channels8
InterfaceSerial SPIOutput TypeVoltage
Output Range Max.(v Or Ma)5.5Settling Time(µs)8
Reference: TypeExtPower Consumption(typ)(mw)1.95
Dnl(max)(+/-lsb)0.75Inl(max)(+/-lsb)8
Pin/package16SON, 16TSSOP, 16WQFN, 16WSON  
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1.0 Functional Description
1.1 DAC ARCHITECTURE
The DAC128S085 is fabricated on a CMOS process with an
architecture that consists of switches and resistor strings that
are followed by an output buffer. The reference voltages are
externally applied at V
for DAC channels A through D and
REF1
V
for DAC channels E through H.
REF2
For simplicity, a single resistor string is shown in Figure 3.
This string consists of 4096 equal valued resistors with a
switch at each junction of two resistors, plus a switch to
ground. The code loaded into the DAC register determines
which switch is closed, connecting the proper node to the
amplifier. The input coding is straight binary with an ideal out-
put voltage of:
V
= V
x (D / 4096)
OUTA,B,C,D
REF1
V
= V
x (D / 4096)
OUTE,F,G,H
REF2
where D is the decimal equivalent of the binary code that is
loaded into the DAC register. D can take on any value be-
tween 0 and 4095. This configuration guarantees that the
DAC is monotonic.
FIGURE 3. DAC Resistor String
Since all eight DAC channels of the DAC128S085 can be
controlled independently, each channel consists of a DAC
register and a 12-bit DAC. Figure 4 is a simple block diagram
of an individual channel in the DAC128S085. Depending on
the mode of operation, data written into a DAC register causes
the 12-bit DAC output to be updated or an additional com-
mand is required to update the DAC output. Further descrip-
tion of the modes of operation can be found in the Serial
Interface description.
FIGURE 4. Single Channel Block Diagram
1.2 OUTPUT AMPLIFIERS
The output amplifiers are rail-to-rail, providing an output volt-
age range of 0V to V
even rail-to-rail types, exhibit a loss of linearity as the output
approaches the supply rails (0V and V
reason, linearity is specified over less than the full output
range of the DAC. However, if the reference is less than V
there is only a loss in linearity in the lowest codes.
The output amplifiers are capable of driving a load of 2 kΩ in
parallel with 1500 pF to ground or to V
full-scale outputs for given load currents are available in the
Electrical Characteristics Table.
1.3 REFERENCE VOLTAGE
The DAC128S085 uses dual external references, V
V
, that are shared by channels A, B, C, D and channels
REF2
E, F, G, H respectively. The reference pins are not buffered
and have an input impedance of 30 kΩ. It is recommended
that V
and V
REF1
output impedance. The reference voltage range is 0.5V to
V
, providing the widest possible output dynamic range.
A
1.4 SERIAL INTERFACE
The three-wire interface is compatible with SPI, QSPI and
MICROWIRE, as well as most DSPs and operates at clock
rates up to 40 MHz. A valid serial frame contains 16 falling
edges of SCLK. See the Timing Diagram for information on a
write sequence.
A write sequence begins by bringing the SYNC line low. Once
SYNC is low, the data on the D
bit serial input register on the falling edges of SCLK. To avoid
mis-clocking data into the shift register, it is critical that
SYNC not be brought low on a falling edge of SCLK (see
minimum and maximum setup times for SYNC in the Timing
Characteristics and Figure 5). On the 16th falling edge of
SCLK, the last data bit is clocked into the register. The write
sequence is concluded by bringing the SYNC line high. Once
SYNC is high, the programmed function (a change in the DAC
channel address, mode of operation and/or register contents)
is executed. To avoid mis-clocking data into the shift register,
it is critical that SYNC be brought high between the 16th and
17th falling edges of SCLK (see minimum and maximum hold
times for SYNC in the Timing Characteristics and Figure 5).
30016907
FIGURE 5. CS Setup and Hold Times
If SYNC is brought high before the 15th falling edge of SCLK,
the write sequence is aborted and the data that has been
shifted into the input register is discarded. If SYNC is held low
beyond the 17th falling edge of SCLK, the serial data pre-
sented at D
IN
tion on this mode of operation can be found in the Daisy Chain
Section. In either case, SYNC must be brought high for the
minimum specified time before the next write sequence is ini-
tiated with a falling edge of SYNC.
Since the D
30016969
should be idled low between write sequences to minimize
power consumption. On the other hand, SYNC should be
13
when the reference is V
. All amplifiers,
A
A
, in this case). For this
A
. The zero-code and
A
be driven by voltage sources with low
REF2
line is clocked into the 16-
IN
will begin to be output on D
. More informa-
OUT
buffer draws more current when it is high, it
IN
www.national.com
,
A
and
REF1
30016965