DAC128S085

Manufacturer Part NumberDAC128S085
ManufacturerTexas Instruments
DAC128S085 datasheet
 


Specifications of DAC128S085

Resolution(bits)12Dac: Channels8
InterfaceSerial SPIOutput TypeVoltage
Output Range Max.(v Or Ma)5.5Settling Time(µs)8
Reference: TypeExtPower Consumption(typ)(mw)1.95
Dnl(max)(+/-lsb)0.75Inl(max)(+/-lsb)8
Pin/package16SON, 16TSSOP, 16WQFN, 16WSON  
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2.5.3 Programmable Attenuator
Figure 16 shows one of the channels of the DAC128S085
being used as a single-quadrant multiplier. In this configura-
tion, an AC or DC signal can be driven into one of the refer-
ence pins. The SPI interface of the DAC can be used to
digitally attenuate the signal to any level from 0dB (full scale)
to 0V. This is accomplished without adding any noticeable
level of noise to the signal. An amplifier stage is shown in
Figure 16 as a reference for applications where the input sig-
nal requires amplification. Note how the AC signal in this
application is ac-coupled to the amplifier before being ampli-
fied. A separate bias voltage is used to set the common-mode
voltage for the DAC128S085's reference input to V
lowing the largest possible input swing. The multiplying band-
width of V
is 360kHz with a V
REF1,2
CM
peak signal swing of 2V.
FIGURE 16. Programmable Attenuator
2.6 DSP/MICROPROCESSOR INTERFACING
Interfacing the DAC128S085 to microprocessors and DSPs
is quite simple. The following guidelines are offered to hasten
the design process.
2.6.1 ADSP-2101/ADSP2103 Interfacing
Figure 17 shows a serial interface between the DAC128S085
and the ADSP-2101/ADSP2103. The DSP should be set to
operate in the SPORT Transmit Alternate Framing Mode. It is
programmed through the SPORT control register and should
be configured for Internal Clock Operation, Active Low Fram-
ing and 16-bit Word Length. Transmission is started by writing
a word to the Tx register after the SPORT mode has been
enabled.
FIGURE 17. ADSP-2101/2103 Interface
2.6.2 80C51/80L51 Interface
A serial interface between the DAC128S085 and the
80C51/80L51 microcontroller is shown in Figure 18. The
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SYNC signal comes from a bit-programmable pin on the mi-
crocontroller. The example shown here uses port line P3.3.
This line is taken low when data is transmitted to the
DAC128S085. Since the 80C51/80L51 transmits 8-bit bytes,
only eight falling clock edges occur in the transmit cycle. To
load data into the DAC, the P3.3 line must be left low after the
first eight bits are transmitted. A second write cycle is initiated
to transmit the second byte of data, after which port line P3.3
is brought high. The 80C51/80L51 transmit routine must rec-
ognize that the 80C51/80L51 transmits data with the LSB first
while the DAC128S085 requires data with the MSB first.
/ 2, al-
A
of 2.5V and a peak-to-
2.6.3 68HC11 Interface
A serial interface between the DAC128S085 and the 68HC11
microcontroller is shown in Figure 19. The SYNC line of the
DAC128S085 is driven from a port line (PC7 in the figure),
similar to the 80C51/80L51.
The 68HC11 should be configured with its CPOL bit as a zero
and its CPHA bit as a one. This configuration causes data on
the MOSI output to be valid on the falling edge of SCLK. PC7
is taken low to transmit data to the DAC. The 68HC11 trans-
mits data in 8-bit bytes with eight falling clock edges. Data is
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transmitted with the MSB first. PC7 must remain low after the
first eight bits are transferred. A second write cycle is initiated
to transmit the second byte of data to the DAC, after which
PC7 should be raised to end the write sequence.
2.6.4 Microwire Interface
Figure 20 shows an interface between a Microwire compatible
device and the DAC128S085. Data is clocked out on the rising
edges of the SK signal. As a result, the SK of the Microwire
device needs to be inverted before driving the SCLK of the
DAC128S085.
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20
FIGURE 18. 80C51/80L51 Interface
FIGURE 19. 68HC11 Interface
FIGURE 20. Microwire Interface
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