The ISO7220 and ISO7221 are dual-channel digital isolators

ISO7221A

Manufacturer Part NumberISO7221A
DescriptionThe ISO7220 and ISO7221 are dual-channel digital isolators
ManufacturerTexas Instruments
ISO7221A datasheet
 


Specifications of ISO7221A

Number Of Channels2Channel Configuration1/1
Insulation Rating(vrms)2500Supply Voltage(s)(v)3.3, 5
Datarate(mbps)1Input Noise FilterYes
Prop Delay(max)(ns)475Ttl/cmos Input ThresholdTTL
FootprintADuM1201Operating Temperature Range(c)-40 to 125
Pin/package8SOICThermal ShutdownNo
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ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
SLLS755L – JULY 2006 – REVISED JANUARY 2012
IEC PACKAGE CHARACTERISTICS
PARAMETER
L(I01)
Minimum air gap (Clearance)
L(I02)
Minimum external tracking
(Creepage)
CTI
Tracking resistance (Comparative
Tracking Index)
Minimum Internal Gap (Internal
Clearance)
R
Isolation resistance
IO
C
Barrier capacitance Input to output
IO
C
Input capacitance to ground
I
NOTE: Creepage and clearance requirements should be applied according to the specific equipment isolation
standards of an application. Care should be taken to maintain the creepage and clearance distance of a board
design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal according to the measurement techniques
shown in the
Isolation Glossary
board are used to help increase these specifications.
IEC 60664-1 RATINGS TABLE
PARAMETER
Basic isolation group
Installation classification
IEC 60747-5-2 INSULATION CHARACTERISTICS
PARAMETER
V
Maximum working insulation
IORM
voltage
V
Input to output test voltage
PR
V
Transient overvoltage
IOTM
R
Insulation resistance
S
Pollution degree
(1) Climatic Classification 40/125/21
14
DEVICE INFORMATION
TEST CONDITIONS
Shortest terminal-to-terminal distance through air
Shortest terminal-to-terminal distance across the
package surface
DIN IEC 60112 / VDE 0303 Part 1
Distance through the insulation
Input to output, V
= 500 V, all pins on each side of the
IO
barrier tied together creating a two-terminal device,
T
< 100°C
A
Input to output, V
= 500 V, 100°C ≤ T
≤ max
IO
A
V
= 0.4 sin (4E6πt)
I
V
= 0.4 sin (4E6πt)
I
. Techniques such as inserting grooves and/or ribs on a printed circuit
TEST CONDITIONS
Material group
Rated mains voltage ≤150 V
RMS
Rated mains voltage ≤300 V
RMS
Rated mains voltage ≤400 V
RMS
(1)
TEST CONDITIONS
Method b1, V
= V
× 1.875,
PR
IORM
100% Production test with t = 1 s, Partial discharge <5 pC
t = 60 s
V
= 500 V at T
IO
S
www.ti.com
MIN
TYP MAX
UNIT
4.8
mm
SOIC-8
4.3
mm
≥400
0.008
mm
12
>10
11
>10
1
1
SPECIFICATION
II
I-IV
I-III
I-II
SPECIFICATION
UNIT
560
V
1050
4000
9
>10
2
Copyright © 2006–2012, Texas Instruments Incorporated
V
pF
pF
PK