The ISO721, ISO721M, ISO722, and ISO722M are digital isolators with a logic input and output buffer separated by a silicon dioxide (SiO2) insulation barrier

ISO722M

Manufacturer Part NumberISO722M
DescriptionThe ISO721, ISO721M, ISO722, and ISO722M are digital isolators with a logic input and output buffer separated by a silicon dioxide (SiO2) insulation barrier
ManufacturerTexas Instruments
ISO722M datasheet
 


Specifications of ISO722M

Number Of Channels1Channel Configuration1/0
Insulation Rating(vrms)2500Supply Voltage(s)(v)3.3, 5
Datarate(mbps)150Input Noise FilterNone
Prop Delay(max)(ns)16Ttl/cmos Input ThresholdCMOS
FootprintADuM1100Operating Temperature Range(c)-40 to 125
Pin/package8SOICThermal ShutdownNo
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ISO721, ISO721M
ISO722, ISO722M
SLLS629J – JANUARY 2006 – REVISED JULY 2010
ELECTRICAL CHARACTERISTICS: V
over recommended operating conditions (unless otherwise noted)
PARAMETER
Quiescent
I
V
supply current
CC1
CC1
25 Mbps
ISO722/722M
Sleep mode
I
V
supply current
CC2
CC2
Quiescent
25 Mbps
V
High-level output voltage
OH
V
Low-level output voltage
OL
V
Input voltage hysteresis
I(HYS)
I
High-level input current
IH
I
Low-level input current
IL
High-impedance output
I
ISO722, ISO722M
OZ
current
C
Input capacitance to ground
I
CMTI
Common-mode transient immunity
(1) For 5-V operation, V
is specified from 4.5 V to 5.5 V. For 3.3-V operation, V
CC1
SWITCHING CHARACTERISTICS: V
over recommended operating conditions (unless otherwise noted)
PARAMETER
t
Propagation delay, low-to-high-level output
PLH
t
Propagation delay , high-to-low-level output
PHL
t
Pulse skew |t
– t
|
sk(p)
PHL
PLH
t
Propagation delay, low-to-high-level output
PLH
t
Propagation delay, high-to-low-level output
PHL
t
Pulse skew |t
– t
|
sk(p)
PHL
PLH
(1)
t
Part-to-part skew
sk(pp)
t
Output signal rise time
r
t
Output signal fall time
f
Sleep-mode propagation delay,
t
pHZ
high-level-to-high-mpedance output
Sleep-mode propagation delay,
t
pZH
high-impedance-to-high-level output
Sleep-mode propagation delay,
t
pLZ
low-level-to-high-impedance output
Sleep-mode propagation delay,
t
pZL
high-impedance-to-low-level output
t
Failsafe output delay time from input power loss
fs
t
Peak-to-peak eye-pattern jitter
jit(PP)
(1) t
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
sk(PP)
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
6
Submit Documentation Feedback
Product Folder Link(s):
(1)
at 5-V, V
at 3.3-V
OPERATION
CC1
CC2
TEST CONDITIONS
V
= V
or 0 V, no load
I
CC
EN at V
CC
V
= V
or 0 V,
I
CC
No load
EN at 0 V or
ISO721/721M
V
= V
or 0 V, no load
I
CC
I
= –4 mA, See
Figure 1
OH
I
= –20 mA, See
Figure 1
OH
I
= 4 mA, See
Figure 1
OL
I
= 20 mA, See
Figure 1
OL
EN, IN at 2 V
EN, IN at 0.8 V
EN, IN at V
CC
IN at V
, V
= 0.4 sin (4E6pt)
CC
I
V
= V
or 0 V, See
Figure 5
I
CC
is specified from 3 V to 3.6 V.
CC2
at 5-V, V
at 3.3-V OPERATION
CC1
CC2
TEST CONDITIONS
ISO72x
EN at 0 V,
See
Figure 1
ISO72xM
EN at 0 V,
See
Figure 1
See
Figure 2
ISO722
ISO722M
See
Figure 3
See
Figure 4
100-Mbps NRZ data input, See
ISO72x
100-Mbps unrestricted bit run length data
input, See
Figure 6
150-Mbps NRZ data input, See
ISO72xM 150-Mbps unrestricted bit run length data
input, See
Figure 6
Copyright © 2006–2010, Texas Instruments Incorporated
ISO721 ISO721M ISO722 ISO722M
www.ti.com
MIN
TYP
MAX
UNIT
0.5
1
mA
2
4
150
mA
4
6.5
mA
5
7.5
V
– 0.4
3
CC
V
V
– 0.1
3.3
CC
0.2
0.4
V
0
0.1
150
mV
10
mA
–10
mA
1
mA
1
pF
25
40
kV/ms
MIN
TYP
MAX
UNIT
15
19
30
ns
15
19
30
ns
0.5
3
ns
10
12
20
ns
10
12
20
ns
0.5
1
ns
0
5
ns
2
ns
2
ns
7
11
25
ns
4.5
6
8
ms
7
13
25
ns
4.5
6
8
ms
3
ms
Figure 6
2
3
ns
Figure 6
1
2