The TI PCI2040 is a PCI-DSP bridge that provides a glueless connection between the 8-bit host port interface (HPI) port on the TMS320C54X or the 16-bit HPI port on TMS320C6X to the high performance PCI bus

PCI2040

Manufacturer Part NumberPCI2040
DescriptionThe TI PCI2040 is a PCI-DSP bridge that provides a glueless connection between the 8-bit host port interface (HPI) port on the TMS320C54X or the 16-bit HPI port on TMS320C6X to the high performance PCI bus
ManufacturerTexas Instruments
PCI2040 datasheet
 


Specifications of PCI2040

Supply Voltage(s)(v)3.3, 5Operating Temperature Range(c)0 to 70
Pin/package144BGA MICROSTAR, 144LQFP  
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PCI2040 PCI DSP Bridge
Controller
Data Manual
2006
PCIBus Solutions

PCI2040 Summary of contents

  • Page 1

    ... PCI2040 PCI DSP Bridge Controller 2006 Data Manual PCIBus Solutions ...

  • Page 2

    Printed in U.S.A. 09/2006 SCPS048A ...

  • Page 3

    ... PCI2040 PCI-DSP Bridge Controller Data Manual Literature Number: SCPS048A September 2006 Printed on Recycled Paper ...

  • Page 4

    ... TI product or service and is an unfair and deceptive business practice not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: ...

  • Page 5

    ... Accessing Internal PCI2040 Registers 3.3 PCI_LOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Serial ROM Interface 3.5 PCI2040 Host Port Interface 3.5.1 Identifying Implemented Ports and DSP Types 3.5.2 DSP Chip Selects 3.5.3 HPI Register Access Control 3.5.4 Mapping HPI DSP Memory to the Host 3 ...

  • Page 6

    ... Section 4 PCI2040 Programming Model 4.1 PCI Configuration Registers 4.2 Vendor and Device ID Register 4.3 PCI Command Register 4.4 PCI Status Register 4.5 Revision ID 4.6 Class Code 4.7 Cache Line Size Register 4.8 Latency Timer Register 4.9 Header Type Register 4.10 BIST Register 4.11 HPI CSR Memory Base Address Register 4.12 Control Space Base Address Register 4 ...

  • Page 7

    Section 6 DSP HPI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 8

    ... Figure 2−1 PCI2040 Pin Diagram 3−1 PCI2040 System Block Diagram 3−2 PCI2040 Serial ROM Data Format 3−3 PCI2040 Reset Illustration 3−4 General-Purpose Bus Word Write 3−5 General-Purpose Bus Word Read 6−1 C54X Select Input Logic 6−2 Word Write To HPID Without Auto-Increment Enabled 6− ...

  • Page 9

    ... Miscellaneous Terminal Functions 2−6 Host Port Interface Terminal Functions 2−7 Compact PCI Hot Swap Interface 2−8 General-Purpose Bus Interface 3−1 PCI2040 Chip Select Decoding 3−2 HPI Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3 PMC Changes for PCI PM 1.1 Register Model 3−4 General-Purpose Bus Signals 4−1 PCI Configuration Registers 4− ...

  • Page 10

    Table 6−1 C54X HPI Registers Access Control 6−2 C54X HPI Control Register Description 6−3 HCNTL0 and HCNTL1 in C6X 6−4 C6X HPI Control Register viii Title . . . . . . . . . . . . . . ...

  • Page 11

    ... TI JTAG test bus controller (TBC). The PCI2040 universal target-only PCI interface is compatible with 3.3-V or 5-V signaling environments. The PCI2040 interfaces with DSPs via a data bus (HPI port). The PCI2040 also provides a serial ROM interface for preloading several registers including the subsystem ID and subsystem vendor ID. ...

  • Page 12

    1−2 ...

  • Page 13

    ... PCI_AD18 24 PCI_AD17 25 PCI_AD16 PCI_C/BE2 29 PCI_FRAME 30 PCI_IRDY 31 GND 32 PCI_TRDY 33 PCI_DEVSEL 34 PCI_STOP 35 RSVD RSVD 36 Figure 2−1. PCI2040 Pin Diagram HCNTL0/GPA3 108 107 HCNTL1/GPA4 HR/W/GPA5 106 105 HCS3 104 HCS2 103 HCS1 102 HCS0 101 GND 100 HAD15/GPD15 99 HAD14/GPD14 98 HAD13/GPD13 97 HAD12/GPD12 96 HAD11/GPD11 ...

  • Page 14

    Table 2−1 shows the card signal names and their terminal assignments sorted alphanumerically by the associated GGU package terminal number. Table 2−2 shows the card signal names sorted alphabetically by the signal name and its associated terminal numbers. Table 2−1. ...

  • Page 15

    Table 2−2. Card Signal Names Sorted Alphabetically PIN NO. SIGNAL NAME SIGNAL NAME SIGNAL NAME SIGNAL NAME GGU PGE GRST G4 20 HBE0/GPA0 GND E3 10 HBE1/GPA1 GND H2 22 HCNTL0/GPA3 GND K3 31 HCNTL1/GPA4 GND M4 43 HCS0 GND ...

  • Page 16

    The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The terminal numbers are also listed for convenient reference. TERMINAL NO. NAME NAME PGE GGU C9, D13, E3, 10, 22, 31, 43, H2, H12, ...

  • Page 17

    ... Initiator ready PCI_LOCK PCI lock PCI_PAR 39 M3 I/O PCI parity PCI_PERR 37 N1 I/O Parity error PCI_RST PCI reset. Assertion forces PCI2040 non-PME context to a predetermined state. PCI_SERR System error PCI_STOP PCI stop PCI_TRDY Target ready DESCRIPTION DESCRIPTION 2−5 ...

  • Page 18

    ... I/O I/O NAME NAME PGE GGU Global reset. This is a power-on reset to PCI2040 that indicates that a power has been applied to GRST the V CC terminals. GRST resets all register bits in PCI2040. Power management event. This output indicates PCI power management wake-up events to the ...

  • Page 19

    ... Data. A 16-bit parallel, bidirectional, and 3-state data bus used to access registers on external devices controlled by PCI2040. HAD15 is MSB and HAD0 is LSB. Read/Write. The PCI2040 drives this signal host port interface for a write and host port interface for a read. ...

  • Page 20

    ... GP_INT 74 M13 I/O GP interrupt. Interrupt from a device on the GP bus. GP_RD 130 B6 I/O GP read. GP ready. Whenever the device on the GP bus is ready to accept a read or write from PCI2040, GP_RDY GP_RDY 75 L12 I/O is asserted. GP_RDY is deasserted when the device is in recovery from a read or write operation. GP_RST 70 L11 O GP reset ...

  • Page 21

    ... PCI2040 Functional Description This section covers the functional description for PCI2040. The PCI2040 provides a 32-bit PCI host interface and an interface for 8-bit and 16-bit host port interface (HPI) ports for TI’s C54x and C6x families of DSP processors. The following conventions are used in this document: • ...

  • Page 22

    ... The HPI CSR I/O base address register identifies the I/O address of the index port. I/O address index + 1 is the data port. To access a HPI CSR register, software writes the offset of the HPI CSR register into the index port. I/O reads from the data port provide the contents of the indexed register and writes to the data port result in PCI2040 updating the indexed register. ...

  • Page 23

    ... Identifying Implemented Ports and DSP Types The PCI2040 supports up to four DSPs of both the C54x and C6x types. It may be useful for generic software to discover what number and type of DSPs are connected to the PCI2040. This is accomplished by using the HPI DSP implementation register (see Section 5.5) and HPI data width register (see Section 5.6) in the HPI control and status register space ...

  • Page 24

    ... HPI Register Access Control The HCNTL1 and HCNTL0 terminals are driven by the PCI2040 to select the DSP HPI register and access mode on a cycle-by-cycle basis. The PCI2040 determines the type of DSP register access from the PCI address, similarly to the chip select decode as described in Section 3.5.2, DSP Chip Selects. ...

  • Page 25

    ... If auto-increment is selected, then it occurs between the transfer of the first and second bytes. 3.5.6 HPI Interface Specific Notes The PCI2040 supports the HPI features from C54x and C6x interfaces given in Table 3−2. See Section 6, DSP HPI Overview, and the HPI functional specification and timing requirements for more details. C54x ...

  • Page 26

    ... GPIOx is reported through the GPIO input data register (see Section 4.22). When GPIOx is selected as an output, the logical value of the data driven by PCI2040 to the GPIOx terminal is programmed via the GPIO output data register (see Section 4.24). The GPIO input data register, GPIO output data register, and GPIO direction control register are only meaningful for GPIOx if GPIOx is selected as a general-purpose input/output through the GPIO select register (see Section 4 ...

  • Page 27

    ... Interrupts Versus PME When an unmasked interrupt event occurs and PCI2040 is in the D0 power state, PCI2040 asserts INTA to signal the interrupt event. When PCI2040 is in D1, D2, or D3, INTA generation is disabled regardless of the value of bit 31 (masterIntEnable) in the interrupt mask register (see Section 5.2). Whenever an unmasked interrupt event occurs and bit 15 (PME_STS) in the power management control/status register is set (see Section 4 ...

  • Page 28

    ... On a transition to the D0 power state from the D3 power state, PCI2040 asserts an internal signal equivalent to a PCI_RST which does not reset all internal states. There are several register bits that are reset by GRST versus the PCI_RST, and these are referred to as the PME context (or sometimes sticky) bits. The PME context bits for PCI2040 are listed below and Figure 3− ...

  • Page 29

    ... Hot swap terminals: HSENUM, HSSWITCH, and HSLED CPCI hot-swap defines a process for installing and removing PCI boards without adversely affecting a running system. The PCI2040 provides this functionality such that it can be implemented on a board that can be removed and inserted in a hot-swap system. ...

  • Page 30

    ... For the removal event, bit 6 (EXT) is set when the ejector handle is opened (HSSWITCH_STS is 1) and bit 7 (INS This will cause HSENUM to be asserted if bit 1 (EIM and software will halt connection with PCI2040 and light the LED via bit 3 (LOO). The board may then be safely removed. ...

  • Page 31

    ... PCI bus. In this case, the data is BBAAh. The address bus (GPA5−GPA0) is driven with the address the PCI2040 obtained from the PCI bus. For example, if the address on the PCI bus is FF0B0h, then this address would translate bus address of 2Ch. ...

  • Page 32

    ... The transaction completes by deasserting the GP_CS. The PCI2040 starts driving the GP address and data bus with stable values. 1 PCI_CLK GP_RST GP_CS GPD[15:0] GPA[5:0] GP_WR GP_RD GP_RDY Figure 3−5. General-Purpose Bus Word Read 3− ZZZZ BBAA 2C 5 ZZZZ ...

  • Page 33

    ... The bit table also has reserved fields that contain read-only reserved bits. These bits return 0s when read. 4.1 PCI Configuration Registers The PCI2040 is a device that interfaces the PCI bus to the 8-bit or 16-bit HPI port of Texas Instruments C54x or C6x family of DSP processors. The configuration header is compliant with the PCI Local Bus Specification. ...

  • Page 34

    ... MEANING Field may be read by software. Field may be written by software to any value. Set Field may be set by a write of 1. Writes of 0 have no effect. Field may be cleared by a write of one. Writes of 0 have no effect. Field may be autonomously updated by PCI2040 ...

  • Page 35

    ... Since the PCI2040 does not require address stepping, this bit is hardwired to 0. Parity error response enable. This bit controls whether or not the device responds to detected parity 6 PERR_EN RW errors. If this bit is set, then the PCI2040 responds normally to parity errors. If this bit is cleared, then the PCI2040 ignores detected parity errors. 5 VGA_EN R VGA palette snoop ...

  • Page 36

    ... Receive master abort. This bit is set to indicate a transaction has been terminated due to a master abort. 12 TABT_REC R Receive target abort. This bit is set when a transaction is terminated by a target abort. Signaled target abort. This bit is set by the PCI slave unit in the PCI2040 to indicate that it has initiated 11 TABT_SIG RC a target abort. ...

  • Page 37

    ... RW RW Default 0 0 Register: Cache line size Type: Read/Write Offset: 0Ch Default: 00h 4.8 Latency Timer Register The latency timer register returns 0s when read since the PCI2040 is a target-only device. Bit 7 6 Name Type R R Default 0 0 Register: Latency timer Type: Read-only ...

  • Page 38

    ... Header Type Register The header type register returns 00h when read, indicating that the PCI2040 configuration space adheres to the standard PCI header and single function device. Bit 7 6 Name Type R R Default 0 0 Register: Header type Type: Read-only Offset: 0Eh ...

  • Page 39

    ... Memory space indicator. This bit indicates whether the base address maps into the host’s memory or 0 MEM_IND R I/O space. This bit is hardwired the PCI2040 to indicate that this base address is valid only for memory accesses ...

  • Page 40

    ... Control Space Base Address Register The control space base address register allows the host to map the PCI2040’s 32K bytes of control space into host memory. Bit Name Type Default Bit Name Type ...

  • Page 41

    ... GP Bus Base Address Register The GP bus base address register is used by the PCI2040 to communicate with a device on the GP bus. This 32−bit register allows software to assign a memory window for the GP bus anywhere in the 4-Gbyte address space. This window has a 256-byte granularity which means the lower 8 bits of this register default to 0 and are read-only. This register is controlled via bit 5 (GP_EN) in the miscellaneous control register (see Section 4 ...

  • Page 42

    ... Register: Capability pointer Type: Read-only Offset: 34h Default: 50h 4.17 Interrupt Line Register The interrupt line register is written by the host and indicates to which input of the system interrupt controller the PCI2040’s interrupt pin is connected. Bit 7 6 Name Type RW RW Default 1 1 Register: ...

  • Page 43

    ... Interrupt Pin Register The interrupt pin register tells which interrupt the device uses. This register is hardwired to 01h in the PCI2040 to indicate that INTA will be used. Bit 7 6 Name Type R R Default 0 0 Register: Interrupt pin Type: Read-only Offset: 3Dh Default: 01h 4.19 MIN_GNT Register This register specifies the length of the burst period for the device needs in 0.25 µ ...

  • Page 44

    ... GP_RD. Read strobe (RD) for the GP bus. The PCI2040 will set this bit when bit 5 (GP_EN) in the GPIO4 pin. The value of this pin determines the function of GPIO4 Normal GPIO data (default GPWR. Write strobe (WR) for the GP bus. The PCI2040 will set this bit when bit 5 (GP_EN) in the 4 GPIO4Pin RU GPIO3 pin ...

  • Page 45

    GPIO Input Data Register The GPIO input data register reflects the state of the GPIO pins, and defaults to an unknown value. Bit 7 6 Name Type R R Default 0 0 Register: GPIO input data Type: Read-only Offset: ...

  • Page 46

    GPIO Output Data Register The GPIO output data register contains the output data for any selected output pin. Bit 7 6 Name Type R R Default 0 0 Register: GPIO output data Type: Read-only, Read/Write Offset: 47h Default: 00h ...

  • Page 47

    Miscellaneous Control Register The miscellaneous control register controls various miscellaneous functions. Bit Name Type RU RCU R R Default Register: Miscellaneous control Type: Read/Clear/Update/Write Offset: 4Ch Default: 000Fh Table 4−13. Miscellaneous ...

  • Page 48

    ... Diagnostic RETRY_DIS. Delayed transaction disable. When bit 4 is set, delayed transactions are 4 DIAG4 RW disabled. When bit (default), they are enabled. Diagnostic RETRY_EXT. When set, the PCI2040 extends the target latency from PCI clocks and 3 DIAG3 RW is not PCI Local Bus Specification, Revision 2.2 compliant. ...

  • Page 49

    ... Vcc terminals. If auxiliary power is not provided to Vcc terminals for D3 cold wake-up, then this bit should be cleared. This bit is not reset by the assertion of PCI_RST, but is reset by GRST. This field has a value of 4’b1111 indicating that the PCI2040 can signal PME from the D3 hot , D2, 14−11 PME Support R D1 and D0 states ...

  • Page 50

    ... Power Management Control/Status Register The power management control/status register determines and changes the current power state of the PCI2040. The contents of this register are not affected by the internally generated reset caused by the transition from the D3 D0 state. All PCI registers will be reset as a result management registers, and the legacy base address register are not reset ...

  • Page 51

    ... HPI CSR I/O Base Address Register The PCI2040 supports the index/data scheme of accessing the HPI CSR registers. An address written to this register is the address for the index register and the address + 1 is the data address. The base address can be mapped anywhere in 32-bit I/O space on a word boundary except at address 0x0000; hence, bit 0 is read-only, returning 0 when read ...

  • Page 52

    ... EXT RCU (INS Thus, this bit is set when the board implementing the PCI2040 is about to be removed. This bit cannot be set under software control. 5−4 RSVD R Reserved ...

  • Page 53

    ... HPI Control and Status Registers This section covers the PCI2040 HPI control and status register (HPI CSR) space. The PCI2040 allows software to access the HPI configuration through either memory or I/O address space. The memory base address is programmable via the HPI CSR base address register (PCI offset 10h). The I/O base address is programmable via the HPI CSR I/O base address register (PCI offset 58h). Table 5− ...

  • Page 54

    ... The PCI2040 sets this bit if an interrupt has been generated by a device connected to the HPI[2] interface. 2 IntDSP2 RSCU Software can set this bit for diagnostics. The PCI2040 sets this bit if an interrupt has been generated by a device connected to the HPI[1] interface. 1 IntDSP1 RSCU Software can set this bit for diagnostics. ...

  • Page 55

    ... Interrupt Mask Register The interrupt mask register is used to enable the various PCI2040 interrupt sources. Reads from either the set register or the clear register always return interrupt mask. In all cases, except masterIntEnable (bit 31), the enables for each interrupt event align with the event register bits detailed in Table 5−2. ...

  • Page 56

    ... HPI Error Report Register The HPI error report register reflects the state of errors on the HPI interfaces. If any bits in this register are set, then the PCI2040 sets bit 30 (HPIError) in the interrupt event register (see Section 5.1). Software can set the bits in this register for diagnostics. ...

  • Page 57

    HPI DSP Implementation Register The HPI DSP implementation register is used to indicate the presence of implemented DSPs on the HPI interface and is loaded from the serial ROM. Bit Name Type ...

  • Page 58

    5−6 ...

  • Page 59

    DSP HPI Overview This section gives an overview of the DSP host port interface (HPI). Refer to the C54x/C6x data sheets for complete HPI details. 6.1 C54X Host Port Interface The HPI is an 8-bit parallel port used to ...

  • Page 60

    ... The control and status bits are located on the least significant 4 bits. When the host writes to the HPI control register, both bytes must be the same. 6−2 DESCRIPTION 0 PCI2040 read/write to HPI control register. PCI2040 read/write to HPI data register. Address auto-increment is 1 selected. 0 PCI2040 read/write to HPI address register. PCI2040 read/write to HPI data register. Address auto-increment is 1 not selected. ...

  • Page 61

    ... DSP can interrupt the host by writing to bit 3 (HINT) of the HPI control register. By writing the DSP to the HINT bit of the HPI control register, the HPI can assert its HINT pin that is connected to the HINT pin of PCI2040. The host can acknowledge and clear this bit by writing this bit. Writing the HINT bit has no effect. ...

  • Page 62

    ... The HPI ready pin (HRDY) allows insertion of wait states to allow deferred completion of access cycles for hosts that have faster cycle times that the HPI can accept due to C54x operating clock rates. The PCI2040 has four HRDY signals, one for each DSP. The HRDY signal will automatically adjust the host access rate to a faster DSP clock rate or switch the HPI mode (to HOM) for faster access ...

  • Page 63

    ... C5410 latches the data, AAh, on the rising edge of HDS. The HWIL is driven high. 6. During clock 6, the PCI2040 starts driving the second byte or half word onto the HAD bus. Please note that the PCI bus uses little endian notation. For this reason, the PCI2040 transfers the least significant byte first followed by the next least significant byte ...

  • Page 64

    ... HRDY5X0 Figure 6−2. Word Write To HPID Without Auto-Increment Enabled 6.2.7.2 PCI Word Read The second example outlined in Figure 6−3 shows how the PCI2040 translates a word read on the PCI bus with a PCI address of FFEF5800h. The event flow is as follows: 1. The host port is idle. ...

  • Page 65

    ... HAD bus. Also during clock 3 the HDS is asserted. During this time, the C5410 latches the values of HCNTL1, HCNTL0, HWIL, and HR/W. 4. The PCI2040 samples the state of HRDY5X0. If the C5410 indicates it is not ready, then the PCI2040 waits until the C5410 indicates it is ready before it deasserts HDS and HWIL. ...

  • Page 66

    Same as Step 3. 13. Same as Step 4. 14. Same as Step 5 except the data latched is DDh and the HCS1 is deasserted indicating the end of the transaction PCI_CLK HRST1 HCS1 HAD[15:0] HCNTL0 HCNTL1 ...

  • Page 67

    Address/Data Bus The HPI provides 32-bit data to the CPU with a 16-bit wide parallel external interface (C54x has 8-bit wide external interface). All transfers with the host consist of two consecutive half-words. On the HPI data register data ...

  • Page 68

    ... Table 6−3. HCNTL0 and HCNTL1 in C6X DESCRIPTION 0 PCI2040 read/write to HPI control register 1 PCI2040 read/write to HPI address register PCI2040 read/write to HPI data register. Address auto-increment is 0 selected. PCI2040 read/write to HPI data register. Address auto-increment is 1 not selected C6X HPI control ...

  • Page 69

    ... Software Handshaking Using HRDY and FETCH Software handshaking using HRDY and FETCH bits in the HPI control register is a C6x feature not supported in PCI2040 because it will support HRDY pin from DSP to host for insertion of wait states. Table 6−4. C6X HPI Control Register FUNCTION Reserved. Bits 31− ...

  • Page 70

    ... C6X will latch the values of HCNTL1, HCNTL0, HWIL, and HR/W. 4. The PCI2040 will sample the state of HRDY6X0. If the C6X indicates it is not ready, then the PCI2040 will wait until the C6X indicates it is ready before it deasserts HDS and HWIL. ...

  • Page 71

    PCI_CLK HRST0 HCS0 HAD[15:0] HCNTL0 HCNTL1 HWIL HDS HR/W HBE0 HBE1 HRDY6X0 Figure 6−6. Double Word Write To HPID Without Auto-Increment Selected 1 2 PCI_CLK HRST0 HCS0 HAD[15:0] HCNTL0 HCNTL1 HWIL HDS HR/W HBE0 HBE1 HRDY6X0 Figure ...

  • Page 72

    6−14 ...

  • Page 73

    Electrical Characteristics 7.1 Absolute Maximum Ratings Over Operating Temperature Ranges Supply voltage range ...

  • Page 74

    Recommended Operating Conditions (see Note Core voltage V CCP V CCP PCI I/O voltage PCI I/O voltage V CCH V CCH HPI I/O voltage HPI I/O voltage V IH † † High-level input voltage ...

  • Page 75

    Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted) PARAMETER PCI PCI High-level output voltage † High-level output voltage † HPI ‡ Miscellaneous § Miscellaneous § PCI PCI V OL Low-level output voltage HPI ‡ ...

  • Page 76

    7−4 ...

  • Page 77

    ... Mechanical Information The PCI2040 is packaged in either a 144-ball GGU BGA or a 144-pin PGE package. The following shows the mechanical dimensions for the GGU and PGE packages. GGU (S-PBGA-N144) 12,10 SQ 11,90 0,95 0,85 0,55 0,12 0,08 0,45 0,08 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Micro Star BGA configuration Micro Star is a trademark of Texas Instruments Incorporated ...

  • Page 78

    PGE (S-PQFP-G144) 108 109 144 1 17,50 TYP 20,20 19,80 22,20 21,80 1,45 1,35 1,60 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 8−2 PLASTIC ...