Manufacturer Part NumberPCI2250
DescriptionThe Texas Instruments PCI2250 PCI-to-PCI bridge provides a high performance connection path between two peripheral component interconnect (PCI) buses
ManufacturerTexas Instruments
PCI2250 datasheet

Specifications of PCI2250

Intel-compatible Part Number21152abSpeed(mhz)33
Expansion Interface(bits)32Hot-swapFriendly
Supply Voltage(s)(v)3.3, 5Operating Temperature Range(c)0 to 70
Pin/package160QFP, 176LQFP  
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PCI to PCI Bridge
Data Manual
PCIBus Solutions

PCI2250 Summary of contents

  • Page 1

    ... PCI2250 PCI to PCI Bridge 1999 Data Manual PCIBus Solutions ...

  • Page 2

    Printed in U.S.A., 12/99 SCPS051 ...

  • Page 3

    ... PCI2250 PCI-to-PCI Bridge Data Manual Literature Number: SCPS051 December 1999 Printed on Recycled Paper ...

  • Page 4

    ... IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability ...

  • Page 5

    ... Feature/Protocol Descriptions 3.1 Introduction to the PCI2250 3.2 PCI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 6

    Bridge Configuration Header 4.1 Vendor ID Register 4.2 Device ID Register 4.3 Command Register 4.4 Status Register 4.5 Revision ID Register 4.6 Class Code Register 4.7 Cache Line Size Register 4.8 Primary Latency Timer Register 4.9 Header Type Register ...

  • Page 7

    Buffer Control Register 5.12 Port Decode Map Register 5.13 Clock Run Control Register 5.14 Diagnostic Control Register 5.15 Diagnostic Status Register 5.16 Arbiter Request Mask Register 5.17 Arbiter Timeout Status Register 5.18 P_SERR Event Disable Register 5.19 Secondary Clock ...

  • Page 8

    ... Figure 2–1 PCI2250 PGF LQFP Terminal Diagram 2–2 PCI2250 PCM PQFP Terminal Diagram 3–1 System Block Diagram 3–2 PCI AD31–AD0 During Address Phase of a Type 0 Configuration Cycle 3–3 PCI AD31–AD0 During Address Phase of a Type 1 Configuration Cycle 3–4 Bus Hierarchy and Numbering 3– ...

  • Page 9

    List of Tables Table 2–1 PGF LQFP Signal Names Sorted by Terminal Number 2–2 PCM LQFP Signals Sorted by Terminal Number 2–3 Signal Names Sorted Alphabetically to PGF Terminal Number 2–4 Signal Names Sorted Alphabetically to PCM Terminal Number 2–5 ...

  • Page 10

    Power Management Capabilities Register 5–20 Power Management Capabilities Register 5–21 PMCSR Bridge Support Register 5–22 Hot Swap Control Status Register viii . . . . . . . . . . . . . . . . . . ...

  • Page 11

    ... The PCI2250 bridge is compliant with the PCI Local Bus Specification , and can be used to overcome the electrical loading limits of 10 devices per PCI bus and one PCI device per expansion slot by creating hierarchical buses. The PCI2250 provides two-tier internal arbitration for up to four secondary bus masters and may be implemented with an external secondary PCI bus arbiter ...

  • Page 12

    ... PCI Local Bus Specification Revision 2.2 PCI Mobile Design Guide, Revision 1.0 PCI-to-PCI Bridge Architecture Specification Revision 1.1 PCI Power Management Interface Specification Revision 1.1 PICMG Compact-PCI Hot Swap Specification Revision 1.0 1.4 Ordering Information ORDERING NUMBER PCI2250 PCI–PCI Bridge 1–2 NAME VOLTAGE 3.3 V, 5-V tolerant I/Os PACKAGE ...

  • Page 13

    ... CC 33 S_AD27 34 S_AD28 35 S_AD29 36 GND 37 S_AD30 38 S_AD31 39 S_REQ0 40 S_REQ1 S_REQ2 Figure 2–1. PCI2250 PGF LQFP Terminal Diagram 132 MS0 131 NC 130 GND 129 NC 128 P_AD8 127 P_AD9 V 126 CC 125 P_AD10 124 P_AD11 123 P_AD12 122 GND 121 P_AD13 ...

  • Page 14

    ... CC S_AD27 31 32 S_AD28 S_AD29 33 GND 34 S_AD30 35 S_AD31 36 S_REQ0 37 S_REQ1 38 S_REQ2 Figure 2–2. PCI2250 PCM PQFP Terminal Diagram 2–2 MS0 120 GND 119 P_AD8 118 117 P_AD9 V 116 CC P_AD10 115 P_AD11 114 P_AD12 113 GND 112 P_AD13 111 P_AD14 ...

  • Page 15

    Table 2–1. PGF LQFP Signal Names Sorted by Terminal Number TERM. NO. SIGNAL NAME TERM. NO. 1 GND S_PAR S_SERR 49 6 S_PERR 50 7 S_MFUNC 51 8 S_STOP 52 ...

  • Page 16

    Table 2–2. PCM LQFP Signals Sorted by Terminal Number TERM. NO. SIGNAL NAME TERM. NO. 1 GND 41 2 S_PAR 42 3 S_SERR 43 4 S_PERR 44 5 S_MFUNC 45 6 S_STOP 46 7 S_DEVSEL ...

  • Page 17

    Table 2–3. Signal Names Sorted Alphabetically to PGF Terminal Number SIGNAL NAME TERM. NO. SIGNAL NAME GND 1 P_AD1 GND 14 P_AD2 GND 21 P_AD3 GND 29 P_AD4 GND 36 P_AD5 GND 45 P_AD6 GND 56 P_AD7 GND 60 P_AD8 ...

  • Page 18

    Table 2–4. Signal Names Sorted Alphabetically to PCM Terminal Number SIGNAL NAME TERM. NO. SIGNAL NAME GND 1 P_AD13 GND 12 P_AD14 GND 19 P_AD15 GND 27 P_AD16 GND 34 P_AD17 GND 41 P_AD18 GND 50 P_AD19 GND 54 P_AD20 ...

  • Page 19

    TERMINAL I/O PCM PGF NAME NUMBER NUMBER Primary PCI bus clock. P_CLK provides timing for all transactions on the primary PCI bus. All P_CLK primary PCI signals are sampled at rising edge of P_CLK. PCI reset. When ...

  • Page 20

    Table 2–7. Primary PCI Interface Control TERMINAL I/O PCM PGF NAME NUMBER NUMBER P_DEVSEL 100 110 I/O 96 106 I/O P_FRAME 68 74 P_GNT P_IDSEL 83 93 P_IRDY 97 107 I/O P_PAR 106 116 I/O 104 114 I/O P_PERR P_REQ ...

  • Page 21

    ... Each secondary bus device samples all secondary PCI signals at the rising edge of its corresponding S_CLKOUT input. Secondary PCI bus clock input. This input syncronizes the PCI2250 to the secondary bus clocks. Secondary external arbiter enable. When this signal is high, the secondary external arbiter is enabled ...

  • Page 22

    Table 2–9. Secondary PCI Address and Data TERMINAL PCM PGF NAME NUMBER NUMBER S_AD31 S_AD30 33 35 S_AD29 32 34 S_AD28 31 33 S_AD27 29 31 S_AD26 28 30 S_AD25 26 28 S_AD24 24 26 S_AD23 ...

  • Page 23

    Table 2–10. Secondary PCI Interface Control TERMINAL I/O PCM PGF NAME NUMBER NUMBER S_DEVSEL 7 9 I/O S_FRAME 11 13 I/O S_GNT3 47 53 S_GNT2 S_GNT1 44 50 S_GNT0 43 49 S_IRDY 10 12 I/O S_PAR 2 ...

  • Page 24

    TERMINAL PCM PGF NAME NUMBER NUMBER GOZ 63 69 NO/HSLED 62 68 120 132 MS0 MS1/BPCC 159 174 P_MFUNC 102 112 S_MFUNC 5 7 TERMINAL NAME PCM NUMBER 1, 12, 19, 27, 34, 41, 50, 54, 58, 65, 71, 81, ...

  • Page 25

    ... PCI Bus 1 3.1 Introduction to the PCI2250 The PCI2250 is a bridge between two PCI buses and is compliant with both the PCI Local Bus Specification and the PCI-to-PCI Bridge Specification . The bridge supports two 32-bit PCI buses operating at a maximum of 33 MHz. The primary and secondary buses operate independently in either a 3 ...

  • Page 26

    ... The bridge accepts PCI cycles by asserting DEVSEL as a medium-speed device, i.e., DEVSEL is asserted two clock cycles after the address phase. The PCI2250 converts memory write and invalidate commands to memory write commands when forwarding transactions from either the primary or secondary side of the bridge. ...

  • Page 27

    ... When the PCI2250 claims a type 1 configuration cycle that has a bus number equal to its secondary bus number, the PCI2250 converts the type 1 configuration cycle to a type 0 configuration cycle and asserts the proper S_AD line as the IDSEL (see Table 3–2). All other type 1 transactions that access a bus number greater than the bridge secondary bus number but less than or equal to its subordinate bus number are forwarded as type 1 configuration cycles ...

  • Page 28

    ... Secondary Clocks The PCI2250 provides five secondary clock outputs (S_CLKOUT[0:4]). Four are provided for clocking secondary devices. The fifth clock should be routed back into the PCI2250 S_CLK input to ensure all secondary bus devices see the same clock. 3–4 ...

  • Page 29

    ... P_AD31–P_AD0 bus, the C/BE3–C/BE0 bus, and primary parity (P_PAR) by driving them to valid logic levels. If the PCI2250 is parking the primary bus and wants to initiate a transaction on the bus, then it can start the transaction on the next PCI clock by asserting the primary cycle frame (P_FRAME) while P_GNT is still asserted. If P_GNT is deasserted, then the bridge must rearbitrate for the bus to initiate a transaction ...

  • Page 30

    ... SERR. These individual bits enable SERR reporting for both downstream and upstream transactions. By default, the PCI2250 will not signal SERR. If the PCI2250 is configured to signal SERR by setting bit 8 of the command register (offset 04h, see Section 4.3), then the bridge signals SERR if any of the error conditions in the ...

  • Page 31

    ... If bit 4 in the P_SERR event disable register (offset 64h, see Section 5.18 and a posted write transaction results in a master abort, then the PCI2250 signals SERR on the initiating bus. When this occurs, bit 4 of the P_SERR status register (offset 6Ah, see Section 5.20) is set. The status bit is cleared by writing a 1. ...

  • Page 32

    ... PERR or detects PERR. 3.11 Master and Target Abort Handling If the PCI2250 receives a target abort during a write burst, then it signals target abort back on the initiator bus receives a target abort during a read burst, then it provides all of the valid data on the initiator bus and disconnects. ...

  • Page 33

    ... At this point, the delayed transaction is complete. If the second request from the initiator does not match the first request exactly, then the bridge issues another retry to the initiator. When bit 2 of the diagnostic control register (offset 5Ch, see Section 5.14 the PCI2250 is configured for immediate retry mode. In immediate retry mode, the bridge issues a retry immediately, instead of after 16 clocks, on delayed transactions ...

  • Page 34

    ... PCI Clock Run Feature The PCI2250 supports the PCI clock run protocol when in clock run mode, as defined in the PCI Mobile Design Guide . When the system’s central resource signals to the system that it wants to stop the PCI clock (P_CLK) by driving the primary clock run (P_CLKRUN) signal high, the bridge either signals that stop the PCI clock by leaving P_CLKRUN deasserted (high) or signals to the system to keep the clock running by driving P_CLKRUN low ...

  • Page 35

    ... Bridge Configuration Header The PCI2250 bridge is a single-function PCI device. The configuration header is in compliance with the PCI-to-PCI Bridge Architecture Specification . Table 4–1 shows the PCI configuration header, which includes the predefined portion of the bridge’s configuration space. The PCI configuration offset is shown in the right column under the OFFSET heading. Table 4– ...

  • Page 36

    ... Default Register: Vendor ID Type: Read-only Offset: 00h Default: 104Ch 4.2 Device ID Register This 16-bit value is allocated by the vendor and identifies the PCI device. The device ID for the PCI2250 is AC23h. Bit Name Type Default Register: ...

  • Page 37

    Command Register The command register provides control over the bridge interface to the primary PCI bus. VGA palette snooping is enabled through this register, and all other bits adhere to the definitions in the PCI Local Bus Specification . ...

  • Page 38

    ... R hardwired 66-MHz capable. The PCI2250 operates at a maximum P_CLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0. Capabilities list. Bit 4 is read-only and is hardwired to 1, indicating that capabilities additional to standard PCI are 4 R implemented. The linked list of PCI power management capabilities is implemented by this function. ...

  • Page 39

    ... Class Code Register This register categorizes the PCI2250 as a PCI-to-PCI bridge device (0604h) with a 01h or 00h programming interface. Bit 0 is read-only but its value is aliased with bit 0 of the primary decode control register (offset 57h, see Section 5 ...

  • Page 40

    ... Default 0 0 Register: Header type Type: Read-only Offset: 0Eh Default: 01h 4.10 BIST Register The PCI2250 does not support built-in self test (BIST). The BIST register is read-only and returns the value 00h when read. Bit 7 6 Name Type R R Default 0 0 Register: ...

  • Page 41

    Base Address Register 0 The bridge requires no additional resources. Base address register 0 is read-only and returns 0s when read. Bit Name Type Default Bit 15 ...

  • Page 42

    ... The subordinate bus number register indicates the bus number of the highest numbered bus beyond the primary bus existing behind the bridge. The PCI2250 uses this register, in conjunction with the primary bus number and secondary bus number registers, to determine when to forward PCI configuration cycles to the subordinate buses. Configuration cycles directed to a subordinate bus (not the secondary bus) remain type 1 cycles as the cycle crosses the bridge ...

  • Page 43

    I/O Base Register The I/O base register is used in decoding I/O addresses to pass through the bridge. The bridge supports 32-bit I/O addressing; thus, bits 3–0 are read-only and default to 0001b. The upper four bits are writable ...

  • Page 44

    Secondary Status Register The secondary status register is similar in function to the status register (offset 06h, see Section 4.4); however, its bits reflect status conditions of the secondary interface. Bits in this register are cleared by writing a ...

  • Page 45

    Memory Base Register The memory base register defines the base address of a memory-mapped I/O address range used by the bridge to determine when to forward memory transactions from one interface to the other. The upper 12 bits of ...

  • Page 46

    ... Register: Prefetchable base upper 32 bits Type: Read-only Offset: 28h Default: 0000 0000h 4.25 Prefetchable Limit Upper 32 Bits Register The PCI2250 does not support 64-bit addressing; thus the prefetchable limit upper 32-bit register is read-only and returns 0s when read. Bit Name Type ...

  • Page 47

    I/O Base Upper 16 Bits Register The I/O base upper 16 bits register specifies the upper 16 bits corresponding to AD31–AD16 of the 32-bit address that specifies the base of the I/O range to forward from the primary PCI ...

  • Page 48

    ... Expansion ROM Base Address Register The PCI2250 does not implement the expansion ROM remapping feature. The expansion ROM base address register returns all 0s when read. Bit Name Type Default Bit Name Type ...

  • Page 49

    Bridge Control Register The bridge control register provides many of the same controls for the secondary interface that are provided by the command register (offset 04h, see Section 4.3) for the primary interface. Some bits affect the operation of ...

  • Page 50

    Table 4–6. Bridge Control Register (Continued0) BIT TYPE ISA enable. When bit 2 is set, the bridge blocks the forwarding of ISA I/O transactions from the primary to the secondary, addressing the last 768 bytes in each 1K-byte block. This ...

  • Page 51

    ... The TI extension registers are those registers that lie outside the standard PCI-to-PCI bridge device configuration space (i.e., registers 40h–FFh in PCI configuration space in the PCI2250). These registers can be accessed through configuration reads and writes. The TI extension registers add flexibility and performance benefits to the standard PCI-to-PCI bridge ...

  • Page 52

    ... R Reserved. Bits 7–1 return 0s when read. Writing this bit causes the PCI2250 to set bit 6 of the bridge control register (offset 3Eh, see Section 4.32) and then 0 W internally reset the PCI2250. Bit 6 of the bridge control register will not be reset by the internal reset. Bit 0 is self-clearing. ...

  • Page 53

    ... Arbiter Control Register The arbiter control register is used for the bridge’s internal arbiter. The arbitration scheme used is a two-tier rotational arbitration. The PCI2250 bridge is the only secondary bus initiator that defaults to the higher priority arbitration tier. Bit Name ...

  • Page 54

    Extension Window Base 0, 1 Registers The bridge supports two extension windows that define an address range decoded as described in the window enable register and window map register. The extension window base registers define the 32-bit base address ...

  • Page 55

    Extension Window Enable Register The decode of the extension windows is enabled through bits 0 and 1 of this register. See Table 5–4 for a complete description of the register contents. Bit 7 6 Name Type R R Default ...

  • Page 56

    Secondary Decode Control Register The secondary decode control register is used to enable/disable the secondary-bus negative decoding. Only through this register can an extension window be defined for positive decoding or excluded from negative decoding from the secondary bus ...

  • Page 57

    Primary Decode Control Register This register is used to enable and disable the primary bus subtractive decoding and to select the primary bus subtractive decode speed. The bridge defaults to primary bus subtractive decoding enabled (bit 0 is set ...

  • Page 58

    Port Decode Enable Register The port decode enable register is used to select which serial and parallel port addresses are positively decoded from the bridge primary bus to the secondary bus. See Table 5–8 for a complete description of ...

  • Page 59

    ... Upstream MRM/MRL read burst enable. By default, the PCI2250 is set to memory read burst a single cache line. By setting this bit to 1, the PCI2250 will memory read burst multiple cache lines or until the FIFO is full. To utilize this feature, bit 4 of the chip control register (offset 40h, see Section 5.1) must be set to 0. ...

  • Page 60

    Port Decode Map Register The port decode map register is used to select whether the serial- and parallel-port address ranges positively decoded from the primary bridge interface to the secondary interface are included or excluded from the primary interface. ...

  • Page 61

    Clock Run Control Register The clock run control register controls the PCI clock-run mode enable/disable also used to enable the keep-clock-running feature. Bit 0 reflects the status of the secondary clock. There are two clock run modes ...

  • Page 62

    ... Immediate retry mode disabled Bus parking bit. This bit determines where the PCI2250 internal arbiter parks the secondary bus. When this bit is set, the arbiter parks the secondary bus on the bridge. When this bit is cleared, the arbiter parks the bus on the last device mastering ...

  • Page 63

    Diagnostic Status Register The diagnostic status register is used to reflect the bridge diagnostic status. See Table 5–13 for a complete description of the register contents. Bit Name Type Default 0 ...

  • Page 64

    Arbiter Request Mask Register The arbiter request mask register contains the SERR enable on arbiter timeouts and the request mask controls. See Table 5–14 for a complete description of the register contents. Bit 7 6 Name Type R R/W ...

  • Page 65

    Arbiter Timeout Status Register The arbiter timeout status register contains the status of each request (request 5–0) timeout. The timeout status bit for the respective request is set if the device did not assert FRAME after 16 clocks. See ...

  • Page 66

    P_SERR Event Disable Register The P_SERR event disable register is used to enable/disable SERR event on the primary interface. All events are enabled by default. See Table 5–16 for a complete description of the register contents. Bit 7 6 ...

  • Page 67

    Secondary Clock Control Register The secondary clock control register is used to control the secondary clock outputs. See Table 5–17 for a complete description of the register contents. Bit Name Type ...

  • Page 68

    P_SERR Status Register The P_SERR status register indicates what caused a SERR event on the primary interface. See Table 5–18 for a complete description of the register contents. Bit 7 6 Name Type R R/C/U Default 0 0 Register: ...

  • Page 69

    ... R indicates that the PCI2250 cannot assert PME signal from that power state. For the PCI2250, these five bits return 00000b when read, indicating that PME is not supported. D2 support. This bit returns 1 when MS0 is 0, indicating that the bridge function supports the D2 device power state. This ...

  • Page 70

    ... R data-scale field. These bits return only 0000b, because the data register is not implemented PME enable. This bit returns a 0 when read because the PCI2250 does not support PME signaling. 7–2 R Reserved. Bits 7–2 return 0s when read. Power state. This two-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the two-bit field is given below: 00 – ...

  • Page 71

    PMCSR Bridge Support Register The PMCSR bridge support register is required for all PCI bridges and supports PCI bridge specific functionality. See Table 5–21 for a complete description of the register contents. Bit 7 6 Name Type R R ...

  • Page 72

    ... Default: 06h 5.28 HS Next Item Pointer Register The HS next item pointer register is used to indicate the next item in the linked list of CPCI hot swap capabilities. Since the PCI2250 functions only include two capabilities list item, this register returns 0s when read. Bit 7 6 Name ...

  • Page 73

    ... ENUM extraction status. When set, the ENUM output is driven by the PCI2250. This bit defaults to 0, and is set when the 6 R/C/U ejector handle is opened and bit Thus, this bit is set when the board implementing the PCI2250 is about to be removed. This bit cannot be set under software control. 5–4 R Reserved ...

  • Page 74

    5–24 ...

  • Page 75

    Electrical Characteristics 6.1 Absolute Maximum Ratings Over Operating Temperature Ranges Supply voltage range ...

  • Page 76

    Recommended Operating Conditions (see Note Supply voltage (core) PV CCP PV PCI primary bus I/O clamping rail voltage PCI primary bus I/O clamping rail voltage SV CCP SV PCI secondary bus I/O clamping rail voltage PCI ...

  • Page 77

    Electrical Characteristics Over Recommended Operating Conditions PARAMETER TERMINALS V OH † High-level output voltage † High oltage Low level output voltage Low-level output voltage Input terminals Input terminals I IH ...

  • Page 78

    PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature (see Figure 6–2 and Figure 6– Cycle time, PCLK t wH Pulse duration, PCLK high t wL Pulse duration, PCLK low v/ t ...

  • Page 79

    PCI Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature (see Note 5 and Figure 6–1 and Figure 6–4) PCLK to shared signal valid delay time Propagation delay time Propagation delay time PCLK ...

  • Page 80

    Parameter Measurement Information LOAD CIRCUIT PARAMETERS C LOAD † TIMING I OL PARAMETER (pF) (mA) t PZH PZL t PHZ t dis PLZ † C LOAD includes ...

  • Page 81

    PCI Bus Parameter Measurement Information 0 PCLK RSTIN PCLK 1.5 V PCI Output PCI Input Figure 6–4. Shared-Signals Timing Waveforms Figure 6–2. PCLK Timing Waveform t ...

  • Page 82

    6–8 ...

  • Page 83

    Mechanical Data PGF (S-PQFP-G176) PLASTIC QUAD FLATPACK 132 133 176 1 21,50 SQ 24,20 23,80 26,20 25,80 1,45 1,35 1,60 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. ...

  • Page 84

    PCM (S-PQFP-G***) 144 PINS SHOWN 108 109 144 1 28,20 27,80 31,45 30,95 3,60 3,20 4,10 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-022 D. ...