TPS65070

Manufacturer Part NumberTPS65070
DescriptionThe TPS6507x are single chip Power Management ICs for portable applications consisting of a battery charger with power path management for a single Li-Ion or Li-Polymer cell
ManufacturerTexas Instruments
TPS65070 datasheet
 


Specifications of TPS65070

Vin(min)(v)2.8Vin(max)(v)6.3
Step-down Dc/dc Converter3Ldo2
Processor NameTI-OMAP-L1xx , TI TMS320C6742/6/8Pin/package48VQFN
Vout(min)(v)0.8Vout(max)(v)3.3
Iout(max)(a)0.2Iq(typ)(ma)0.08
Duty Cycle(max)(%)100Shutdown Current(typ)(ua)0.08
Switching Frequency(max)(khz)2250Operating Temperature Range(c)-40 to 85
TopologyMulti-ChannelRegulated Outputs(#)5
Priority(used For Pqs)3  
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Single Chip Power Solution for Battery Powered Systems
Check for Samples: TPS65070, TPS65072, TPS65073, TPS650702, TPS650731,
FEATURES
1
Charger/Power Path Management:
2
– 2A Output Current on the Power Path
– Linear Charger; 1.5A Maximum Charge
Current
– 100mA/500mA/ 800mA/1300mA Current
Limit From USB Input
– Thermal Regulation, Safety Timers
– Temperature Sense Input
3 Step-Down Converters:
– 2.25MHz Fixed Frequency Operation
– Up to 1.5A of Output Current
– Adjustable or Fixed Output Voltage
– V
Range From 2.8V to 6.3V
IN
– Power Save Mode at Light Load Current
– Output Voltage Accuracy in PWM Mode
±1.5%
– Typical 19 μA Quiescent Current per
Converter
– 100% Duty Cycle for Lowest Dropout
LDOs:
– Fixed Output Voltage
– Dynamic Voltage Scaling on LDO2
– 20μA Quiescent Current
– 200mA Maximum Output Current
– V
Range From 1.8V to 6.3V
IN
wLED Boost Converter:
– Internal Dimming Using I2C
– Up to 2 × 10 LEDs
– Up to 25mA per String With Internal Current
Sink
2
I
C Interface
10 Bit A/D Converter
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OMAP, PowerPAD are trademarks of Texas Instruments.
2
UNLESS
OTHERWISE
NOTED
this
document
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS65070, TPS65072, TPS65073, TPS650702
Touch Screen Interface
Undervoltage Lockout and Battery Fault
Comparator
APPLICATIONS
Portable Navigation Systems
PDAs, Pocket PCs
OMAP™ and Low Power DSP Supply
DESCRIPTION
The TPS6507x are single chip Power Management
ICs for portable applications consisting of a battery
charger with power path management for a single
Li-Ion or Li-Polymer cell. The charger can either be
supplied by a USB port on pin USB or by a dc voltage
from a wall adapter connected to pin AC. Three
highly efficient 2.25MHz step-down converters are
targeted at providing the core voltage, memory and
I/O voltage in a processor based system. The
step-down converters enter a low power mode at light
load for maximum efficiency across the widest
possible range of load currents. For low noise
applications the devices can be forced into fixed
frequency PWM using the I
step-down converters allow the use of small inductors
and capacitors to achieve a small solution size. The
TPS6507x also integrate two general purpose LDOs
for an output current of 200mA. These LDOs can be
used to power an SD-card interface and an
always-on rail, but can be used for other purposes as
well. Each LDO operates with an input voltage range
between 1.8V and 6.3V allowing them to be supplied
from one of the step-down converters or directly from
the main battery. An inductive boost converter with
two programmable current sinks power two strings of
white LEDs.
The TPS6507x come in a 48-pin leadless package
(6mm × 6mm QFN) with a 0.4mm pitch.
contains
TPS650731, TPS650732
SLVS950E – JULY 2009 – REVISED FEBRUARY 2012
TPS650732
2
C interface. The
Copyright © 2009–2012, Texas Instruments Incorporated

TPS65070 Summary of contents

  • Page 1

    ... Single Chip Power Solution for Battery Powered Systems Check for Samples: TPS65070, TPS65072, TPS65073, TPS650702, TPS650731, FEATURES 1 • Charger/Power Path Management: 2 – 2A Output Current on the Power Path – Linear Charger; 1.5A Maximum Charge Current – 100mA/500mA/ 800mA/1300mA Current Limit From USB Input – ...

  • Page 2

    ... The RSL package is available in tape and reel. Add R suffix (TPS65070RSLR) to order quantities of 2500 parts per reel. Add T suffix (TPS65070RSLT) to order quantities of 250 parts per reel. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) Voltage range on all pins except the pins listed below with respect to AGND ...

  • Page 3

    ... Output current at L2; except TPS650702 OUTDCDC2 I Output current at L2 for TPS650702 OUTDCDC2 (2) L2 Inductor Output Capacitor at VDCDC2 OUTDCDC2 I Output current at L3;except TPS650702 OUTDCDC3 I Output current at L3 for TPS650702 OUTDCDC3 (2) L3 Inductor Input Capacitor at VINDCDC3 INDCDC3 C Output Capacitor at VDCDC3 OUTDCDC3 (2) L4 Inductor ...

  • Page 4

    ... Voltage at the output of the power manager detected at pin SYS; falling voltage, voltage defined with <UVLO0>, <UVLO1> DEFAULT: 2.8V Rising voltage defined with <UVLO hysteresis>; DEFAULT: 500mV Due to internal delay Increasing junction temperature Decreasing junction temperature TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com = 25°C (unless A MIN TYP MAX UNIT 2 ...

  • Page 5

    ... VINDCDC2 = 6.3 V VINDCDC2 = 2.8 V VINDCDC2 = 3 6 TPS65072/702/73/731/732 2.8 V < V INDCDC2 TPS65070 External resistor divider Internal resistor divider, I selectable (Default setting) TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 MIN TYP MAX UNIT 2.8 6.3 V 600 mA 1200 ...

  • Page 6

    ... TPS65070, TPS65072, TPS65073, TPS650702 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 DCDC2 CONVERTER (continued) PARAMETER Default output voltage for TPS65070, TPS650732, TPS650702 Vout Default output voltage for TPS65072 Default output voltage for TPS65073, TPS650731 DC output voltage accuracy; PFM mode DC output voltage accuracy ...

  • Page 7

    ... ≤ mA, PFM mode OUT Time from active EN to Start switching Time to ramp from OUT rising voltage falling voltage TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 MIN TYP MAX UNIT 1.0 1.2 1.8 3.3 1 ...

  • Page 8

    ... Vin ≥ Vout + 200 0.5 V (min. 2 6.5 V, INLDO1,2 LDO1,2 ILDO1 = 100 mA; ILDO2 = 100 200 < < Time to ramp from OUT TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com MIN TYP MAX UNIT (1) 1.8 6.3 1.0 3.3 0.725 3.3 200 1.2 1 ...

  • Page 9

    ... I = 0.1 mA; optional push pull output OH Reset, PB_OUT, PGood, INT open drain output in high impedance state Input voltage falling Input voltage rising TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 MIN TYP MAX UNIT 2 ...

  • Page 10

    ... AC detected when V(AC)–V(BAT) > VIN(DT) ; USB detected when V(USB)–V(BAT) > VIN(DT) AC not detected when V(AC)–V(BAT) < VIN(NDT) ; USB not detected when V(USB)–V(BAT) < VIN(NDT) Activated based on settings in CHGCONFIG3 Bit 0 and Bit 7 TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com MIN TYP MAX UNIT 0 2.25 ...

  • Page 11

    ... Internal resistor connected from AC to SYS; Specified by design Internal resistor connected from USB to SYS; Specified by design Set with Bits <PowerPath DPPM threshold1>; <PowerPath DPPM threshold0> TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 MIN TYP MAX UNIT 22 ...

  • Page 12

    ... Maximum value for pre-charge safety timer, thermal, DPM or DPPM loops always active 10 k curve 2 NTC 100 k curve 1 NTC Battery charging Battery charging Battery charging Battery charging NTC error Battery charging TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com MIN TYP MAX 2 –1% 4.10 1% –1% 4 ...

  • Page 13

    ... I Clock input for the I2C interface. SDAT 27 I/O Data line for the I2C interface. Analog input1 for A/D converter TPS65070, TPS650702, TPS65073, TPS650731, TPS650732 only: AD_IN1 43 I (TSX1) Input 1 to the x-plate for the touch screen. Copyright © 2009–2012, Texas Instruments Incorporated ...

  • Page 14

    ... Analog input3 for A/D converter TPS65070, TPS650702, TPS65073, TPS650731, TPS650732 only: AD_IN3 45 I (TSY1) Input 1 to the y-plate for the touch screen Analog input4 for A/D converter TPS65070, TPS650702, TPS65073, TPS650731, TPS650732 only: AD_IN4 46 I (TSY2) Input 2 to the y-plate for the touch screen Connect a 10μ ...

  • Page 15

    ... TPS65070, TPS65073, TPS650731, TPS650732:Input for the reset comparator. RESET will be LOW if this THRESHOLD 47 I voltage drops below 1V. TPS650702, TPS65072, : This pin is the actively high enable input for the wLED driver. The wLED converter EN_wLED enabled by the ENABLE ISINK Bit OR enable EN_wLED pin. ...

  • Page 16

    ... DCDC3 STEP-DOWN CONVERTER 600mA / 1500mA LDO1 200mA LDO LDO2 200mA LDO wLED boost I2C controlled up to 25mA per string - delay + PGND(PAD) AGND TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com SYS SYS AVDD6 4 Batt Batt INT_LDO BYPASS ...

  • Page 17

    ... V O Scope plot 3.6V Scope plot 3.6V Scope plot Scope plot 1.2V Scope plot 2 x 6LEDs (VLED=19.2V 6LEDs (VLED=19.2V); I TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 FIGURE = 3.3V 3. 1.8V 3. 1.2V 3. ...

  • Page 18

    ... TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com EFFICIENCY DCDC1 vs LOAD CURRENT/PFM MODE 3.4V 3. PWM Mode 25°C 0.001 0.01 0 Output Current - A O Figure 2. EFFICIENCY DCDC2 vs LOAD CURRENT/PFM MODE 4 ...

  • Page 19

    ... PWM Mode 90 25° 3. 0.0001 TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 EFFICIENCY DCDC2 vs LOAD CURRENT/PFM MODE PWM Mode 25°C 0.001 0.01 0 Output Current - A O Figure 6 ...

  • Page 20

    ... V DCDC2 (Offset: 1.8 V) OUT I DCDC2 Load TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com EFFICIENCY DCDC3 vs LOAD CURRENT/PFM MODE 3V 4.2V 5V 0.001 0.01 0 Output Current - A O Figure 10. LOAD TRANSIENT RESPONSE CONVERTER 2 V DCDC3 = 3 Load mA - 1350 mA - 150 mA Figure 12. Copyright © ...

  • Page 21

    ... TPS65070, TPS65072, TPS65073, TPS650702 V OUT V DCDC1 (Offset OUT V DCDC3 (Offset TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 LINE TRANSIENT RESPONSE CONVERTER 1 DCDC1 (Offset 3.6V, IN Load = 0.6 A Figure 14. ...

  • Page 22

    ... OUTPUT VOLTAGE RIPPLE AND INDUCTOR CURRENT V DCDC2 (Offset: 1.8 V) OUT I DCDC2 L V LDO1 (Offset: 1.8 V) OUT 3.6 V LOAD IN TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com CONVERTER 2 – PFM MODE Load = 15 mA PFM Figure 18. LOAD TRANSIENT RESPONSE LDO1 LDO1 = 3.6 V, bat IN LOAD = 180 mA LDO1 Figure 20 ...

  • Page 23

    ... LEDs 20 mA each 2.8 3 100 TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 K SET vs R ISET 1 10 100 Iset Figure 22. wLED EFFICIENCY vs Vin 100% duty cycle ...

  • Page 24

    ... USB1300 V LOWV I USB BAT - SC t DGL(NO -IN) t DGL(PGOOD ) t BLK(OVP ) Charge control Timer fault CC1 3 CC1 0 RST EN Figure 25. Charger Block Diagram TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com 250 mV V BAT SYS - SC2 t DGL(SC2 ) VSYS ADC2 V ISET V IPRECHG ADC5 VI CHG I PRECHG ...

  • Page 25

    ... During the power down mode the host commands at the control pins are Figure 26. Power Path Functionality is turned on till the voltage on the BAT pin rises above V BAT(SC) TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 and ...

  • Page 26

    ... OUT pin, if any). In this case, the charger (Vset-100mV), a check is performed to see whether the battery RCH is pulled from the battery for a duration t TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com DONE TERM CURRENT = 1 . The battery voltage CHG BAT(REG) ...

  • Page 27

    ... BAT(DET whichever is lesser. Battery detection is not performed. CHG IN-MAX Figure TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 out of the BAT PRECHG , it is possible that a fully charged RCH ...

  • Page 28

    ... Battery Current IC junction temperature, T Figure 28. Thermal Loop in time t during pre-charging LOWV PRECHG in time t in fast charge (measured from beginning of fast TERM MAXCH TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com DONE TERM CURRENT = 1 J Copyright © 2009–2012, Texas Instruments Incorporated ...

  • Page 29

    ... YES Clear safety timer EN_CHG=0 RECHARGE EN_CHG=0 NO RCH_D = 1 YES BAT_SRHT_D = 1 YES EN_ISHRT=1 for Tdet Figure 29. Charger State Machine TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 EN_CHG=0 FAULT EN_CHG=0 FAULT Submit Documentation Feedback 29 ...

  • Page 30

    ... Submit Documentation Feedback Product Folder Link(s): Table Table 1. Default Voltages DCDC2 DEFDCDC2=HIGH 1.8 V 3.3 V 1.8 V 3.3 V 1.8 V 2.5 V 1.2 V 1.8 V 1.2 V 1.8 V 1.8 V 3.3 V TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com 1. DCDC3 DEFDCDC3=LOW DEFDCDC3=HIGH 1.0 V 1.2 V 1.8 V 3.3 V 1.2 V 1.4 V 1.2 V 1.35 V 1.2 V 1.35 V 1.2 V 1.35 V Copyright © 2009–2012, Texas Instruments Incorporated ...

  • Page 31

    ... Product Folder Link(s): TPS65070, TPS65072, TPS65073, TPS650702 +1%, the device starts a PFM pulse. For this the High Side OUTnominal Figure 30. Power Save Mode TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 Submit Documentation Feedback 31 ...

  • Page 32

    ... This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. 32 Submit Documentation Feedback Product Folder Link(s): TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com Copyright © 2009–2012, Texas Instruments Incorporated ...

  • Page 33

    ... Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Link(s): TPS65070, TPS65072, TPS65073, TPS650702 + R ) max Start RAMP Figure 31. Soft Start TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 (3) has expired. Start Figure 31. Submit Documentation Feedback (3) 33 ...

  • Page 34

    ... LDO1 and LDO2 will start up automatically as defined in register LDO_CTRL1. See details about the sequencing options in the register description for CON_CTRL1 and LDO_CTRL1. RESET (TPS65070, , TPS650702TPS65073, TPS650731, TPS650732 only) The TPS6507x contain circuitry that can generate a reset pulse for a processor with a certain delay time. The input voltage at a comparator is sensed at an input called THRESHOLD ...

  • Page 35

    ... SYS = ON POWER_ON=0 POWER POWER POWER_ON=1 ON_1 ON_2 SYS = ON SYS = ON Figure 33. State Machine TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 DCDC converters power down LDOs power down depending on sequencing option Submit Documentation Feedback 35 ...

  • Page 36

    ... LED current need to be changed to a lower value as defined with Iset2. In order to do this without any 36 Submit Documentation Feedback Product Folder Link(s): 33. , exceeds typically 150°C for the DCDC converters or LDOs, the device J TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com Copyright © 2009–2012, Texas Instruments Incorporated ...

  • Page 37

    ... ADC and touch screen are not used. Touch Screen Interface (only for TPS65070, TPS650702, TPS65073, TPS650731, TPS650732) The touch screen itself consists of two parallel plates, called the X and Y plates, separated by short distance; ...

  • Page 38

    ... pos pos R // × Y × (1 – pos pos TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com Table 2. The touch screen MODE MEASUREMENT X-Position Voltage TSY1 Y-Position Voltage TSX1 Pressure Current TSX1 and TSX2 Plate X Current TSX1 Reading on ADC_IN14 ...

  • Page 39

    ... Figure 35. Two Position Measurement TSX1 I L /150 TGATE R C TSREF R X2 TSX2 PRESSURE MEASUREMET Figure 36. Pressure Measurement TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 TSY1 PMOS TSREF NMOS ...

  • Page 40

    ... TGATE TRESHOLD DETECTOR TGATE TSX2 STANDBY MODE Figure 38. Touch Screen Standby Mode 2 C specifications, allowing transfers TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com TSY1 I L PMOS I L/150 R Y1 TGATE TSREF TO ADC TGATE NMOS ...

  • Page 41

    ... Register Address Figure 41. Serial I/f WRITE to TPS6507x ... ... .. .. R7 R0 ACK Register Slave Address Address Repeated Start TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 P STOP Condition ... ... ACK 0 0 Data Stop ... .. R/W ACK D7 ...

  • Page 42

    ... R7 R0 ACK A6 0 Stop Start Register Slave Address Address (HIGH) t su(STA) t h(DATA) t su(DATA) STA Figure 44. Serial I/f Timing Diagram TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com ... .. A0 R/W ACK D7 D0 ACK 1 0 Slave Master Drives Drives the Data ACK and Stop ...

  • Page 43

    ... Voltage UVLO UVLO removed UVLO AC OR UVLO R/W R/W R/W TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 input USB input USB input current LSB current MSB current LSB ...

  • Page 44

    ... MASK TSC INT PB_IN Cleared when Cleared when Cleared when Cleared when read UVLO UVLO R TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com USB or AC USB or AC PB_IN input voltage input voltage INT applied removed ...

  • Page 45

    ... TPS65070, TPS65072, TPS65073, TPS650702 DPPM Thermal Term active Suspend Current UVLO UVLO UVLO TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 Chg Prechg BatTemp Timeout Timeout error UVLO UVLO UVLO ...

  • Page 46

    ... Submit Documentation Feedback Product Folder Link(s Safety timer SENSOR Charger enable TYPE UVLO UVLO UVLO R/W R/W R/W TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com Charge Suspend Charger Termination reset Charge enable ON/OFF UVLO UVLO UVLO ...

  • Page 47

    ... TPS65070, TPS65072, TPS65073, TPS650702 Charge Charge voltage voltage voltage selection1 selection0 UVLO UVLO UVLO R/W R/W R/W TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 Submit Documentation Feedback ...

  • Page 48

    ... B5 B4 Power path Termination Precharge DPPM DPPM current time threshold0 factor1 UVLO UVLO UVLO R/W R/W R/W TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com Termination Charger Disable current active Isink at USB factor0 UVLO UVLO UVLO UVLO R/W ...

  • Page 49

    ... TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 INPUT INPUT INPUT SELECT_2 SELECT_1 SELECT_0 UVLO UVLO UVLO R/W R/W R/W INPUT SELECTED Voltage at AD_IN1 Voltage at AD_IN2 ...

  • Page 50

    ... V2 V2 GND GND A/D A/D A/D A/D open open open open AD_BIT5 AD_BIT4 AD_BIT3 TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com TSC_M2 TSC_M1 TSC_M0 UVLO UVLO UVLO R R/W R/W MODE MEASUREMENT X-Position Voltage TSY1 Y-Position Voltage TSX1 Pressure Current TSX1 and ...

  • Page 51

    ... PGOOD PGOOD DELAY 0 VDCDC1 VDCDC2 PGOOD PGOOD VDCDC1 VDCDC2 PGOOD PGOOD VDCDC1 VDCDC2 R/W R/W R TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 AD_BIT9 AD_BIT8 MSB ...

  • Page 52

    ... B5 B4 MASK MASK MASK VDCDC3 and VDCDC1 VDCDC2 LDO1 UVLO UVLO UVLO R R/W R/W TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com MASK MASK MASKLDO1 VDCDC3 LDO2 UVLO UVLO UVLO R/W R/W R/W Copyright © ...

  • Page 53

    ... DCDC_SQ1 DCDC_SQ0 ENABLE 1 See Table 9 See Table DCDC1_E DCDC2_EN DCDC3_EN NZ UVLO UVLO UVLO R/W R/W R/W TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 DCDC2 DCDC3 LDO1 LDO2 ENABLE ENABLE ENABLE ENABLE ...

  • Page 54

    ... EN_DCDC3 PIN 54 Submit Documentation Feedback Product Folder Link(s): EN_DCDC2 PIN disabled disabled enabled CON_CTRL1<2> DCDC3 CONVERTER TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com CON_CTRL1<3> DCDC2 CONVERTER 0 x disabled 1 0 disabled 1 1 enabled disabled disabled enabled Copyright © 2009–2012, Texas Instruments Incorporated ...

  • Page 55

    ... PWR_D DS_RDY MASK_EN_DCDC3 UVLO UVLO UVLO R/W R/W R/W TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 UVLO UVLO1 UVLO0 hysteresis BG_GOOD BG_GOOD BG_GOOD R/W R/W R/W Submit Documentation Feedback ...

  • Page 56

    ... UVLO UVLO UVLO R/W R/W R DCDC1[5] DCDC1[4] DCDC1[ UVLO UVLO UVLO R R/W R/W TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com DCDC3 LDO1 discharge discharge discharge UVLO UVLO UVLO UVLO R/W R/W R DCDC1[2] DCDC1[1] DCDC1[ ...

  • Page 57

    ... B5 B4 DCDC3[5] DCDC3[4] DCDC3[ UVLO UVLO UVLO R R/W R/W R/W TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 DCDC2[2] DCDC2[1] DCDC2[ UVLO UVLO UVLO R/W R/W ...

  • Page 58

    ... TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com ...

  • Page 59

    ... Immediate TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 ...

  • Page 60

    ... DCDC converters have an internal 170us delay as well. 60 Submit Documentation Feedback Product Folder Link(s LDO_SQ0 LDO1[3] Table 9 See Table 9 0 UVLO UVLO R/W R/W R TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com LDO1[2] LDO1[1] LDO1[ ...

  • Page 61

    ... LDO2[5] LDO2[4] LDO2[ UVLO UVLO R/W R/W R/W TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 LDO1 OUTPUT VOLTAGE 1.0 V 1.1 V 1.2 V 1.25 V 1.3 V 1.35 V 1.4 V 1.5 V 1.6 V 1.8 V 2.5 V 2.75 V 2.8 V 3.0 V 3 LDO2[2] ...

  • Page 62

    ... UVLO UVLO R R/W R LED DUTY LED DUTY LED DUTY CYCLE_5 CYCLE_4 CYCLE_3 UVLO UVLO UVLO R/W R/W R/W TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com LED DUTY LED DUTY LED DUTY CYCLE_2 CYCLE_1 CYCLE_0 ...

  • Page 63

    ... APPLICATION INFORMATION Table 4. Tested Inductors RECOMMENDED INDUCTOR VALUE MAXIMUM DC CURRENT 0.6 A 2.2 μH 1.2 A 2.2 μH 1.5 A 2.2 μH 1.5 A 2.2 μH TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 Equation SUPPLIER Coilcraft Coilcraft Coilcraft TDK Submit Documentation Feedback 4. (4) (5) 63 ...

  • Page 64

    ... DCDC3. See table 1 for the default voltages if the pins are pulled to GND or to Vcc. Voltage Change on DCDC2 and DCDC3 The output voltage of DCDC2 and DCDC3 can be changed during operation from e.g. 1.0V to 1.2V (TPS65070) and back by toggling the DEFDCDC2 or DEFDCDC3 pin. The status of the DEFDCDC3 pin is sensed during operation and the voltage is changed as soon as the logic level on this pin changes from low to high or vice versa ...

  • Page 65

    ... NMOS when turned on I AVG Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Link(s): TPS65070, TPS65072, TPS65073, TPS650702 TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 (8) (9) Submit Documentation Feedback ...

  • Page 66

    ... H m Table 6. Tested Inductors INDUCTOR TYPE INDUCTOR VALUE LPS3015 18 μH LPS4018 47 μH 47 μH LPS4018 TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com 140 mV = 117 mA Table 6 with the test conditions as SUPPLIER Coilcraft Coilcraft Coilcraft Copyright © 2009–2012, Texas Instruments Incorporated (10) ...

  • Page 67

    ... V 1210 Table 8. NTCs Supported CURVE / B VALUE RT2 NEEDED FOR Curve 2 / B=3477 Curve 1 / B=3964 TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 Table 7 for reference. CAPACITOR TYPE MANUFACTURER UMK316BJ475KL Taiyo Yuden ...

  • Page 68

    ... Product Folder Link(s): RT1 TS 2.25 V RT2 V (45) HOT + - + V (0) COLD - Figure 45. Linearizing the NTC 46. RT1 RT3 TS 2.25 V RT2 V (45) HOT + - + V (0) COLD - TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com Table 8. NTC NTC Copyright © 2009–2012, Texas Instruments Incorporated (18) ...

  • Page 69

    ... Temperature - (T) VTS ( Temperature - (T) Figure 48. Resulting TS Voltage TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 Figure 48 shows the result Submit Documentation Feedback 69 ...

  • Page 70

    ... DCDC1=VDDS_WKUP_BG, VDDS_MEM, VDDS, VDDS_SRAM (1.8V) DCDC2=VDDCORE (1.2V) DCDC3=VDD_MPU_IVA (1.2V) LDO1=VDDS_DPLL_DLL (1.8V) LDO2=VDDA_DAC (1.8V): OFF, enabled by I2C PGOOD delay time (reset delay): 400ms <PGOODMASK>=1Ch: reset based on VDCDC1, VDCDC2, VDCDC3 TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com COMMENT Copyright © 2009–2012, Texas Instruments Incorporated ...

  • Page 71

    ... TPS65070, TPS65072, TPS65073, TPS650702 LDO_SQ[2..0] 001 DCDC1=VDDS1-5 (1.8V) DCDC2=VDDSHV (3.3V) DCDC3=VDD_CORE (1.2V) LDO1=VDDA1P8V (1.8V) LDO2=VDDS_DPLL (1.8V) PGOOD delay time (reset delay): 400ms <PGOODMASK>=1Ch: reset based on VDCDC1, VDCDC2, VDCDC3 TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 COMMENT Submit Documentation Feedback 71 ...

  • Page 72

    ... F m PGND BC847 PowerPad(TM) AGND PB_OUT PGOOD SDAT SCLK INT POWER_ON Reset delay Figure 49. Powering OMAP-L138 TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com OMAP-L138 RTC_CVDD (1.2V) USB0_VDDA33 (3.3 V) USB1_VDDA33 (3.3 V) Sense DVDD3318_A (3.3V or 1.8 V) DVDD3318_B (3.3V or 1.8 V) DVDD3318_C (3.3V or 1.8 V) CVDD (1.2 V) SATA_VDD (1.2 V) PLL0_VDDA (1.2 V) PLL1_VDDA (1.2 V) USBs CVDD (1.2 V) VDDARNWA/1 (1 ...

  • Page 73

    ... Figure 50. Timing for OMAP-L138 TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 50 ms debounce PB_IN = LOW to keep the system alive Submit Documentation Feedback 73 ...

  • Page 74

    ... VIN SYS LDO EN_EXTLDO EN EN_wLED POWER_ON EN_DCDC3 PB_OUT PGOOD SDAT SCLK INT Figure 51. Powering Atlas IV TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com m ALTAS IV VCC_3V3 (VDDIO) VCC_1V8 (VDDIO_MEM) VDD_PDN (1.2 V) VDD_PRE (1.2 V) VDDPLL (1.2 V) VDD_RTCIO GPIO (enable wLED) GPIO (power hold) X_PWR_EN VIO PB_INTERRUPT ...

  • Page 75

    ... Figure 52. Timing for Atlas IV TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 15s 50ms debounce 250 0.5ms Submit Documentation Feedback 75 ...

  • Page 76

    ... See timing diagrams for Sirf Prima SLEEP and DEEP SLEEP in 76 Submit Documentation Feedback Product Folder Link(s): Figure 53 TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com and Figure 54. Copyright © 2009–2012, Texas Instruments Incorporated ...

  • Page 77

    ... DCDC3 and LDO1 are enabled / disabled by EN_DCDC3 to m 170 s 250 s m 170 s m 20ms TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 15s enter / exit SLEEP mode 250 0.5ms Submit Documentation Feedback ...

  • Page 78

    ... DS_RDY=1, start wake-up sequence; otherwise start initial power-up from OFF state set Bits DS_RDY to indicate memory was backed-up set Bits PWR_DS to set Titan 2 to DEEP SLEEP mode 20ms TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com wakeup from DEEP SLEEP 0.95 x Vout,nominal ...

  • Page 79

    ... EN_DCDC2 SYS VDD /RST /MR EN_DCDC3 GND PB_OUT POWER_ON PGOOD SDAT SCLK /INT /Reset TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 OMAP35xx VDDS_MMC1(1.8V / 3.0V) LDO VDDS_WKUP_BG (1.8V) VDDS_MEM; VDDS VDDS_SRAM VDDCORE (1.2V) VDD_MPU_IVA (1.2V) VDDA_DAC (1.8V) VDDS_DPLL_DLL (1.8V) VDDS_DPLL_PER (1.8V) ...

  • Page 80

    ... HIGH any time after POWR_ON=HIGH asserted HIGH by the application processor (OMAP) any time while /PB_IN=LOW to keep the system alive 250 s m 250 s m 250 s m 400ms TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com Copyright © 2009–2012, Texas Instruments Incorporated ...

  • Page 81

    ... EN_DCDC3 PB_OUT POWER_ON PGOOD SDAT SCLK /INT AVDD6 BYPASS INT_LDO /Reset Figure 57. TPS650731 for OMAP35xx TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 OMAP35xx VDDS_WKUP_BG (1.8 V) VDDS_MEM; VDDS VDDS_SRAM VDDCORE (1.2 V) VDD_MPU_IVA (1.2 V) VDDA_DAC (1.8 V) VDDDLL VDDS_DPLL_DLL (1.8 V) VDDS_DPLL_PER (1 ...

  • Page 82

    ... HIGH by the application processor any time while /PB_IN=LOW to keep the system alive m 250 s m 250 s m 170 enabled by OMAP35xx by I2C command 400ms TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com Copyright © 2009–2012, Texas Instruments Incorporated ...

  • Page 83

    ... EN_DCDC3 PB_OUT POWER_ON PGOOD SDAT SCLK /INT AVDD6 BYPASS SYS INT_LDO SYS /Reset TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 TPS650731, TPS650732 SLVS950E – JULY 2009 – REVISED FEBRUARY 2012 AM3505 VDDS1-5 (1.8V) VDDSHV (3.3V) VDD_CORE (1.2V) VDDS_DPLL (1.8V) VDDA1P8V(1.8V) GPIO (/disable power) SYS.nRESPWRON SDAT SCLK ...

  • Page 84

    ... HIGH any time after POWR_ON=HIGH asserted HIGH by the application processor any time while /PB_IN=LOW to keep the 250us 250us 170us 400ms TPS65070 TPS65072 TPS65073 TPS650702 TPS650731 TPS650732 www.ti.com 50ms debounce system alive Copyright © 2009–2012, Texas Instruments Incorporated ...

  • Page 85

    ... LDO1 is defined by the settings in Register DEFLDO1" to "The output voltage for LDO1 is defined by the settings in Register LDO_CTRL1" ...................................................................................................................................... Changes from Revision D (September 2011) to Revision E • Added TPS650702 device specs throughout data sheet. .................................................................................................... Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Link(s): TPS65070, TPS65072, TPS65073, TPS650702 REVISION HISTORY specification ...

  • Page 86

    ... PACKAGING INFORMATION Orderable Device (1) Package Type Package Status TPS65070RSLR ACTIVE VQFN TPS65070RSLT ACTIVE VQFN TPS65072RSLR ACTIVE VQFN TPS65072RSLT ACTIVE VQFN TPS650731RSLR ACTIVE VQFN TPS650731RSLT ACTIVE VQFN TPS650732RSLR ACTIVE VQFN TPS650732RSLT ACTIVE VQFN TPS65073RSLR ACTIVE VQFN TPS65073RSLT ACTIVE VQFN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs ...

  • Page 87

    Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants ( not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak ...

  • Page 88

    ... TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing TPS65070RSLR VQFN RSL TPS65070RSLT VQFN RSL TPS65072RSLR VQFN RSL TPS65072RSLT VQFN RSL TPS650731RSLT VQFN RSL TPS650732RSLR VQFN RSL TPS650732RSLT VQFN RSL TPS65073RSLR VQFN RSL TPS65073RSLT VQFN ...

  • Page 89

    ... Device Package Type TPS65070RSLR VQFN TPS65070RSLT VQFN TPS65072RSLR VQFN TPS65072RSLT VQFN TPS650731RSLT VQFN TPS650732RSLR VQFN TPS650732RSLT VQFN TPS65073RSLR VQFN TPS65073RSLT VQFN PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) RSL 48 2500 RSL 48 250 RSL 48 2500 ...

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    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...