The UCC28019 8-pin active Power Factor Correction (PFC) controller uses the boost topology operating in Continuous Conduction Mode (CCM)

UCC28019

Manufacturer Part NumberUCC28019
DescriptionThe UCC28019 8-pin active Power Factor Correction (PFC) controller uses the boost topology operating in Continuous Conduction Mode (CCM)
ManufacturerTexas Instruments
UCC28019 datasheet
 


Specifications of UCC28019

Uvlo Thresholds On/off(v)10.5/9.5Operating Supply(max)(v)22
Startup Current(ma)0.1Operating Supply Current(ma)7
Vref(v)5Vref Tol(%)2
Duty Cycle(max)(%)99.3Practical Operating Frequency(max)(mhz)0.65
Pin/package8PDIP, 8SOIC  
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Current Sense Resistor, R
SENSE
The current sense resistor, R
SENSE
V
= 0.66 V. To avoid triggering this threshold during normal operation, taking into account the gain of the
SOC(min)
internal non-linear power limit, resulting in a decreased duty cycle, the resistor is typically sized for an overload
current of 25% more than the peak inductor peak current.
V
SOC(min)
R
£
SENSE
.
I
1 25
L _ PEAK (max)
Since R
sees the average input current, worst-case power dissipation occurs at input low line when input
SENSE
line current is at its maximum. Power dissipated by the sense resistor is:
2
P
( I
) R
=
RSENSE
IN _ RMS (max)
SENSE
Peak Current Limit (PCL) protection turns off the output driver when the voltage across the sense resistor
reaches the PCL threshold, V
. The absolute maximum peak current, I
PCL
V
PCL
I
=
PCL
R
SENSE
Gate Driver
The GATE output is designed with a current-optimized structure to directly drive large values of total MOSFET
gate capacitance at high turn-on and turn-off speeds. An internal clamp limits voltage on the MOSFET gate to
12.5 V. An external gate drive resistor, R
inductances and capacitances of the gate drive circuit thus reducing EMI. The final value of the resistor depends
upon the parasitic elements associated with the layout and other considerations. A 10-kΩ resistor close to the
gate of the MOSFET, between the gate and ground, discharges stray gate capacitance and protects against
inadvertent dv/dt-triggered turn-on.
UVLO
From
Fault
PWM
OLP
Logic
Latch
IBOP
PCL
S
Q
OVP
Clock
R
Q
Copyright © 2007, Texas Instruments Incorporated
, is sized using the minimum threshold value of Soft Over Current (SOC),
, limits the rise time and dampens ringing caused by parasitic
GATE
VCC
Pre-Drive and
Clamp Circuit
Figure 26. Gate Driver
Product Folder Link(s):
UCC28019
UCC28019
SLUS755B – APRIL 2007 – REVISED DECEMBER 2007
, is given as:
PCL
Rectified
L
V
AC
D
BST
VCC
BST
Q
BST
GATE
R
GATE
10k
GND
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OUT
C
OUT
19