The TPS731xx family of low-dropout (LDO) linear voltage regulators uses a new topology: an NMOS pass element in a voltage-follower configuration

 

TPS73101

Manufacturer Part NumberTPS73101
DescriptionThe TPS731xx family of low-dropout (LDO) linear voltage regulators uses a new topology: an NMOS pass element in a voltage-follower configuration
ManufacturerTexas Instruments
TPS73101 datasheets

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Specifications of TPS73101

Iout(max)(a)0.1Vdo(typ)(mv)30
Iq(typ)(ma)0.4Vin(min)(v)1.7
Vin(max)(v)5.5Vout Adj(min)(v)1.2
Vout Adj(max)(v)5.5Accuracy(%)1
Output Capacitor TypeCapacitor FreeVout(min)(v)1.2
Vout(max)(v)5.5Pin/package5SOT-23
Regulated Outputs(#)1  
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TPS731xx
SBVS034M – SEPTEMBER 2003 – REVISED AUGUST 2009
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PRODUCT
TPS731xx yy yz
(1) For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet
or see the TI website at www.ti.com.
(2) Most output voltages of 1.25V and 1.3V to 5.0V in 100mV increments are available through the use of innovative factory EEPROM
programming. Minimum order quantities apply; contact factory for details and availability.
(3) For fixed 1.20V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted
PARAMETER
V
range
IN
V
range
EN
V
range
OUT
V
, V
range
NR
FB
Peak output current
Output short-circuit duration
Continuous total power dissipation
Junction temperature range, T
J
Storage temperature range
ESD rating, HBM
ESD rating, CDM
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
POWER DISSIPATION RATINGS
BOARD
PACKAGE
R
ΘJC
(2)
Low-K
DBV
64°C/W
(3)
High-K
DBV
64°C/W
(1) See Power Dissipation in the Applications section for more information related to thermal design.
(2) The JEDEC Low-K (1s) board design used to derive this data was a 3 inch x 3 inch, two-layer board with 2-ounce copper traces on top
of the board.
(3) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on the top and bottom of the board.
2
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..........................................................................................................................................
ORDERING INFORMATION
XX is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable
YYY is package designator.
Z is package quantity.
(1)
(1)
DERATING FACTOR
T
R
ΘJA
ABOVE T
= 25°C
POWER RATING POWER RATING POWER RATING
A
255°C/W
3.9mW/°C
180°C/W
5.6mW/°C
www.ti.com
(1)
(2)
V
OUT
(3)
).
TPS731xx
UNIT
–0.3 to 6.0
–0.3 to 6.0
–0.3 to 5.5
–0.3 to 6.0
Internally limited
Indefinite
See
Dissipation Ratings Table
–55 to +150
–65 to +150
2
500
≤ 25°C
T
= 70°C
T
= 85°C
A
A
A
390mW
215mW
155mW
560mW
310mW
225mW
Copyright © 2003–2009, Texas Instruments Incorporated
V
V
V
V
°C
°C
kV
V