The TMS320DM6441 (also referenced as DM6441) leverages TI's DaVinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices

TMS320DM6441

Manufacturer Part NumberTMS320DM6441
DescriptionThe TMS320DM6441 (also referenced as DM6441) leverages TI's DaVinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices
ManufacturerTexas Instruments
TMS320DM6441 datasheet
 

Specifications of TMS320DM6441

ApplicationsCommunications and Telecom,Consumer Electronics,Video and ImagingOperating SystemsDSP/BIOS,Integrity,Linux,Neutrino,PrOS,Windows Embedded CE
Dsp1 C64xDsp Instruction TypeFixed Point
Dsp Mhz (max.)405,513Dsp Peak Mmacs4104
Arm Cpu1 ARM9Arm Mhz (max.)202,256
Arm Mips(max.)256Video Acceleration1 VICP
Video CapabilityDecode,Encode,Analytics,Image EnhanceTi Video CodecsH.264-BP,JPEG,MPEG2-MP,MPEG4-SP,VC1
Video Resolution/frame RateD1 or LessTi Audio CodecsAAC-HE,AAC-LC,G.711,MP3,WMA
Other Hardware AccelerationH3A,OSD,Previewer,ResizerOn-chip L2 Cache64 KB (DSP)
On-chip L1 Cache112 KB (DSP),32 KB (ARM9)General Purpose MemoryAsync SRAM,GPMC,Memory Stick/Memory Stick PRO,NAND Flash,SmartMedia/xD
Dram1 32-bit SDRAM (DDR2)Usb1
Emac10/100Uart(sci)3
Dac4Pwm(ch)3
I2c1Hpi1
Spi1Dma(ch)Yes
Video Port (configurable)1 Dedicated Input,1 Dedicated OutputIo Supply(v)1.8,3.3
Pin/package361NFBGA  
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1 Digital Media System-on-Chip (DMSoC)
1.1
Features
12
• High-Performance Digital Media SoC
– C64x+™ DSP Clock Rate
405-MHz (Max) at 1.05 V or 513-MHz (Max)
at 1.2 V
– ARM926EJ-S™ Clock Rate
202.5-MHz (Max) at 1.05 V or 256-MHz
(Max) at 1.2 V
– Eight 32-Bit C64x+ Instructions/Cycle
– 4752 C64x+ MIPS
– Fully Software-Compatible With C64x /
ARM9™
• Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+™ DSP Core
– Eight Highly Independent Functional Units
Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
– Load-Store Architecture With Non-Aligned
Support
– 64 32-Bit General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Additional C64x+™ Enhancements
Protected Mode Operation
Exceptions Support for Error Detection
and Program Redirection
Hardware Support for Modulo Loop
Operation
• C64x+ Instruction Set Features
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– Compact 16-Bit Instructions
– Additional Instructions to Support Complex
Multiplies
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010
TMS320DM6441
Digital Media System-on-Chip
Check for Samples:
TMS320DM6441
• C64x+ L1/L2 Memory Architecture
– 32K-Byte L1P Program RAM/Cache (Direct
Mapped)
– 80K-Byte L1D Data RAM/Cache (2-Way
Set-Associative)
– 64K-Byte L2 Unified Mapped RAM/Cache
(Flexible RAM/Cache Allocation)
• ARM926EJ-S Core
– Support for 32-Bit and 16-Bit (Thumb®
Mode) Instruction Sets
– DSP Instruction Extensions and Single Cycle
MAC
– ARM® Jazelle® Technology
– Embedded ICE-RT™ Logic for Real-Time
Debug
• ARM9 Memory Architecture
– 16K-Byte Instruction Cache
– 8K-Byte Data Cache
– 16K-Byte RAM
– 8K-Byte ROM
• Embedded Trace Buffer™ (ETB11™) With 4KB
Memory for ARM9 Debug
• Endianness: Little Endian for ARM and DSP
• Video Imaging Co-Processor (VICP)
• Video Processing Subsystem
– Front End Provides:
CCD and CMOS Imager Interface
BT.601/BT.656 Digital YCbCr 4:2:2
(8-/16-Bit) Interface
Preview Engine for Real-Time Image
Processing
Glueless Interface to Common Video
Decoders
Histogram Module
Auto-Exposure, Auto-White Balance, and
Auto-Focus Module
Resize Engine
– Resize Images From 1/4x to 4x
– Separate Horizontal/Vertical Control
TMS320DM6441
Copyright © 2006–2010, Texas Instruments Incorporated

TMS320DM6441 Summary of contents

  • Page 1

    ... Preview Engine for Real-Time Image Processing • Glueless Interface to Common Video Decoders • Histogram Module • Auto-Exposure, Auto-White Balance, and Auto-Focus Module • Resize Engine – Resize Images From 1/ – Separate Horizontal/Vertical Control TMS320DM6441 Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 2

    ... Cu Metal Process (CMOS) • 3.3-V and 1.8-V I/O, 1.05-V or 1.2-V internal • Applications: – Digital Media – Networked Media Encode/Decode – Video Imaging – Portable Media Players Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com ...

  • Page 3

    ... Description The TMS320DM6441 (also referenced as DM6441) leverages TI’s DaVinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices. The DM6441 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution ...

  • Page 4

    ... DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution. 4 Digital Media System-on-Chip (DMSoC) Section 2.8.3.1, Related Documentation From Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com ...

  • Page 5

    ... Pin Multiplexing 8 KB ROM Peripherals Audio EDMA3 Serial Port Connectivity USB 2.0 VLYNQ PHY Figure 1-1. TMS320DM6441 Functional Block Diagram Copyright © 2006–2010, Texas Instruments Incorporated BT.656, Y/C, Raw (Bayer) Video-Imaging Coprocessor (VICP) Video Processing Subsystem (VPSS) DSP Subsystem Front End t C64x+ DSP CPU ...

  • Page 6

    ... IEEE 1149.1 JTAG 7 Mechanical Packaging and Orderable Information ............ 92 7.1 Thermal Data for ZWT .......... 93 7.2 Packaging Information Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com .............................. ............................................ ..................................... .............................................. ........ ........................................ .......................................... ............ .......................................... ................ ............................................ .................................... ........................................... ...

  • Page 7

    ... NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data manual revision history highlights the technical changes made to the SPRS359D device-specific data manual to make it an SPRS359E revision. Scope: Added information/data on silicon revision 2.3. Applicable updates to the DM644x device family, specifically relating to the TMS320DM6441 device, have been incorporated. SEE Global • ...

  • Page 8

    ... Electrical – Added "For more details on core and I/O activity, as well as information relevant to board power Characteristics Over supply design, see the TMS320DM6441 Power Consumption Summary application report Recommended (literature number SPRAAU3)." Ranges of Supply Voltage and Operating Case Temperature Section 6 ...

  • Page 9

    ... TMS320DM6441 Revision History (continued) SEE Section 6.12 • Added "SDIO is only supported for WLAN operation through TI third parties ..." paragraph MMC/SD/SDIO Section 6.12.1 Table 6-43, MMC/SD/SDIO Register Descriptions: MMC/SD/SDIO • Updated/changed 0x01E1 0064 from "SDIO" to "SDIOCTL (SDIO Control Register)" ...

  • Page 10

    ... Device Overview 2.1 Device Characteristics Table 2-1 provides an overview of the TMS320DM6441 SoC. The table shows significant features of the device, including the capacity of on-chip RAM, peripherals, internal peripheral bus frequency relative to the C64x+ DSP, and the package type with pin count. Table 2-1. Characteristics of the Processor ...

  • Page 11

    ... System module Copyright © 2006–2010, Texas Instruments Incorporated SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 DM6441 DSP 2.47 ns, ARM 4. 1.05 V DSP 1.9 ns, ARM 3 1.2V 1.05 V, 1.2 V 1 (bypass), x15 (1.05 V), x19 (1.2 V) 361-pin BGA (ZWT) 0.09 µ ...

  • Page 12

    ... Invalidate entire TLB, using CP15 register 8 • Invalidate TLB entry, selected by MVA, using CP15 register 8 • Lockdown of TLB entries, using CP15 register 10 12 Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com ...

  • Page 13

    ... Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the config bus and the external memories bus. Copyright © 2006–2010, Texas Instruments Incorporated SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 Device Overview 13 ...

  • Page 14

    ... VICP Registers and Memories The ARM has access to the registers and memories of the video/imaging coprocessor (VICP) subsystem. 14 Device Overview Section 2.5, Memory Map Summary, of this document. The ARM has Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com ...

  • Page 15

    ... Clock PLLs. For more detailed information Section 6.3, Power Supplies. For more detailed 3, Device Configurations, and see the TMS320DM644x DMSoC ARM Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 3.3.3, DSP Boot, for details Section 3.3.2, ARM Boot, for Section 3, Device Configurations, for Section 6 ...

  • Page 16

    ... Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions. 16 Device Overview Section 3, Device Configurations, Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com Section 6, Peripheral ...

  • Page 17

    ... TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732) • TMS320C64x Technical Overview (literature number SPRU395) Copyright © 2006–2010, Texas Instruments Incorporated SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 Device Overview 17 ...

  • Page 18

    ... MSB ST2a 32 LSB ST2b 8 long src even dst odd dst .L2 src2 src1 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com Even Odd register register file A file A (A0, A2, (A1, A3, A4...A30) A5...A31) (D) (D) (A) (B) (C) 2x ...

  • Page 19

    ... L2IBAR L2 invalidate base address register L2IWC L2 invalidate word count register L1PIBAR L1P invalidate base address register L1PIWC L1P invalidate word count register Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 DESCRIPTION Device Overview 19 ...

  • Page 20

    ... Reserved 0x5000 0000 - 0x7FFF FFFF Memory attribute registers for DDR2 0x8000 0000 - 0x8FFF FFFF Reserved 0x9000 0000 - 0xFFFF FFFF Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com DESCRIPTION Table 2-4 depicts the expanded map of Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 21

    ... DDR2 Control Regs Reserved Reserved EMIFA/VLYNQ Shadow EMIFA/VLYNQ Shadow Reserved Reserved DDR2 DDR2 Reserved Reserved Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 EDMA3/ HPI VPSS Reserved ARM RAM0 ARM RAM1 ARM ROM Reserved Reserved DDR2 Control Regs Reserved DDR2 Reserved ...

  • Page 22

    ... Power and Sleep Controller Power and sleep controller Reserved Reserved DDR2 VTP Reg DDR2 VTP reg Reserved ARM interrupt controller Reserved Reserved USB2.0 Regs / RAM ATA/CF SPI GPIO Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com ...

  • Page 23

    ... Memory Stick/Memory Stick PRO Reserved EMIFA Data/Code (CS2) EMIFA data (CS2) EMIFA Data/Code (CS3) EMIFA data (CS3) EMIFA Data/Code (CS4) EMIFA data (CS4) EMIFA Data/Code (CS5) EMIFA data (CS5) Reserved Reserved VLYNQ (Remote) Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 Device Overview 23 ...

  • Page 24

    ... GPIO22 RESET MXV DD18 EM_A[4]/ DV DD18 GPIO27 Figure 2-2. Pin Map [Quadrant A] Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com DDR_CLK0 DDR_A[12] DDR_A[11] V DDR_CKE DDR_BS[1] DDR_A[8] U DDR_BS[0] DDR_BS[2] DDR_A[10] T DDR_WE DDR_CS DDR_VDDDLL R RSV7 ...

  • Page 25

    ... CI0/CCD8 CI1/CCD9 SS DD18 DV V YI4/CCD4 YI5/CCD5 DD18 YI0/CCD0 SS DD18 Figure 2-3. Pin Map [Quadrant B] Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 DDR_D[27] DDR_D[29] RSV4 V DDR_D[24] DDR_D[28] DDR_D[30] U DDR_D[25] DDR_D[26] DDR_D[31] T DDR_D[23 DAC_IOUT_D SSA 1P1V R V ...

  • Page 26

    ... BTSEL1 GPIOV33_1/ PWM2/ COUT0/B3/ GPIO6/B1 TXCLK B2/GPIO47 BTSEL0 Figure 2-4. Pin Map [Quadrant C] Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com USB_ USB_ USB_VBUS V V SSA3P3 DDA3P3 USB_V USB_R1 USB_DM SS1P8 ...

  • Page 27

    ... GPIO32 TDO RTCK DX/ GPIO33 SPI_EN0/ TDI TCK DR/ GPIO37 GPIO34 Figure 2-5. Pin Map [Quadrant D] Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 DDDSP DDDSP DDDSP SS DDDSP ...

  • Page 28

    ... After reset, these are video encoder outputs YOUT[0:4] or RGB666/888 Red and Green data bit outputs G5, G6, G7, R3, and R4. IPD DV DD18 IPD DV DD18 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com DESCRIPTION 3.3, Bootmode, for more details. ARM Boot Mode 0 ARM ROM boot (NAND, SPI) [default] 1 ARM EMIFA boot (NOR) 0 ...

  • Page 29

    ... This pin is multiplexed between the USB clock generator, timer, and GPIO. For the USB clock generator clock output CLK_OUT1. This is configurable for DD18 12 MHz or 24 MHz clock outputs. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 DESCRIPTION should still be connected to the 1.8-V DD should still be connected to ground. should still be connected to the 1.8-V DD ...

  • Page 30

    ... After reset, these are video encoder outputs YOUT[0:4] or RGB666/888 Red and Green data bit outputs G5, G6, G7, R3, and R4. IPD DD18 IPD DD18 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com DESCRIPTION (Section 6.26, IEEE DESCRIPTION Section 3.4.2, Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 31

    ... For EMIFA address bit 17 output EM_A[17]. This pin is multiplexed between EMIFA, GPIO, and VLYNQ. DD18 For EMIFA address bit 16 output EM_A[16]. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 DESCRIPTION Device Overview 31 ...

  • Page 32

    ... When connected to a 16-bit asynchronous memory, this pin is the 2nd bit of the address. For an 8-bit asynchronous memory, this pin is the 3rd bit of the address. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com DESCRIPTION Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 33

    ... These pins are multiplexed between EMIFA (NAND), ATA/CF, and HPI. In all cases they are used bit bi-directional data bus. For EMIFA (NAND), these are EM_D[15:0]. DD18 DD18 DD18 DD18 DD18 DD18 DD18 DD18 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 DESCRIPTION Device Overview 33 ...

  • Page 34

    ... This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA Chip Select 5 output EM_CS5 for use with asynchronous memories (i.e., NOR flash) or DD18 NAND flash. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com DESCRIPTION Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 35

    ... These pins are multiplexed between EMIFA (NAND), ATA/CF, and HPI. In all cases they are used bit bi-directional data bus. For EMIFA (NAND), these are EM_D[15:0]. DD18 DD18 DD18 DD18 DD18 DD18 DD18 DD18 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 DESCRIPTION Device Overview 35 ...

  • Page 36

    ... DQS1: For DDR_D[15:8] DDR2 DQS0: For bottom byte DDR_D[7:0] Bank select outputs (BS[2:0]). Two are required to support 1Gb DDR2 memories. DDR2 DDR2 address bus DDR2 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com DESCRIPTION Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 37

    ... Power (1.8 Volts) for the DDR2 digital locked loop. Impedance control for DDR2 outputs. This must be connected via a 200 Ω resistor ( DDR2 Impedance control for DDR2 outputs. This must be connected via a 200 Ω resistor ( Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 DESCRIPTION Device Overview 37 ...

  • Page 38

    ... This pin is multiplexed between SPI and GPIO. DD18 For SPI data input SPI_DI. This pin is multiplexed between SPI and GPIO. DD18 For SPI it is data output SPI_DO. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com DESCRIPTION DESCRIPTION DESCRIPTION Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 39

    ... This pin is multiplexed between GPIO and Ethernet MAC. DD33 In Ethernet MAC mode management data clock output MDCLK. This pin is multiplexed between GPIO and Ethernet MAC. DD33 In Ethernet MAC mode management data IO MDIO. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 DESCRIPTION Device Overview 39 ...

  • Page 40

    ... This pin is multiplexed between GPIO and Ethernet MAC. DD33 In GPIO mode, this pin is 3.3V GPIO pin GPIOV33_0. (2) Standalone GPIOV18 This pin is standalone and functions as GPIO7. DD18 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com DESCRIPTION DESCRIPTION Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 41

    ... When the USB peripheral is not used, the USB_V DD18 I/O Ground for USB phy. (3) When the USB peripheral is not used, the USB_V Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 DESCRIPTION should be connected to the 1.8-V DD should be connected to ground. SS signal should be connected SSREF signal should be DDA3P3 . SS signal should be connected ...

  • Page 42

    ... DD18 For VLYNQ receive bus bit 1 input VLYNQ_RXD1. This pin is multiplexed between EMIFA, GPIO, and VLYNQ. DD18 For VLYNQ receive bus bit 0 input VLYNQ_RXD0. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com DESCRIPTION signal should still be DDA1P2LDO . SS signal should still be ...

  • Page 43

    ... In 16-bit CCD AFE mode input CCD7. IPD In 16-bit YCbCr mode input Y7. DD18 In 8-bit YCbCr mode time multiplexed between Y7, CB7, and CR7 of the lower 8-bit channel. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 DESCRIPTION Device Overview 43 ...

  • Page 44

    ... In VPFE mode the CCD controller write enable input C_WE. This pin is multiplexed between GPIO, the VPFE, and the VPBE. DD18 In VPFE mode CCDC field identification bidirectional signal C_FIELD. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com DESCRIPTION Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 45

    ... In VPBE mode the LCD output enable LCD_OE. This pin is multiplexed between GPIO and the VPBE. DV DD18 In VPBE mode RGB888 Green data bit 0 output G0. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 DESCRIPTION Device Overview 45 ...

  • Page 46

    ... SS External resistor connection for current bias configuration. This pin must be (3) connected via a 4-kΩ resistor to V DAC_RBIAS signal should be connected to V Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com DESCRIPTION DESCRIPTION signal should be DDA_1P8V signal should be SSA_1P8V signal should be ...

  • Page 47

    ... For UART0 receive data input UART_RXD0. This pin is multiplexed between UART0 and GPIO. . DD18 For UART0 transmit data output UART_TXD0. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 DESCRIPTION Device Overview 47 ...

  • Page 48

    ... For ATA/CF DMA acknowledge output DMACK. IPD This pin is multiplexed between ATA/CF and UART1. For ATA/CF DMA request DMARQ input. DD18 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com DESCRIPTION DESCRIPTION Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 49

    ... This pin is multiplexed between EMIFA, ATA/CF, and GPIO. DD18 For ATA/CF Device address bit 1 output DA1. This pin is multiplexed between EMIFA, ATA/CF, HPI. DD18 For ATA/CF Device address bit 0 output DA0. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 DESCRIPTION Device Overview 49 ...

  • Page 50

    ... Stick PRO. In MMC/SD/SDIO mode, these pins are the nibble-wide bi-directional data bus SD_DATA[3:0]. DD33 In Memory Stick mode, these pins are the nibble-wide bi-directional data bus MS_DATA[3:0]. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com DESCRIPTION Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 51

    ... For EMIFA wait state extension input EM_WAIT. IPU For NAND/SmartMedia/xD ready/busy input (RDY/BSY). DD18 For ATA/CF Ready input IORDY. For HPI ready output HRDY. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 DESCRIPTION Device Overview 51 ...

  • Page 52

    ... For EMIFA (NAND), these are EM_D[15:0]. DD18 For ATA/CF, these are DD[15:0]. In HPI mode, these are HD[15:0] and are multiplexed internally with the HPI address lines. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com DESCRIPTION Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 53

    ... Reserved. (Leave unconnected, do not connect to power or ground) Reserved. (Leave unconnected, do not connect to power or ground) Reserved. (Leave unconnected, do not connect to power or ground) Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 DESCRIPTION DESCRIPTION for normal device operation. SS ...

  • Page 54

    ... Power-Supply Decoupling, of this data manual) 1.8 V I/O supply voltage (see Section 6.3.1.2, Power-Supply Decoupling, of this data manual) 1.8 V DDR2 I/O supply voltage (see Section 6.3.1.2, Power-Supply Decoupling, of this data manual) Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com DESCRIPTION Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 55

    ... SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 OTHER 1. 1.2 V core supply voltage (see Section 6.3.1.2, Power-Supply Decoupling, of this data manual) 1. 1.2 V DSPSS supply voltage (see Section 6.3.1.2, Power-Supply Decoupling, of this data manual) Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 DESCRIPTION Device Overview 55 ...

  • Page 56

    ... G14 J14 ( Input Output High impedance Supply voltage, GND = Ground Analog signal 56 Device Overview Table 2-30. Ground Terminal Functions OTHER GROUND PINS Ground pins Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com DESCRIPTION Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 57

    ... Table 2-30. Ground Terminal Functions (continued) SIGNAL (1) TYPE NAME NO. L14 N14 R14 V GND SS H15 K15 P15 Copyright © 2006–2010, Texas Instruments Incorporated SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 OTHER Ground pins Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 DESCRIPTION Device Overview 57 ...

  • Page 58

    ... Only qualified production devices are to be used. 58 Device Overview http://www.ti.com uniform resource locator (URL). For information Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com ...

  • Page 59

    ... TEMPERATURE RANGE (DEFAULT Blank = PACKAGE TYPE ZWT = 361-pin plastic BGA, with Pb-free soldered balls SILICON REVISION 0 = Initial Silicon A = Silicon 2 Silicon 2.3 ROM SECURITY S = Secure N = Non-secure Figure 2-6. Device Nomenclature Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 (A) Device Overview 59 ...

  • Page 60

    ... TMS320DM644x Digital Media System-on-Chip (DMSoC). The EDMA3 controller’s primary purpose is to service user-programmed data transfers between two memory-mapped slave endpoints on the DMSoC. 60 Device Overview the asynchronous external memory Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com interface (EMIF) in the ...

  • Page 61

    ... EDMA3. This document summarizes the key differences between the EDMA3 and the EDMA2 and provides guidance for migrating from EDMA2 to EDMA3. Copyright © 2006–2010, Texas Instruments Incorporated SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 Device Overview 61 ...

  • Page 62

    ... Implementing DDR2 PCB Layout on the TMS320DM644x DSP. Contains implementation instructions for the DDR2 interface contained on the TMS320DM644x digital signal processor (DSP) device. SPRAAU3 TMS320DM6441 Power Consumption Summary. Discusses the power consumption of the Texas Instruments TMS320DM6441 digital media System-on-Chip (DMSoC). 62 Device Overview Copyright © ...

  • Page 63

    ... VPSS clock control. VDD 3.3V I/O powerdown control. See after Reset, for details. Enables access to the DDR2 VTP register. Reserved Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 DESCRIPTION Section 3.5.4, PINMUX0 Register Description, Section 3.5.5, PINMUX1 Register Description, 3.3.1.2, DSPBOOTADDR Register Section 3.6, Emulation Control, for details. ...

  • Page 64

    ... Figure 3-1. CHP_SHRTSW Register RESERVED Description and described in Table 3-3. By default, these pins are all disabled at reset. Figure 3-2. VDD3P3V_PWDN Register RESERVED Description Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com 1 0 DSPPWRON R/W IOPWDN1 IOPWDN0 R/W-1 R/W-1 Copyright © ...

  • Page 65

    ... SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 and bit field descriptions are shown in Figure 3-3. BOOTCFG Register DSP_BT BTSEL EM_WIDTH R-L R-LL R-L Description (Table 3-9, Table 3-10, and Table 3-11). Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 Table 3-4. The captured bits are DAEAW R-LLLLL Device Configurations 0 65 ...

  • Page 66

    ... K-btyes secondary boot loader through an external host. 0x0000 4000 K-bytes secondary boot loader through UART0. Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com Table 3-5. DSPBOOTADDR is 0 RESERVED R-00 0000 0000 Upper 22 bits of the C64x+ DSP boot address. ...

  • Page 67

    ... HPI loads code into the DM6441 memory map with the entry point set to the memory location specified in the DSPBOOTADDR register. Once the HPI completes loading the code, the ARM should release the DSP from reset. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 Device Configurations 67 ...

  • Page 68

    ... See the GPIO and EMIFA Multiplexing tables details. 3-8, the state of the AEAW[4:0] pins captured at reset configures the show the AEAW[4:0] bit settings and the corresponding multiplexing for (Table 3-9, Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com (Table 3-9, Table 3-10, and Table 3-11) for ...

  • Page 69

    ... GPIO[14] GPIO[14] GPIO[14] GPIO[13] GPIO[13] GPIO[13] GPIO[12] GPIO[12] GPIO[12] GPIO[11] GPIO[11] GPIO[11] GPIO[10] GPIO[10] GPIO[10] Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 00110 00111 EM_BA[1] EM_BA[1] EM_A[0] EM_A[0] EM_A[1] EM_A[1] EM_A[2] EM_A[2] EM_A[3] EM_A[3] EM_A[4] EM_A[4] GPIO[26] EM_A[5] GPIO[25] GPIO[25] ...

  • Page 70

    ... GPIO[13] GPIO[13] GPIO[13] GPIO[12] GPIO[12] GPIO[12] GPIO[11] GPIO[11] GPIO[11] GPIO[10] GPIO[10] GPIO[10] Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com 01110 01111 EM_BA[1] EM_BA[1] EM_A[0] EM_A[0] EM_A[1] EM_A[1] EM_A[2] EM_A[2] EM_A[3] EM_A[3] EM_A[4] ...

  • Page 71

    ... EM_A[17] EM_A[17] EM_A[17] GPIO[13] EM_A[18] EM_A[18] GPIO[12] GPIO[12] EM_A[19] GPIO[11] GPIO[11] GPIO[11] GPIO[10] GPIO[10] GPIO[10] Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 10110 Others EM_BA[1] EM_BA[1] EM_A[0] EM_A[0] EM_A[1] EM_A[1] EM_A[2] EM_A[2] EM_A[3] EM_A[3] EM_A[4] EM_A[4] EM_A[5] EM_A[5] EM_A[6] EM_A[6] ...

  • Page 72

    ... Register) Figure 3-5. MSTPRI0 Register RESERVED R-0000 0000 0000 C64X+_CFGP RSV ARM_CFGP R/W-001 R-0 R/W-001 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com Table 3-12. The priority levels Figure 3 (1) VICPP R/W-101 RSV ARM_DMAP R-0 R/W-001 Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 73

    ... SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Figure 3-6. MSTPRI1 Register 23 22 HPIP R/W-100 USBP RSV RESERVED R/W-100 R-0 R-100 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 RSV VLYNQP R-0 R/W-100 RSV EMACP R-0 R/W-100 Device Configurations 73 ...

  • Page 74

    ... EMIFA: VLYNQ: EM_CS5 VLYNQ_CLOCK EMIFA: VLYNQ: EM_CS4 VLYNQ_SCRUN EMIFA: VLYNQ: EM_A[21:14] VLYNQ_TXD[0:3], VLYNQ_RXD[0:3] EMIFA: EM_A[13:3] Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com Section Section 3.5.3, Peripheral Selection After SECONDARY TERTIARY (3) REGISTER/PIN REGISTER/PIN CONTROL CONTROL PinMux0:HPIEN Pins:BTSEL[1: PinMux0:ATAEN PinMux0:HPIEN PinMux0:ATAEN PinMux0:HPIEN ...

  • Page 75

    ... UART1: TXD, RXD DMACK,DMARQ UART2: UART_RXD2, UART2: UART_CTS2, Memory Stick/Memory Stick PRO: CLK, BS, DATA[3:0] Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 SECONDARY TERTIARY (3) REGISTER/PIN REGISTER/PIN CONTROL CONTROL PinMux1:ASP PinMux1:UART0 PinMux1:SPI PinMux1:SPI PinMux0:HDIREN ...

  • Page 76

    ... Figure 3-7. PINMUX0 Register CWE LFLDEN LOEEN RGB888 R/W-0 R/W-0 R/W-0 R/W AECS5 AECS4 RESERVED R/W-0 R/W-0 R-00000 Description Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com 2.7, Terminal Functions. Section 3.5.4, Section 3.5.6, Pin Table 3-14. More details on ( RGB666 RESERVED ATAEN HDIREN R/W-0 R-0000 R/W-0 R/W AEAW R/W-LLLLL Copyright © ...

  • Page 77

    ... Figure 3-8. PINMUX1 Register RESERVED R-0000 0000 0000 MSKT SPI I2C PWM2 PWM1 PWM0 Description Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 TIMIN CLK1 R/W-0 R/W U2FLO UART2 UART1 ...

  • Page 78

    ... Table 3-17. PIN FUNCTIONALITY SELECTED GPIO3V EMAC GPIO EMAC TXEN TXCLK COL TXD[0] TXD[1] TXD[2] TXD[3] RXD[0] RXD[1] RXD[2] RXD[3] RXCLK RXDV RXER CRS MDIO MDCLK Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 79

    ... PWM1 - - PWM2 - R1/ LFLDEN GPIO[38 GPIO[38 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 C_WE/ LCD_OE/ GPIO[1] GPIO[0] - GPIO[0] - LCD_OE GPIO[1] - C_WE - - - - - - - - - Table 3-19 MULTIPLEXED PINS C_FIELD/ LCD_FIELD/ R0/ ...

  • Page 80

    ... UART_TXD1 1 - UART_TXD1 0 0 DMACK 0 1 DMACK 1 - DMACK 0 0 UART_TXD1 0 1 UART_TXD1 1 - UART_TXD1 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com Table 3-21. If ATA pin Table 3-22. When (1) EM_BA[1]/ EM_A[0]/ EM_D[15:0]/ DIOW/ GPIO[52]/ GPIO[53]/ DD[15:0] EM_WE ATA1 ATA2 EM_WE EM_BA[1]/ EM_A[0]/ EM_D[15:0] (2) (2) GPIO[52] ...

  • Page 81

    ... GPIO[12] GPIO[13] GPIO[14] VL_TXD1 VLRXD1 EM_A[17]/ GPIO[14] VL_TXD1 VLRXD1 VL_TXD2 VL_TXD1 VLRXD1 VL_TXD2 Table 3-9. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 MULTIPLEXED PINS EM_CS4/ GPIO[9]/ VLYNQ_SCRUN GPIO[9] EM_CS4 GPIO[9] EM_CS4 GPIO[9] EM_CS4 VLYNQ_SCRUN EM_A[16]/ EM_A[15]/ EM_A[14]/ GPIO[15]/ GPIO[16]/ GPIO[17]/ VL_RXD2 ...

  • Page 82

    ... SP_EN1 SPI_DO 1 HDDIR SPI_DO MULTIPLEXED PINS I2C_CLK/ I2C_DATA/ I2C GPIO[43] GPIO[44] 0 GPIO[43] GPIO[44] 1 I2C_CLK I2C_DATA Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com Table 3-25. FSR/ DX/ DR/ GPIO[32] GPIO[33] GPIO[34] GPIO[32] GPIO[33] GPIO[34] FSR DX DR MULTIPLEXED PINS SPI_DI/ SPI_CLK/ SPI_EN0/ GPIO[40] ...

  • Page 83

    ... MULTIPLEXED PINS PWM2/ PWM0 RGB888 B2/ GPIO[47 GPIO[47 PWM2 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Section 3.5.6.3, VPBE (RGB666 PWM1/ PWM0/ R2/ GPIO[45] GPIO[46] GPIO[46] GPIO[45] R2 GPIO[45] - PWM0 PWM1 - - - Device Configurations 83 ...

  • Page 84

    ... DMARQ 1 UART_TXD1 UART_RXD1 MULTIPLEXED PINS UART_TXD0/ UART_RXD0/ GPIO[36] GPIO[35] 0 GPIO[36] GPIO[35] 1 UART_TXD0 UART_RXD0 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com shows how UART2 selection reduces the Table 3-31. If the ATA module is CCD[12]/ CI[4]/ UART_RTS2 CCD[12]/ (1) (1) CI[4] CCD[12]/ (1) (1) CI[4] UART_RTS2 Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 85

    ... DIOR/ DIOW/ EM_A[2] IORDY EM_OE EM_WE EM_WAIT EM_OE EM_WE EM_A[2] IORDY DIOR DIOW EM_A[2] HRDY HDS1 HDS2 HCNTLA Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 HCNTLB/ HINT/ HD[15:0]/ ATA2/ ATA0/ DD[15:0]/ EM_A[0] EM_BA[0] EM_D[15:0] (1) (1) EM_A[0] EM_BA[0] EM_D[15:0] (1) (1) EM_A[0] ATA0 DD[15:0] HCNTLB ...

  • Page 86

    ... PWM2 PWM1 PWM0 SPI UART2 SRC SRC SRC SRC SRC R/W USB RESERVED SRC R/W-0 R-0 00 Table 3-34. SUSPSRC Register Descriptions Description Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com UART1 UART0 I2C ASP SRC SRC SRC SRC SRC R/W-0 R/W-0 R/W-0 R/W EMAC ...

  • Page 87

    ... EMACSRC Ethernet MAC emulation suspend source 0 = ARM emulation suspend 1 = DSP emulation suspend RESERVED Reserved Copyright © 2006–2010, Texas Instruments Incorporated SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Description Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 Device Configurations 87 ...

  • Page 88

    ... System Interconnect 4-1. Table 4-1. System Connection Matrix SLAVE C64x+ ARM DDR2 MEMORY CONTROLLER Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com Figure Figure 4-1, Bridge 8 (1) SCR3 ...

  • Page 89

    ... ARM Bridge3 TCM 64 32 Bridge5 64 32 Bridge6 SCR6 32 32 SCR3 32 32 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 DSP/2 Clock Rate DSP/3 Clock Rate DSP/6 Clock Rate MXI/CLKIN Rate EDMA3CC Bridge8 SCR4 EDMA3TC0 EDMA3TC1 32 32 Bridge9 32 UART0 32 32 ...

  • Page 90

    ... DD1P8 I/O, 3. I/O, 1. I/O, 3. I/O, 1.8V O (default) (default) SSA1P2LDO SS. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com ( 1.5 V DDDSP - 2.5 V DD18 DDA_1P8V -0 4 2 4 2.5 V 0°C to 85°C -55°C to 150°C . Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 91

    ... SSA_1P1V SSDLL , USB_V , SSA3P3 SSA1P2LDO 0.49DV SS DDR2 SSA_1P8V Default 1.05 V core 1.2 V core SSA1P2LDO of the transmitting device and to track variations in the DV DDR2 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 MIN NOM MAX 1.00 1.05 1.10 1.15 1.2 1.25 3.15 3.3 3.45 1.71 1.8 1. 0.5DV ...

  • Page 92

    ... Timer0 at 100% utilization. At room temperature (25°C) for typical process devices. The actual current draw varies across manufacturing processes and is highly application-dependent. For more details on core and I/O activity, as well as information relevant to board power supply design, see the TMS320DM6441 Power Consumption Summary application report (literature number SPRAAU3). ...

  • Page 93

    ... For 3.3 V I/O, ref = 0.9 V. ref Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Data Manual Timing Reference Point Output Under Test Device Pin (see note) ...

  • Page 94

    ... DDDSP and Figure 6-4 describe the power-on sequence timing requirements for supplies. DDDSP 3.2.1, Power Configurations at Reset. Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com (or between V and DD18 DDDSP supply must be powered up before the ...

  • Page 95

    ... DD33 and DV supplies may be powered up in any order of DD18 DDR2 DD33 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Figure 6-4) 1.05 V and 1.2 V MIN MAX (1) 0 Table 6-2 supply power-up, not the ...

  • Page 96

    ... PLL2 Clock Domain Block Diagram). 96 Peripheral and Electrical Specifications pins of the DM6441. Table 6-3 DDDSP Table 6-4 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com pins of the DM6441. DD provides a listing of the DM6441 power (DM6441 Clock Domains) and Figure 6-6 Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 97

    ... PLL Bypass – 27 MHz 1:1 27 MHz 1:2 13.5 MHz 1:3 9 MHz 1:6 4.5 MHz Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 (1) Clock Modes (Frequency) PLL Enabled 405 MHz 405 MHz 202.5 MHz 135 MHz 67.5 MHz Peripheral and Electrical Specifications 97 ...

  • Page 98

    ... SYSCLK3 SCR EDMA3 VPFE VPBE DACs DDR2 PHY DDR2 VTP DDR2 Mem Ctlr Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com UARTs (x3) I2C PWMs (x3) Timers (x3) USB PHY 24 MHz 60 MHz USB 2.0 VLYNQ EMAC ATA/CF ...

  • Page 99

    ... SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 PLLEN Post−DIV 1 0 BPDIV PLLEN Post−Div 1 (/1) 0 BPDIV Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 PLLDIV1 (/1) SYSCLK1 PLLDIV2 (/2) SYSCLK2 PLLDIV3 (/3) SYSCLK3 PLLDIV4 (/4) SYSCLK4 PLLDIV5 (/6) SYSCLK5 AUXCLK SYSCLKBP PLL2_SYSCLK1 PLLDIV1 (VPSS−VPBE) ...

  • Page 100

    ... Power Error Pending Register - Reserved Power Error Clear Register - Reserved External Power Error Pending Register - Reserved External Power Control Clear Register Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com 6-5. The PSC Register memory map is 2.8.3, Documentation Support, for the LPSC Peripheral/Module Number 28 TIMER1 29 Reserved 30 ...

  • Page 101

    ... Module Status 28 Register (TIMER1) - Reserved Module Status 39 Register (C64x+ CPU) Module Status 40 Register (VICP) - Reserved Module Control 0 Register (VPSS DMA) Module Control 1 Register (VPSS MMR) Module Control 2 Register (EDMA3CC) Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 DESCRIPTION Peripheral and Electrical Specifications 101 ...

  • Page 102

    ... Module Control 25 Register (PWM2) Module Control 26 Register (GPIO) Module Control 27 Register (TIMER0) Module Control 28 Register (TIMER1) - Reserved Module Control 39 Register (C64x+ CPU) Module Control 40 Register (VICP) - Reserved Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com DESCRIPTION Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 103

    ... MMR controls the C64x+ reset input. This is used for control of C64x+ reset by the ARM. The C64x+ Slave DMA port is still alive when in local reset. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 Section 3, Device Configurations, Peripheral and Electrical Specifications 103 ...

  • Page 104

    ... RESET high until the DDR2 controller is enabled via the PSC. 104 Peripheral and Electrical Specifications (see Figure 6-9) Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com Figure 6-9) 1.05 V and 1.2 V UNIT MIN MAX 444 ...

  • Page 105

    ... TRST , YI/CCD[7:0], CI[3:0]/CCD[11:8], CI4/CCD12/UART_RTS2, EM_CS2 EM_OE RE IORD DIOR , /( )/( )/ Figure 6-9. Reset Timing Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 EM_CS3 EM_WE WE IOWR DIOW , /( )/( )/ ...

  • Page 106

    ... Do not connect to board ground (V SS MXO MXV SS C2 Figure 6-10. 27-MHz System Oscillator pin Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com Section 6.5.1, Section 6.5.2, Clock ). The SS . DD18 MXV DD 1.8 V Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 107

    ... Do not connect to board ground (V SS M24XO M24V SS C2 Figure 6-11. 24-MHz USB Oscillator pin Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 MIN TYP MAX UNIT MHz 60 Ω ±50 ppm ). SS M24V DD 1.8 V MIN TYP MAX UNIT 4 ms ...

  • Page 108

    ... The MXI/CLKIN pin is connected to the 1.8-V pin can be connected to the same 1.8-V power supply MXV MXO NC pin is connected to board ground (V SS Table 6-17, Timing Requirements for M24XI Devices. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com pin is connected The DD18 Table 6-16, Timing Requirements MXV ...

  • Page 109

    ... PLL Controller 2 Clock Enable Register PLL Controller 2 Clock Status Register (For All Clocks Except SYSCLKx) Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-12. For more details, see the DESCRIPTION Peripheral and Electrical Specifications ...

  • Page 110

    ... PLL Controller 2 System Clock Status 1 Register (Indicates SYSCLK on/off Status recommends EMI filter DM644x PLLV DD18 C2 0.1 µF 0.01 µF Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com DESCRIPTION DD18 , as shown in Figure 6-13. The 1.8-V DD18 manufacturer Murata, part number Figure 6-13. For PLL1 PLL2 Copyright © ...

  • Page 111

    ... DD At 1.05 1.2 MIN 20 At 1.05-V CV 400 DD At 1.2-V CV 400 DD 6-15. MIN TYP 150 (1) 128C Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 MAX UNIT 30 MHz 405 MHz 513 MHz 405 MHz 513 MHz MAX UNIT 30 MHz 600 MHz 900 MHz Table 6-15. Table 6-15 ...

  • Page 112

    ... EMIF transactions that include extended wait states inserted during the STROBE MAX and Figure 6-14. MXI/CLKIN Timing (1) (2) (3) MAX and Figure 6-15. M24XI Timing Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com (1) (2) (3) (4) (see Figure 6-14) 1.05 V and 1.2 V UNIT MIN MAX 33.3 50 0.45C 0.55C 0.45C 0.55C 0.05C 0.02C MIN ...

  • Page 113

    ... Delay time, CLKIN/MXI high to CLK_OUT0 high (divide-by-2 only) MAX and Figure 6-16. CLK_OUT0 Timing Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 (1) (2) 1.05 V and 1.2 V MIN MAX 37.037 74.074 0.45P 0.55P 0.45P 0.55P ...

  • Page 114

    ... Delay time, CLKIN/MXI high to CLK_OUT1 low (divide-by-2 only) Delay time, CLKIN/MXI high to CLKOUT1 high (divide-by-2 only) MAX and Figure 6-17. CLK_OUT1 Timing Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com (1) (2) 1.05 V and 1.2 V MIN MAX 41.667 83.33 0.45P 0.55P 0.45P 0.55P ...

  • Page 115

    ... TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14). Copyright © 2006–2010, Texas Instruments Incorporated SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 Table 6-21 shows Peripheral and Electrical Specifications 115 ...

  • Page 116

    ... GPIOBNK0 57 GPIOBNK1 58 GPIOBNK2 59 GPIOBNK3 GPIOBNK4 60 61 COMMTX 62 COMMRX 63 EMUINT Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com SOURCE Timer 0 – TINT12 Timer 0 – TINT34 Timer 1 – TINT12 Timer 1 – TINT34 PWM 0 PWM 1 PWM 2 I2C I2C UART 0 UART 1 UART 2 SPI SPI ...

  • Page 117

    ... Interrupt Entry Table Base Address Register Reserved Interrupt 0-7 Priority Select Interrupt 8-15 Priority Select Interrupt 16-23 Priority Select Interrupt 24-31 Priority Select Interrupt 32-39 Priority Select Interrupt 40-47 Priority Select Interrupt 48-55 Priority Select Interrupt 56-63 Priority Select Reserved Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 Peripheral and Electrical Specifications 117 ...

  • Page 118

    ... INTERR 96 EMC_IDMAERR 100 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com Table 6-22. Also, the interrupt ACRONYM SOURCE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ...

  • Page 119

    ... PMCDMPA 122 DMCCMPA 123 DMCDMPA 124 UMCCMPA 125 UMCDMPA 126 EMCCMPA 127 EMCDMPA Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SOURCE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved C64x+ PMC Reserved Reserved Reserved C64x+ UMC 1 ...

  • Page 120

    ... INTMUX3 Interrupt mux register 3 – Reserved INTXSTAT Interrupt exception status INTXCLR Interrupt exception clear INTDMASK Dropped interrupt mask register EVTASRT Event assert register Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com REGISTER DESCRIPTION ...

  • Page 121

    ... INT RESERVED DSP3 DSP2 DSP1 R-0000 R/W-0 R/W-0 R/W-0 Description (1) (1) (1) (1) (1) (1) (1) (2) (2) (2) (2) (2) (2) (2) Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 DSP0 RESERVED STAT STAT R/W-0 R-000 R/W INT INT RESERVED DSP0 R/W-0 R-000 R/W-0 Peripheral and Electrical Specifications 16 NMI 0 ...

  • Page 122

    ... The memory map for the GPIO registers is shown in see the TMS320DM644x DMSoC General-Purpose Input/Output (GPIO) User's Guide (literature number SPRUE25). 122 Peripheral and Electrical Specifications Table 6-25. For more detailed information on GPIOs, Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com ...

  • Page 123

    ... GPIO Bank 4 Set Falling Edge Interrupt Register (GPIO[64:70]) GPIO Bank 4 Clear Falling Edge Interrupt Register (GPIO[64:70]) INSTAT4 GPIO Bank 4 Interrupt Status Register (GPIO[64:70]) - Reserved Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 REGISTER NAME Peripheral and Electrical Specifications 123 ...

  • Page 124

    ... Peripheral and Electrical Specifications (1) (see Figure 6-19) PARAMETER Figure 6-19. GPIO Port Timing 2 1 Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com (see Figure 6-19) 1.05 V and 1.2 V UNIT MIN MAX 1.05 V and 1.2 V UNIT MIN ...

  • Page 125

    ... Copyright © 2006–2010, Texas Instruments Incorporated SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 EVENT DESCRIPTION Reserved ASP Transmit Event ASP Receive Event VPSS Histogram Event VPSS H3A Event VPSS Previewer Event Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 (1) Peripheral and Electrical Specifications 125 ...

  • Page 126

    ... GPIO Bank 2 Interrupt GPIO Bank 3 Interrupt GPIO Bank 4 Interrupt Reserved Timer 0 Interrupt Timer 1 Interrupt Watchdog timer Interrupt Timer 3 Interrupt PWM 0 Event PWM 1 Event PWM 2 Event Reserved Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com ...

  • Page 127

    ... DMA Region Access Enable Register for Region 3 DRAEH3 DMA Region Access Enable Register High for Region 3 – Reserved Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 REGISTER NAME Peripheral and Electrical Specifications 127 ...

  • Page 128

    ... Reserved QSTAT0 Queue 0 Status Register QSTAT1 Queue 1 Status Register Reserved QWMTHRA Queue Watermark Threshold A Register for Q[3:0] – Reserved CCSTAT EDMA3CC Status Register Reserved Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com REGISTER NAME Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 129

    ... Event Clear Register ECRH Event Clear Register High ESR Event Set Register ESRH Event Set Register High CER Chained Event Register CERH Chained Event Register High Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 REGISTER NAME Peripheral and Electrical Specifications 129 ...

  • Page 130

    ... Event Enable Clear Register High EESR Event Enable Set Register EESRH Event Enable Set Register High SER Secondary Event Register SERH Secondary Event Register High Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com REGISTER NAME Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 131

    ... Reserved IER Interrupt Enable Register IERH Interrupt Enable Register High IECR Interrupt Enable Clear Register IECRH Interrupt Enable Clear Register High IESR Interrupt Enable Set Register Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 REGISTER NAME Peripheral and Electrical Specifications 131 ...

  • Page 132

    ... IPRH Interrupt Pending Register High ICR Interrupt Clear Register ICRH Interrupt Clear Register High IEVAL Interrupt Evaluate Register - Reserved QER QDMA Event Register Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com REGISTER NAME Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 133

    ... DFDSTBREF Register - Reserved DFOPT0 EDMA3 TC0 Destination FIFO Options Register 0 DFSRC0 EDMA3 TC0 Destination FIFO Source Address Register 0 DFCNT0 EDMA3 TC0 Destination FIFO Count Register 0 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 REGISTER NAME Table 6-31) Peripheral and Electrical Specifications 133 ...

  • Page 134

    ... EDMA3 TC1 Source Active Destination Address Register SABIDX EDMA3 TC1 Source Active Source B-Index Register SAMPPRXY EDMA3 TC1 Source Active Memory Protection Proxy Register Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com REGISTER NAME Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 135

    ... EDMA3 TC1 Destination FIFO Count Register 3 DFDST3 EDMA3 TC1 Destination FIFO Destination Address Register 3 DFBIDX3 EDMA3 TC1 Destination FIFO BIDX Register 3 DFMPPRXY3 EDMA3 TC1 Destination FIFO Memory Protection Proxy Register 3 - Reserved Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 REGISTER NAME Peripheral and Electrical Specifications 135 ...

  • Page 136

    ... ACRONYM OPT SRC A_B_CNT DST SRC_DST_BIDX LINK_BCNTRLD SRC_DST_CIDX CCNT Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com Table 6-32 PARAMETER ENTRY Option Source Address A Count, B Count Destination Address Source B Index, Destination B Index Link Address, B Count Reload Source C Index, Destination C Index C Count ...

  • Page 137

    ... SPRUE19) and the TMS320DM644x DMSoC Asynchronous External Memory Interface (EMIF) Reference Guide (literature number SPRUE20). Copyright © 2006–2010, Texas Instruments Incorporated SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 6-33. For more details on the EMIFA Peripheral and Electrical Specifications 137 ...

  • Page 138

    ... NAND Flash 1 ECC Register (CS2 Space) NANDF2ECC NAND Flash 2 ECC Register (CS3 Space) NANDF3ECC NAND Flash 3 ECC Register (CS4 Space) NANDF4ECC NAND Flash 4 ECC Register (CS5 Space) - Reserved Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com REGISTER NAME Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 139

    ... SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 (see Figure 6-21 and Figure 6-22) READS and WRITES READS (2) WRITES (2) describe EMIF transactions that include extended wait states inserted during the STROBE Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 (1) 1.05 V and 1.2 V UNIT MIN MAX 10.4 ...

  • Page 140

    ... E - 0.7 ( 0.9 ( 1.7 ( 2.3 ( 1.8 ( 2.6 (WST + (WST + ( 2.2 Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com and Figure 6-22) 1.05 V and 1.2 V UNIT MIN MAX ( (RS + RST + ...

  • Page 141

    ... Figure 6-21. Asynchronous Memory Read Timing for EMIF Copyright © 2006–2010, Texas Instruments Incorporated SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Figure 6-21 and Figure ( 2 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 6-22) (continued) 1.05 V and 1.2 V UNIT MIN MAX ( 1 ...

  • Page 142

    ... EM_WAIT Figure 6-23. EM_WAIT Read Timing Requirements 142 Peripheral and Electrical Specifications 15 24 STROBE Extended Due to EM_WAIT Asserted Deasserted Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com STROBE HOLD ...

  • Page 143

    ... A memory map of the DDR2 memory controller registers is shown in Copyright © 2006–2010, Texas Instruments Incorporated SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 STROBE Extended Due to EM_WAIT Asserted Deasserted Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 STROBE HOLD Table 6-36. Peripheral and Electrical Specifications 143 ...

  • Page 144

    ... Reserved DDRPHYCR DDR PHY Control Register - Reserved VTPIOCR VTP IO Control Register - Reserved (1) (2) (see Figure PARAMETER 1 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com REGISTER NAME 6-25) 1.05 V 1.2 V UNIT MIN MAX MIN MAX 7 Copyright © 2006–2010, Texas Instruments Incorporated ns ...

  • Page 145

    ... Multiword DMA Recovery Timing Register Ultra-DMA Strobe Timing Register Ultra-DMA Ready-to-Pause Timing Register Ultra-DMA Timing Envelope Register Primary IO Ready Timer Configuration Register Reserved Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Peripheral and Electrical Specifications 145 ...

  • Page 146

    ... Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com is provided at the DM6441 device assume correct configuration of (1) (2) (see Figure 6-26) 1.05 V and 1.2 V UNIT MIN MAX ns 12P - 1.6 ns (DATSTB + 1 – ns (DATRCVR + 1 ...

  • Page 147

    ... Copyright © 2006–2010, Texas Instruments Incorporated (no wait is generated data is driven valid Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 (wait is generated) RD ...

  • Page 148

    ... MODE 0-2 (DMASTB + DMARCVR + 2)P - 0.5 0 0-2 0 0-2 0-2 0-2 0-2 0 0-1 2 0-2 0-2 0 1-2 Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com (1) (2) (see Figure 6-27) 1.05 V and 1.2 V UNIT MIN MAX ns (DMASTB + 1 150 (DMASTB)P ns 100 ...

  • Page 149

    ... Figure 6-27. ATA/CF Multiword DMA Timing Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Peripheral and Electrical Specifications 149 ...

  • Page 150

    ... Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com (1) (2) 1.05 V and 1.2 V UNIT MIN MAX 25 MHz 240 160 120 6.7 6 (UDMASTB 6.7 230 ...

  • Page 151

    ... UI t ENV t ENV t ZIORDY t ZFS ACK Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 1.05 V and 1.2 V MIN MAX (TENV + 1 160 125 100 ZAD ZAD ...

  • Page 152

    ... CYC the device, it may be different at the host due to propagation delay CYC ZAH Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com RFS t MLI t ACK t ACK t IORDYZ t CVH t CVS CRC t ACK Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 153

    ... ZAH ACK t ENV ZIORDY t ACK t ACK Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 t MLI t ACK t ACK t MLI t IORDYZ t CVS t CVH CRC t ACK DZFS t DVH t DVS ...

  • Page 154

    ... DVS t DVH t DVS at the host, it may be different at the device due to propagation delay CYC t RFS Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com t 2CYC t DVH MLI t ACK t IORDYZ t ACK t CVS ...

  • Page 155

    ... Figure 6-37. ATA/CF Device Terminating an Ultra DMA Data-Out Burst Timing Copyright © 2006–2010, Texas Instruments Incorporated RFS t LI Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 t ACK t MLI t IORDYZ t ACK t MLI t ...

  • Page 156

    ... A. t one cycle C Figure 6-39. ATA/CF HDDIR PIO Postwrite Start Timing 156 Peripheral and Electrical Specifications show the behavior of HDDIR for the different types of transfers. ( Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com (1) 1.05 V and 1.2 V UNIT MIN MAX E - 3.1 2 ...

  • Page 157

    ... Figure 6-41. ATA/CF HDDIR Ultra DMA Write Transfer Timing Copyright © 2006–2010, Texas Instruments Incorporated ( ( Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 ( CRC Peripheral and Electrical Specifications 157 ...

  • Page 158

    ... Reserved MMC Command Index Register Reserved SDIO Control Register SDIO Status Register 0 SDIO Interrupt Enable Register SDIO Interrupt Status Register MMC FIFO Control Register Reserved Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com ...

  • Page 159

    ... Copyright © 2006–2010, Texas Instruments Incorporated SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 (see Figure 6-43 and Figure 6-45) Figure 6-42 through Figure PARAMETER Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 1.05 V and 1.2 V UNIT MIN MAX 6-45) 1.05 V and 1.2 V ...

  • Page 160

    ... Peripheral and Electrical Specifications XMIT Valid Valid Valid Valid Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com 13 13 Valid END Valid END END End Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 161

    ... MHz . 4 4332628318 - pal sc è ø 1017 6.5.1, Clock Input Option 1 – Crystal. Alternatively, if the VPBE input Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Description MHz MHz Peripheral and Electrical Specifications 161 ...

  • Page 162

    ... VPFE – Preview Engine/Image Signal Processor RESZ VPFE – Resizer HIST VPFE – Histogram H3A VPFE – Hardware 3A (Auto-Focus/WB/Exposure) VPSS VPSS Shared Buffer Logic Registers Table 6-48. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com REGISTER NAME Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 163

    ... Program Entries 8-15 for Even Line Program Entries 0-7 for Odd Line Program Entries 8-15 for Odd Line Video Port Output Settings Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 DESCRIPTION Peripheral and Electrical Specifications 163 ...

  • Page 164

    ... Line Offset for the Read Data Dark Frame Address From SDRAM Line Offset for the Dark Frame Data Write Address to the SDRAM Line Offset for the Write Data Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com DESCRIPTION ...

  • Page 165

    ... Color Space Conversion Coefficients Color Space Conversion Coefficients Color Space Conversion Offsets Contrast and Brightness Settings Chrominance Suppression Settings Maximum/Minimum Y and C Settings Setup Table Addresses Setup Table Data Table 6-50. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 DESCRIPTION Peripheral and Electrical Specifications 165 ...

  • Page 166

    ... Vertical Filter Coefficients 21 and 20 Vertical Filter Coefficients 23 and 22 Vertical Filter Coefficients 25 and 24 Vertical Filter Coefficients 27 and 26 Vertical Filter Coefficients 29 and 28 Vertical Filter Coefficients 31 and 30 Luminance Enhancer Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com DESCRIPTION ...

  • Page 167

    ... Start Position and Height for Black Line of AE/AWB Windows Configuration for Subsample Data in AE/AWB Window SDRAM/DDRAM Start Address for AE/AWB Engine Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 DESCRIPTION Peripheral and Electrical Specifications 167 ...

  • Page 168

    ... Separate vertical start coordinate and height for a black row of paxels that is different than the remaining color paxels. • Programmable horizontal sampling points in a window. • Programmable vertical sampling points in a window. 168 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com ...

  • Page 169

    ... Read Address From DDR2 Memory Register Read Address Offset for Each Line in the DDR2 Memory Register Horizontal/Vertical Information Register (Horizontal/Vertical Number of Pixels When Data is Read From DDR2 Memory Information Register) Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 DESCRIPTION Peripheral and Electrical Specifications 169 ...

  • Page 170

    ... PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced. 170 Peripheral and Electrical Specifications 1 Figure 6-46. VPFE PCLK Timing Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com Figure 6-46) 1.05 V and 1.2 V UNIT MIN MAX (1) 10 ...

  • Page 171

    ... Figure 6-48. VPFE (CCD) Master Mode Input Data Timing Copyright © 2006–2010, Texas Instruments Incorporated SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 11 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 (1) (see Figure 6-48) 1.05 V and 1.2 V UNIT MIN MAX ...

  • Page 172

    ... HD VD C_FIELD Figure 6-49. VPFE (CCD) Master Mode Control Output Data Timing 172 Peripheral and Electrical Specifications Figure 6-49 Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com 1.05 V 1.2 V UNIT MIN MAX MIN MAX 0 ...

  • Page 173

    ... Copyright © 2006–2010, Texas Instruments Incorporated Table 6-57. Table 6-57. VPBE Register Descriptions PID Peripheral Revision and Class Information Register PCR Peripheral Control Register Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Description Peripheral and Electrical Specifications 173 ...

  • Page 174

    ... Video Window 1 X-Position Video Window 1 Y-Position Video Window 1 X-Size Video Window 1 Y-Size OSD Bitmap Window 0 X-Position OSD Bitmap Window 0 Y-Position OSD Bitmap Window 0 X-Size Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com Description Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 175

    ... Window 1 Bitmap Value to Palette Map C/D Window 1 Bitmap Value to Palette Map E/F Reserved Reserved Miscellaneous Control CLUT RAMYCB Setup CLUT RAM Setup CLUT RAM Setup Reserved Ping-Pong Video Window 0 Address Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 Peripheral and Electrical Specifications 175 ...

  • Page 176

    ... Master/slave operation • Internal color bar generation (100%/75%) The VENC register memory mapping including the digital LCD and DACs is shown in 176 Peripheral and Electrical Specifications Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com Table 6-59. ...

  • Page 177

    ... Vertical DCLK Mask Start Vertical DCLK Mask Range Caption Control Caption Data Odd Field Caption Data Even Field Video Attribute Data # 0 Video Attribute Data # 1 Video Attribute Data # 2 Reserved Video Status Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 Peripheral and Electrical Specifications 177 ...

  • Page 178

    ... Vertical Data Valid Start Position for Even Field OSD Clock Control 0 OSD Clock Control 1 Horizontal Valid Culling Control 0 Horizontal Valid Culling Control 1 OSD Horizontal Sync Advance Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com ...

  • Page 179

    ... PCLK 6 VPBECLK Figure 6-50. VPBE PCLK and VPBECLK Timing Copyright © 2006–2010, Texas Instruments Incorporated SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 Figure 6-50) 1.05 V and 1.2 V UNIT MIN MAX 13.33 160 ns 5 ...

  • Page 180

    ... Figure 6-51. VPBE Input Timing With Respect to PCLK and VPBECLK 180 Peripheral and Electrical Specifications (see Figure 6-51 Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com (1) 1.05 V and 1.2 V UNIT MIN MAX ...

  • Page 181

    ... B. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0] Figure 6-52. VPBE Output Timing With Respect to PCLK and VPBECLK Copyright © 2006–2010, Texas Instruments Incorporated PARAMETER 11, 29 13, 31 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 (1) (see Figure 6-52) 1.05 V 1.2 V MIN ...

  • Page 182

    ... MODE MIN 13.33 ( 1.3 ( 1.3 ( 0 2.3 1.9 RGB 2.8 YCC 2.8 RGB 2.3 YCC 2.6 Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com 6-53) 1.2 V UNIT MAX MIN MAX 160 13.33 160 ns (4) ( 0.3 ns (4) ( 0.3 ns (4) ...

  • Page 183

    ... Figure 6-53. VPBE Control and Data Output Timing With Respect to VCLK Copyright © 2006–2010, Texas Instruments Incorporated SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 Peripheral and Electrical Specifications 183 ...

  • Page 184

    ... OUT MHz CLK F = 2.0 MHz OUT MHz CLK F = 2.0 MHz OUT Low-Pass Filter I Amplifier f = 6.5 MHz OUT c Gain = 5.6 V 500 LOAD Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com 1.05 V and 1.2 V MIN TYP MAX -1.0 1.0 -0.5 0.5 0.5 5 500 200 0.475 0.5 0.525 3.8 4.0 4.2 1.05 V and 1.2 V MIN TYP MAX 27 60 ...

  • Page 185

    ... Copyright © 2006–2010, Texas Instruments Incorporated Figure 6-55. USBPHY_CTL Register RESERVED R-0000 0000 0000 0000 0000 000 PHYPLLON CLKO1SEL R/W-0 R/W-0 Description Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Figure 6-55 and Table 6-66 PHYCLKGD R OSCPDWN RSV ...

  • Page 186

    ... TX/RX CCPI Channel 0 State Block TX CPPI DMA State Word 0 TX CPPI DMA State Word 1 TX CPPI DMA State Word 2 TX CPPI DMA State Word 3 TX CPPI DMA State Word 4 Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com ...

  • Page 187

    ... RX CPPI DMA State Word 2 RX CPPI DMA State Word 3 RX CPPI DMA State Word 4 RX CPPI DMA State Word 5 RX CPPI DMA State Word 6 RX CPPI Completion Pointer Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 Peripheral and Electrical Specifications 187 ...

  • Page 188

    ... Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) Number of bytes in host RX endpoint FIFO. (Index register set to select Endpoints Defines the speed of Endpoint 0 Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com ...

  • Page 189

    ... Port of the hub that has to be accessed through the associated RX Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high speed hub Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 Peripheral and Electrical Specifications 189 ...

  • Page 190

    ... Port of the hub that has to be accessed through the associated RX Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high speed hub Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com ...

  • Page 191

    ... Sets the operating speed, transaction protocol and peripheral endpoint number for the host RX endpoint. Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host RX endpoint. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 Peripheral and Electrical Specifications 191 ...

  • Page 192

    ... Sets the operating speed, transaction protocol and peripheral endpoint number for the host RX endpoint. Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host RX endpoint. Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com ...

  • Page 193

    ... USB USB_V USB_R1 SSREF ( ±1% ± close to the device as possible. Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 1.05 V and 1.2 V FULL SPEED HIGH SPEED 12 Mbps 480 Mbps MAX MIN MAX MIN MAX ...

  • Page 194

    ... UART0 Line Status Register Reserved Reserved UART0 Divisor Latch (LSB) UART0 Divisor Latch (MSB) Peripheral Identification Register 1 Peripheral Identification Register 2 UART0 Power and Emulation Management Register Reserved Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com Table 6-71. Copyright © 2006–2010, Texas Instruments Incorporated ...

  • Page 195

    ... UART2 Divisor Latch (LSB) UART2 Divisor Latch (MSB) Peripheral Identification Register 1 Peripheral Identification Register 2 UART2 Power and Emulation Management Register Reserved Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Peripheral and Electrical Specifications 195 ...

  • Page 196

    ... Figure 6-58) PARAMETER 3 2 Start Bit Data Bits 5 4 Start Bit Data Bits Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com (1) (see Figure 6-58) 1.05 V and 1.2 V UNIT MIN MAX 0.96U 1.05U ns 0.96U 1.05U ns 1.05 V and 1.2 V ...

  • Page 197

    ... SPI Data Format Register 1 SPI Data Format Register 2 SPI Data Format Register 3 SPI Interrupt Vector Register 0 SPI Interrupt Vector Register 1 Reserved Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 REGISTER NAME Peripheral and Electrical Specifications 197 ...

  • Page 198

    ... Polarity = 0) SPIx_CLK (Clock Polarity = 1) 198 Peripheral and Electrical Specifications ( Figure 6-59. SPI_CLK Timing Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com (see Figure 6-59) 1.05 V 1.2 V UNIT MIN MAX MIN MAX 44.4 56888.89 30.3 56888. ...

  • Page 199

    ... Clock Polarity = 0 Clock Polarity = 1 [Clock Phase = 0] (see Figure 6-60) PARAMETER Clock Polarity = 0 Clock Polarity = MSB IN DATA 8 9 MSB OUT DATA Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 TMS320DM6441 (1) (see Figure 6-60) 1.05 V and 1.2 V UNIT MIN MAX 0.5P + 9.4 ns 0.5P + 9.4 ns 0.5P - 4.5 ns 0.5P - 4.5 ns 1.05 V and 1.2 V UNIT MIN MAX ...

  • Page 200

    ... Clock Polarity = 0 Clock Polarity = 1 [Clock Phase = 1] (see Figure 6-61) PARAMETER Clock Polarity = 0 Clock Polarity = MSB IN DATA 17 MSB OUT DATA Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 www.ti.com (1) (see Figure 6-61) 1.05 V and 1.2 V MIN MAX 0.5P + 9.4 0.5P + 9.4 0.5P - 4.5 0.5P - 4.5 1.05 V and 1.2 V MIN MAX - 0. ...