CD74HC237

Manufacturer Part NumberCD74HC237
ManufacturerTexas Instruments
CD74HC237 datasheet
 


Specifications of CD74HC237

Voltage Nodes(v)2, 4.5, 6Vcc Range(v)2 to 6
Technology FamilyHC  
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Data sheet acquired from Harris Semiconductor
SCHS146F
March 1998 - Revised October 2003
Features
• Select One of Eight Data Outputs
- Active Low for CD74HC137 and CD74HCT137
- Active High for ’HC237 and CD74HCT237
• l/O Port or Memory Selector
• Two Enable Inputs to Simplify Cascading
• Typical Propagation Delay of 13ns at V
o
15pF, T
= 25
C (CD74HC237)
A
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
= 30%, N
IL
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), V
= 2V (Min)
IL
IH
- CMOS Input Compatibility, I
l
Description
The
CD74HC137,
CD74HCT137,
CD74HCT237 are high speed silicon gate CMOS decoders
well suited to memory address decoding or data routing
applications. Both circuits feature low power consumption
usually associated with CMOS circuitry, yet have speeds
comparable to low power Schottky TTL logic.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
©
Copyright
2003, Texas Instruments Incorporated
CD74HC137, CD74HCT137,
CD54HC237, CD74HC237,
High-Speed CMOS Logic, 3- to 8-Line
Decoder/Demultiplexer with Address Latches
Both circuits have three binary select inputs (A0, A1 and A2)
that can be latched by an active High Latch Enable (LE)
signal to isolate the outputs from select-input changes. A
“Low” LE makes the output transparent to the input and the
circuit functions as a one-of-eight decoder. Two Output
Enable inputs (OE
cascading
demultiplexing function is accomplished by using the A
A
inputs to select the desired output and using one of the
2
= 5V,
other Output Enable inputs as the data input while holding
CC
the other Output Enable input in its active state. In the
CD74HC137 and CD74HCT137 the selected output is a
“Low”; in the ’HC237 and CD74HCT237 the selected output is
a “High”.
Ordering Information
o
o
C to 125
C
PART NUMBER
CD54HC237F3A
CD74HC137E
CD74HC137PW
= 30%, of V
IH
CC
CD74HC137PWR
CD74HC137PWT
CD74HC237E
CD74HC237M
1 A at V
, V
OL
OH
CD74HC237MT
CD74HC237M96
’HC237,
and
CD74HC237NSR
CD74HC237PW
CD74HC237PWR
CD74HC237PWT
CD74HCT137E
CD74HCT137MT
CD74HCT137M96
CD74HCT237E
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
1
CD74HCT237
and OE
) are provided to simplify
1
0
and
to
facilitate
demultiplexing.
TEMP. RANGE
o
(
C)
PACKAGE
-55 to 125
16 Ld CERDIP
-55 to 125
16 Ld PDIP
-55 to 125
16 Ld TSSOP
-55 to 125
16 Ld TSSOP
-55 to 125
16 Ld TSSOP
-55 to 125
16 Ld PDIP
-55 to 125
16 Ld SOIC
-55 to 125
16 Ld SOIC
-55 to 125
16 Ld SOIC
-55 to 125
16 Ld SOP
-55 to 125
16 Ld TSSOP
-55 to 125
16 Ld TSSOP
-55 to 125
16 Ld TSSOP
-55 to 125
16 Ld PDIP
-55 to 125
16 Ld SOIC
-55 to 125
16 Ld SOIC
-55 to 125
16 Ld PDIP
The
, A
,
0
1

CD74HC237 Summary of contents

  • Page 1

    ... Port or Memory Selector • Two Enable Inputs to Simplify Cascading • Typical Propagation Delay of 13ns 15pF (CD74HC237) A • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55 • Balanced Propagation Delay and Transition Times • ...

  • Page 2

    ... CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Pinout CD54HC237 (CERDIP) CD74HC137 (PDIP, TSSOP) CD74HCT137 (PDIP, SOIC) CD74HC237 (PDIP, SOIC, SOP, TSSOP) CD74HCT237 (PDIP) TOP VIEW GND 8 9 INPUTS ...

  • Page 3

    ... CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Functional Block Diagram LATCH LATCH ...

  • Page 4

    ... CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Absolute Maximum Ratings DC Supply Voltage -0. Input Diode Current For V < -0. > 0. Output Diode Current For V < -0. > 0. Output Source or Sink Current per Output Pin, I For V > -0. < ...

  • Page 5

    ... CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 DC Electrical Specifications (Continued) CONDITIONS PARAMETER SYMBOL V (V) I Quiescent Device Current GND HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output ...

  • Page 6

    ... CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Prerequisite For Switching Specifications PARAMETER SYMBOL LE Pulse Width t W HCT TYPES Setup Time Hold Time t CD74HCT137 CD74HCT237 t LE Pulse Width t W Switching Specifications Input PARAMETER SYMBOL HC TYPES Propagation Delay t t PLH, ...

  • Page 7

    ... CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Switching Specifications Input PARAMETER SYMBOL HCT TYPES Propagation Delay An to any PLH PHL Address to Output PLH PHL OE to any Y (HC137 PLH PHL OE to any Y (HC237 PLH PHL OE to any Y (HC137) ...

  • Page 8

    ... CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Test Circuits and Waveforms 90% CLOCK INPUT 10% t H(H) DATA INPUT t SU(H) t TLH 90% OUTPUT t PLH t REM V CC SET, RESET 50% OR PRESET IC FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE ...

  • Page 9

    ... TSSOP CD74HC137PWT ACTIVE TSSOP CD74HC137PWTE4 ACTIVE TSSOP CD74HC137PWTG4 ACTIVE TSSOP CD74HC237E ACTIVE PDIP CD74HC237EE4 ACTIVE PDIP CD74HC237M ACTIVE SOIC CD74HC237M96 ACTIVE SOIC CD74HC237M96E4 ACTIVE SOIC CD74HC237M96G4 ACTIVE SOIC Pins Package Qty (2) Eco Plan Drawing Ball Finish TBD TBD J 16 ...

  • Page 10

    ... SOIC CD74HC237MT ACTIVE SOIC CD74HC237MTE4 ACTIVE SOIC CD74HC237MTG4 ACTIVE SOIC CD74HC237NSR ACTIVE SO CD74HC237NSRE4 ACTIVE SO CD74HC237NSRG4 ACTIVE SO CD74HC237PWR ACTIVE TSSOP CD74HC237PWRE4 ACTIVE TSSOP CD74HC237PWRG4 ACTIVE TSSOP CD74HC237PWT ACTIVE TSSOP CD74HC237PWTE4 ACTIVE TSSOP CD74HC237PWTG4 ACTIVE TSSOP CD74HCT137E ACTIVE PDIP CD74HCT137EE4 ACTIVE PDIP CD74HCT137M96 ...

  • Page 11

    ... TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC237, CD74HC237 : • ...

  • Page 12

    Military: CD54HC237 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Military - QML certified for Military and Defense Applications • PACKAGE OPTION ADDENDUM Addendum-Page 4 5-Sep-2011 ...

  • Page 13

    ... TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing CD74HC137PWR TSSOP PW CD74HC137PWT TSSOP PW CD74HC237M96 SOIC CD74HC237NSR SO NS CD74HC237PWR TSSOP PW CD74HC237PWT TSSOP PW CD74HCT137M96 SOIC PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel Diameter Width (mm) W1 (mm) 16 2000 330.0 12.4 16 250 330.0 12 ...

  • Page 14

    ... Device Package Type CD74HC137PWR TSSOP CD74HC137PWT TSSOP CD74HC237M96 SOIC CD74HC237NSR SO CD74HC237PWR TSSOP CD74HC237PWT TSSOP CD74HCT137M96 SOIC PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm 2000 PW 16 250 D 16 2500 NS 16 2000 PW 16 2000 PW 16 ...

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    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...