- Page 1
... TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Delfino Microcontrollers Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SPRS516C March 2009 – Revised July 2011 ... - Page 2
... TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 1 TMS320C2834x ( Delfino™) MCUs .................................................................................................................... 1.1 Overview .................................................................................................................... 1.2 Features ............................................................................................................. 1.3 Getting Started ...................................................................................................................... 2 Introduction ........................................................................................................... 2.1 Pin Assignments ........................................................................................................ 2.2 Signal Descriptions .......................................................................................................... 3 Functional Overview .............................................................................................................. 3.1 Memory Maps .......................................................................................................... 3.2 Brief Descriptions ....................................................................................................... 3.2.1 C28x CPU 3.2.2 Memory Bus (Harvard Bus Architecture) 3.2.3 Peripheral Bus 3 ... - Page 3
... External Interrupt Timing 6.13 I2C Electrical Specification and Timing 6.14 Serial Peripheral Interface (SPI) Timing 6.14.1 Master Mode Timing 6.14.2 SPI Slave Mode Timing Copyright © 2009–2011, Texas Instruments Incorporated TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 ....................................................................................... ........................................................................... ................................................................................. .................................................................. ............................................................. ............................................................................................. .............................................................................................. ............................................................. ................................................................................................. ............................................................................................. ... - Page 4
... TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 6.15 External Interface (XINTF) Timing 6.15.1 USEREADY = 0 6.15.2 Synchronous Mode (USEREADY = 1, READYMODE = 0) 6.15.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1) 6.15.4 XINTF Signal Alignment to XCLKOUT 6.15.5 External Interface Read Timing 6.15.6 External Interface Write Timing 6.15.7 External Interface Ready-on-Read Timing With One External Wait State 6 ... - Page 5
... Emulator Connection Without Signal Buffering for the MCU ......................................................................................................... 6-3 3.3-V Test Load Circuit ..................................................................................................................... 6-4 Clock Timing ................................................................................................................. 6-5 Power-on Reset Copyright © 2009–2011, Texas Instruments Incorporated TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 List of Figures ................................................................................................. ................................................................................................. ................................................................................................ ............................................................................................ ............................................................................... ............................................................................................... ............................................................................................... ................................................................................................ ............................................................................. ................................................................... ................................................... ... - Page 6
... TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 ..................................................................................................................... 6-6 Warm Reset 6-7 Example of Effect of Writing Into PLLCR Register 6-8 General-Purpose Output Timing ................................................................................................................. 6-9 Sampling Mode 6-10 General-Purpose Input Timing .................................................................................................... 6-11 IDLE Entry and Exit Timing 6-12 STANDBY Entry and Exit Timing Diagram ... - Page 7
... XCLKIN/X1 Timing Requirements – PLL Enabled 6-7 XCLKIN/X1 Timing Requirements – PLL Disabled 6-8 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) 6-9 Power Management and Supervisory Circuit Solutions Copyright © 2009–2011, Texas Instruments Incorporated TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 List of Tables .................................................................................................. .................................................................................................. .................................................................................................. .................................................................................................. ...................................................................................... ............................................................... ............................................................................................ ... - Page 8
... TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 6-10 Reset (XRS) Timing Requirements 6-11 General-Purpose Output Switching Characteristics 6-12 General-Purpose Input Timing Requirements 6-13 IDLE Mode Timing Requirements 6-14 IDLE Mode Switching Characteristics 6-15 STANDBY Mode Timing Requirements 6-16 STANDBY Mode Switching Characteristics ... - Page 9
... Thermal Model 179-Ball ZHH Results 8-2 Thermal Model 256-Ball ZFE Results Copyright © 2009–2011, Texas Instruments Incorporated TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 ....................................................................................... ....................................................................................... 165 165 List of Tables 9 ... - Page 10
... TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 10 List of Tables www.ti.com Copyright © 2009–2011, Texas Instruments Incorporated ... - Page 11
... Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Delfino Microcontrollers TMS320C28344, TMS320C28343, TMS320C28342, TMS320C28341 • Dead-Band Generation • PWM Chopping by High-Frequency Carrier • ... - Page 12
... C2000 Getting Started Website (http://www.ti.com/c2000getstarted) • TMS320F28x Development and Experimenter's Kits (http://www.ti.com/f28xkits) 12 TMS320C2834x ( Delfino™) MCUs focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ... - Page 13
... Introduction The TMS320C28346, TMS320C28345, TMS320C28344, TMS320C28343, TMS320C28342, and TMS320C28341 devices, members of the Delfino™ MCU generation, are highly integrated, high-performance solutions for demanding control applications. Throughout this document, the devices are abbreviated as C28346, C28345, C28344, C28343, C28342, and C28341, respectively. ... - Page 14
... TMX samples will come with the ZEP designator. The designator will change to ZFE after TMS. (3) Custom secure versions of these devices are available. See 14 Introduction focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 2-1. C2834x Hardware Features C28345 C28344 (200 MHz) (300 MHz) ... - Page 15
... Product status – TMS (1) See Section 5.1 for descriptions of device stages. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 2-1. C2834x Hardware Features (continued) C28345 C28344 (200 MHz) (300 MHz) ZFE ZHH ZFE ZFE ZFE – ... - Page 16
... DDIO SS GPIO12/ TZ1 / CANTXB/ MDXB 1 2 Figure 2-1. C2834x 179-Ball ZHH MicroStar BGA™ Upper Left Quadrant (Bottom VIew) 16 Introduction focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 GPIO19/ GPIO23/ GPIO24/ SPISTEA / EQEP1I/ ECAP1/ SCIRXDB/ MFSXA/ EQEP2A/ CANTXA SCIRXDB MDXB ... - Page 17
... L EMU1 DDIO 8 Figure 2-2. C2834x 179-Ball ZHH MicroStar BGA™ Upper Right Quadrant (Bottom View) Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 GPIO49/ ECAP6/ SPISIMOA/ V TCK ... - Page 18
... GPIO31/ GPIO0/ B CANTXA/ EPWM1A XA17 GPIO39/ A XA16 1 2 Figure 2-3. C2834x 179-Ball ZHH MicroStar BGA™ Lower Left Quadrant (Bottom View) 18 Introduction focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 GPIO8/ GPIO10/ EPWM5A/ EPWM6A CANRXB/ CANTXB/ ADCSOCBO ADCSOCAO GPIO6/ EPWM4A/ ... - Page 19
... V B SSK GPIO44 Figure 2-4. C2834x 179-Ball ZHH MicroStar BGA™ Lower Right Quadrant (Bottom View) Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 GPIO78/ ... - Page 20
... MFSXB GPIO13/ TZ2 / TZ3 XHOLD V J DDIO CANRXB/ SCITXDB/ MDRB Figure 2-5. C2834x 256-Ball ZFE Plastic BGA Upper Left Quadrant (Bottom View) 20 Introduction focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 GPIO19/ GPIO21/ GPIO24/ SPISTEA / EQEP1B/ ECAP1/ V DDIO SCIRXDB/ MDRA/ ... - Page 21
... Figure 2-6. C2834x 256-Ball ZFE Plastic BGA Upper Right Quadrant (Bottom View) Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 GPIO50/ GPIO53/ EQEP1A/ V TCK ... - Page 22
... C CANRXA XA18 GPIO31/ B CANTXA Figure 2-7. C2834x 256-Ball ZFE Plastic BGA Lower Left Quadrant (Bottom View) 22 Introduction focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TZ1 / MDXB GPIO6 DDIO DDIO ... - Page 23
... DDIO XA3 Figure 2-8. C2834x 256-Ball ZFE Plastic BGA Lower Right Quadrant (Bottom View) Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 GPIO72 XD7 ... - Page 24
... Internal Oscillator Output. A quartz crystal may be connected across X1 and X2 not used it X2 must be left unconnected. (O) 24 Introduction focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 for details. Inputs are not 5-V tolerant. All XINTF pins have a drive strength Table 2-2. Signal Descriptions DESCRIPTION JTAG Clock ... - Page 25
... MCLKRA McBSP-A receive clock (I/O) ECAP2 Enhanced capture input/output 2 (I/O) Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 DESCRIPTION Reset External ADC Interface Signals ... - Page 26
... GPIO19 General purpose input/output 19 (I/O/Z) SPISTEA SPI-A slave transmit enable input/output (I/ SCIRXDB SCI-B receive (I) CANTXA Enhanced CAN-A transmit (O) 26 Introduction focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 DESCRIPTION Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ... - Page 27
... SCI-A receive data (I) XZCS0 External Interface zone 0 chip select (O) Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 DESCRIPTION Submit Documentation Feedback ... - Page 28
... General-Purpose Input/Output 54 (I/O/Z) SPISIMOA SPI-A slave in, master out (I/O) P12 R13 XD25 External Interface Data Line 25 (O) EQEP3A Enhanced QEP3 input A (I) 28 Introduction focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 DESCRIPTION Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ... - Page 29
... H15 - XD8 External Interface Data Line 8 (O) Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 DESCRIPTION Submit Documentation Feedback Introduction ... - Page 30
... External Memory Interface Write Enable for Upper 16-bits (O). The XWE1 pin is high-impedance on XWE1 C13 E14 reset. It stays that way as long as the XINTF clock is turned off (which happens on reset). 30 Introduction focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 DESCRIPTION Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ... - Page 31
... D12 DDIO V L14 E4 DDIO Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 DESCRIPTION CPU and I/O Power Pins Figure 3-12 for proper application board connections. Submit Documentation Feedback SPRS516C – MARCH 2009 – REVISED JULY 2011 ... - Page 32
... D13 D13 SS V B11 D14 E12 F10 SS 32 Introduction focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 DESCRIPTION Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ... - Page 33
... N10 SS V N13 SS Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 DESCRIPTION Submit Documentation Feedback Introduction 33 ... - Page 34
... SS V P14 Digital ground pins V R15 SS V R16 T15 SS V T16 SS 34 Introduction focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 DESCRIPTION Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ... - Page 35
... FIFO (16 Levels) (16 Levels) (16 Levels) SCI-A/B/C SPI-A/D I2C Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 (0-Wait) H0 SARAM 32K Wait, Prefetch) (0-Wait) H1 SARAM 32K Wait, Prefetch) (0-Wait) ... - Page 36
... If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for this. 36 Functional Overview focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 3-4, the following apply: Submit Documentation Feedback www.ti.com Copyright © 2009–2011, Texas Instruments Incorporated ... - Page 37
... A. These locations support compatibility with legacy C28x designs only. See Figure 3-2. C28346/C28345 Memory Map Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 External Memory XINTF Prog Space Data Space ... - Page 38
... Only one of these vector maps-M0 vector, PIE vector, BROM vector-should be enabled at a time. A. These locations support compatibility with legacy C28x designs only. See Figure 3-3. C28344/C28343 Memory Map 38 Functional Overview focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 External Memory XINTF Prog Space Data Space Reserved XINTF Zone 0 (4K x 16, Reserved ... - Page 39
... These locations support compatibility with legacy C28x designs only. See Figure 3-4. C28342, C28341 Memory Map Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 External Memory XINTF Prog Space ... - Page 40
... H1 SARAM H2 SARAM H3 SARAM H4 SARAM H5 SARAM Boot-ROM 1-wait (1) The DMA has a base of 4 cycles/word. 40 Functional Overview focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 3-1. Wait-states WAIT-STATES (1) (DMA) No access Fixed No access (writes) 0-wait (reads) 0-wait (writes) Assumes no conflicts between CPU and DMA. ... - Page 41
... The third version supports DMA access and both 16- and 32-bit accesses (called peripheral frame 3). Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 without ... - Page 42
... All SARAM blocks are mapped to both program and data space. L0–L7 are accessible by both the CPU and the DMA (1 wait state). 42 Functional Overview focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 8K × 16. These 8K × 16 SARAM blocks are single-wait state at all frequencies. frequencies. A program-access prefetch buffer is used to improve performance of linear code. Copyright © ... - Page 43
... Contact TI at support@ti.com for more details. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 3-2. Boot Mode Selection GPIO85/XA13 ... - Page 44
... Turns off the internal oscillator. This mode basically shuts down the device and places it in the lowest possible power consumption mode. A reset or external signal can wake the device from this mode. 44 Functional Overview focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ... - Page 45
... INT13 of the CPU. CPU-Timer 0 is also for general use and is connected to the PIE block. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 ... - Page 46
... MCU through the I2C module. The I2C contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead. 46 Functional Overview focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ... - Page 47
... GPIO registers Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 See Table 3-3. See Table 3-4. See Table 3-5 ... - Page 48
... PROTSTART 0x0884 PROTRANGE 0x0885 48 Functional Overview focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 3-5. Peripheral Frame 2 Registers ADDRESS RANGE 0x00 7010 – 0x00 702F 0x00 7040 – 0x00 704F 0x00 7050 – 0x00 705F 0x00 7070 – 0x00 707F 0x00 7750 – 0x00 775F 0x00 7770 – ... - Page 49
... NMI 1 DMA A. DMA-accessible Figure 3-5. External and PIE Interrupt Sources Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Peripherals (SPI, SCI, I2C, CAN, McBSP Clear EPWM, ECAP, EQEP WDINT ... - Page 50
... PIE group. For example: TRAP #1 fetches the vector from INT1.1, TRAP #2 fetches the vector from INT2.1, and so forth. 50 Functional Overview focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 DMA Interrupt Control Latch XINT3CR(15:0) GPIOXINT3SEL(4:0) ... - Page 51
... PIEIFR. To summarize, there is one sage case when the reserved interrupts could be used as software interrupts peripheral within the group is asserting interrupts. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 IFR(12:1) ... - Page 52
... Reserved 0x0CFA – 0x0CFF (1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected. 52 Functional Overview focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SIZE (x16) DESCRIPTION 1 PIE, Control Register 1 PIE, Acknowledge Register 1 PIE, INT1 Group Enable Register ... - Page 53
... For more information, see the TMS320x2834x Delfino System Control and Interrupts Reference Guide (literature number SPRUFN1). Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 3-10. External Interrupt Registers ... - Page 54
... There is a 2-SYSCLKOUT cycle delay from when the write to PCLKCR0/1/2 registers (enables peripheral clocks) occurs to when the action is valid. This delay must be taken into account before attempting to access the peripheral configuration registers. 54 Functional Overview focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 System Clock enables control register LSPCLK ... - Page 55
... A 1.8-V external oscillator can be directly connected to the X1 pin. The X2 pin should be left unconnected and the XCLKIN pin tied DD18 Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SIZE (x16) 1 PLL Status Register 7 ... - Page 56
... SPRS516C – MARCH 2009 – REVISED JULY 2011 The three possible input-clock configurations are shown in Figure 3-10. Using a 3.3-V External Oscillator Figure 3-11. Using a 1.8-V External Oscillator X1 XCLKIN C1 Figure 3-12. Using the Internal Oscillator 56 Functional Overview focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Figure 3-10 XCLKIN SSK NC External Clock Signal (Toggling ... - Page 57
... Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 ... - Page 58
... External clock source operation - This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external clock source input on the X1 or the XCLKIN pin. 58 Functional Overview focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 (1) Table 3-12. PLL Settings PLLSTS[DIVSEL PLLSTS[DIVSEL ... - Page 59
... XRS pin of the MCU, should the capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent it from getting fully charged. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 REMARKS Submit Documentation Feedback SPRS516C – ... - Page 60
... In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is the WATCHDOG. 60 Functional Overview focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 shows the various functional blocks within the watchdog module. WDCR (WDDIS) WDCLK Watchdog ... - Page 61
... IDLE instruction was executed. See the TMS320x2834x Delfino System Control and Interrupts Reference Guide (literature number SPRUFN1) for more details. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 3-15. Low-Power Modes OSCCLK ... - Page 62
... McBSP-A and McBSP-B transmit and receive buffers • Word Size: 16-bit or 32-bit (McBSPs limited to 16-bit) • Throughput: 4 cycles/word (5 cycles/word for McBSP reads) 62 Peripherals focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ... - Page 63
... I RAM I/F Figure 4-1. DMA Functional Block Diagram Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 CPU bus External interrupts McBSP A ... - Page 64
... The timer registers are connected to the memory bus of the C28x processor. B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock. Figure 4-3. CPU-Timer Interrupt Signals and Output Signal 64 Peripherals focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 NOTE 16-Bit Timer Divide-Down TDDRH:TDDR 16-Bit Prescale Counter PSCH:PSC Borrow Figure 4-2 ... - Page 65
... TIMER2TPRH 0x0C17 Reserved 0x0C18 – 0x0C3F Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 are used to configure the timers. For more information, see the SIZE (x16) 1 CPU-Timer 0, Counter Register ... - Page 66
... Figure 4-4. Generation of SOC Pulses to the External ADC Module 66 Peripherals focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Figure 4-4 shows the signal interconnections with the ePWM. EXTSOC1A POLSEL 0 1 EXTSOC1B POLSEL 0 1 EXTSOC2A POLSEL ... - Page 67
... PCCTL 0x681E 0x685E HRCNFG 0x6820 0x6860 (1) Registers that are EALLOW protected. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 4-2. ePWM1-4 Control and Status Registers SIZE (x16) / ePWM3 ePWM4 #SHADOW 0x6880 0x68C0 Time Base Control Register ... - Page 68
... ETFRC 0x691D 0x695D PCCTL 0x691E 0x695E HRCNFG 0x6920 0x6960 (1) Registers that are EALLOW protected. 68 Peripherals focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 4-3. ePWM5-9 Control and Status Registers SIZE (x16) / ePWM7 ePWM8 ePWM9 #SHADOW 0x6980 0x69C0 0x6600 0x6981 0x69C1 0x6601 ... - Page 69
... CMPA active (24) CMPA shadow (24) 16 CMPB active (16) CMPB shadow (16) Figure 4-5. ePWM Submodules Showing Critical Internal Signal Interconnections Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Sync CTR=ZERO in/out select CTR=CMPB Mux Disabled CTR=PRD TBCTL[SYNCOSEL] ... - Page 70
... HRPWM capabilities are offered only on the A signal path of an ePWM module (i.e., on the EPWMxA output). EPWMxB output has conventional PWM capabilities. 70 Peripherals focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ... - Page 71
... CTR_OVF Flag CTR=PRD Control CTR=CMP Figure 4-6. eCAP Functional Block Diagram Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 APWM Mode CTR_OVF OVF CTR [0-31] Delta Mode PRD [0-31] RST ... - Page 72
... ECCLR 0x6A18 0x6A38 0x6A58 ECFRC 0x6A19 0x6A39 0x6A59 Reserved 0x6A1A- 0x6A3A- 0x6A5A- 0x6A1F 0x6A3F 0x6A5F 72 Peripherals focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 low power operation). Upon reset, eCAP4 eCAP5 eCAP6 0x6A60 0x6A80 0x6AA0 0x6A62 0x6A82 0x6AA2 0x6A64 0x6A84 0x6AA4 ... - Page 73
... QPOSILAT 32 QPOSCNT QPOSCMP QPOSINIT QPOSMAX Enhanced QEP (eQEP) Peripheral Figure 4-7. eQEP Functional Block Diagram Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 To CPU QCPRD QCTMR 16 Capture Unit (QCAP) ... - Page 74
... The external ADC interface operation is configured, controlled, and monitored by the External SoC Configuration Register (EXTSOCCFG) Start-of-Conversion signals for external ADCs are generated by the on-chip PWM modules. 74 Peripherals focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 eQEPx eQEP2 eQEP3 SIZE(x16)/ ADDRESS #SHADOW 0x6B40 ... - Page 75
... Table 4-6. External ADC Interface Registers NAME EXTSOCCFG Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 EXTSOC1A POLSEL 0 1 EXTSOC1B POLSEL 0 1 EXTSOC2A ... - Page 76
... Internal prescalers must be adjusted such that the peripheral speed is less than the I/O buffer speed limit. See Section 6 for maximum I/O pin toggling speed. 76 Peripherals focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 CLKSRG CLKG = ( ) 1 + CLKGDV NOTE Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback www ... - Page 77
... McBSP Receive Interrupt Select Logic RX Interrupt Logic MRINT To CPU Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 TX Interrupt Peripheral Write Bus ... - Page 78
... XCERH 0x501E 0x505E MFFINT 0x5023 0x5063 MFFST 0x5024 0x5064 78 Peripherals focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 4-7. McBSP Register Summary TYPE RESET VALUE Data Registers, Receive, Transmit R 0x0000 McBSP Data Receive Register 2 R 0x0000 McBSP Data Receive Register 1 W 0x0000 ... - Page 79
... The CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and exceptions. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 ... - Page 80
... Message Controller Mailbox RAM (512 Bytes) 32-Message Mailbox 32-Bit Words eCAN Protocol Kernel Figure 4-10. eCAN Block Diagram and Interface Circuit 80 Peripherals focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Controls Address Data 32 Memory Management Unit CPU Interface, Receive Control Unit ... - Page 81
... V SN65HVD233 3.3 V SN65HVD234 3.3 V Standby and Sleep SN65HVD235 3.3 V ISO1050 3–5.5 V Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 4-8. 3.3-V eCAN Transceivers SLOPE VREF MODE CONTROL Standby Adjustable Yes Sleep Adjustable ... - Page 82
... RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for this. 82 Peripherals focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 eCAN-A Control and Status Registers Transmission Request Set - CANTRS Transmission Request Reset - CANTRR Transmission Acknowledge - CANTA Received Message Pending - CANRMP ... - Page 83
... Mailbox 30 63F8h-63FFh Mailbox 31 Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 eCAN-B Control and Status Registers Transmission Request Set - CANTRS Transmission Request Reset - CANTRR Transmission Acknowledge - CANTA ... - Page 84
... CANTOC 0x6030 CANTOS 0x6032 (1) These registers are mapped to Peripheral Frame 1. 84 Peripherals focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 4-9 are used by the CPU to configure and control the CAN controller Table 4-9. CAN Register Map eCAN-B SIZE ADDRESS (x32) 0x6200 ... - Page 85
... When a register is accessed, the register data is in the lower byte (7-0), and the upper byte (15-8) is read as zeros. Writing to the upper byte has no effect. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 LSPCLK ... - Page 86
... Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. (2) These registers are new registers for the FIFO mode. 86 Peripherals focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 (1) Table 4-10. SCI-A Registers SIZE (x16) 1 SCI-A Communications Control Register ... - Page 87
... Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. (2) These registers are new registers for the FIFO mode. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 (1) (2) Table 4-12. SCI-C Registers ... - Page 88
... Buffer Register RX FIFO Registers SCIRXST.7 SCIRXST Error Error RX ERR INT ENA Figure 4-13. Serial Communications Interface (SCI) Module Block Diagram 88 Peripherals focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SCICTL1.1 TXSHF Register TXENA TX EMPTY SCICTL2.6 8 TXRDY Transmitter-Data SCICTL2.7 Buffer Register 8 ... - Page 89
... When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 LSPCLK ... - Page 90
... SPIPRI 0x778F (1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. 90 Peripherals focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 4-13. SPI-A Registers SIZE (x16) DESCRIPTION 1 SPI-A Configuration Control Register 1 SPI-A Operation Control Register ... - Page 91
... A. SPISTE is driven low by the master for a slave device. Figure 4-14. SPI Module Block Diagram (Slave Mode) Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Overrun Receiver INT ENA Overrun Flag SPISTS ... - Page 92
... Data transfer rate from 10 kbps up to 400 kbps (I2C Fast-mode rate) • One 16-word receive FIFO and one 16-word transmit FIFO 92 Peripherals focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Figure 4-15 shows how the I2C peripheral module interfaces System Control Block I2CAENCLK SYSCLKOUT ... - Page 93
... There is a 2-SYSCLKOUT cycle delay from when the write to the GPxMUXn and GPxQSELn registers occurs to when the action is valid. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 4-15. I2C-A Registers ... - Page 94
... This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the TMS320x2834x Delfino System Control and Interrupts Reference Guide (literature number for pin-specific variations. 94 Peripherals focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 GPIOLMPSEL LPMCR0 Low-Power Modes Block GPxQSEL1/2 ... - Page 95
... GPIOXINT3SEL 0x6FE3 GPIOXINT4SEL 0x6FE4 GPIOXINT5SEL 0x6FE5 Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 4-16. GPIO Registers SIZE (x16) 2 GPIO A Control Register (GPIO0 to 31) 2 GPIO A Qualifier Select 1 Register (GPIO0 to 15) ... - Page 96
... Peripherals focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 4-16. GPIO Registers (continued) SIZE (x16) 1 XINT6 GPIO Input Select Register (GPIO32 to 63) 1 XINT7 GPIO Input Select Register (GPIO32 to 63) 2 LPM GPIO Select Register (GPIO0 to 31) 22 ... - Page 97
... Open drain Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 PERIPHERAL SELECTION GPIOx PER1 GPBMUX1 = 0, 0 GPBMUX1 = 0, 1 (1) GPIO32 (I/O) SDAA (I/OC) (1) GPIO33 (I/O) ... - Page 98
... Peripherals focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 PERIPHERAL SELECTION GPIOx or PER1 GPCMUX1 = GPIO64 (I/O) GPIO65 (I/O) GPIO66 (I/O) GPIO67 (I/O) GPIO68 (I/O) GPIO69 (I/O) GPIO70 (I/O) GPIO71 (I/O) GPIO72 (I/O) GPIO73 (I/O) GPIO74 (I/O) GPIO75 (I/O) GPIO76 (I/O) GPIO77 (I/O) ... - Page 99
... GPIO pin. Also, when an input signal is not selected, the input signal will default to either state, depending on the peripheral. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Time Between Samples ... - Page 100
... XA0 and XWE1 signals change, depending on the configuration. XINTF configuration and control registers. 16-bits A(19:0) D(15:0) Figure 4-19. Typical 16-bit Data Bus XINTF Connections 100 Peripherals focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 4-18. Prog Space XINTF Zone 0 (8K x 16) XINTF Zone 6 (1M x 16) XINTF Zone 7 (1M x 16) ... - Page 101
... XTIMING1 - XTIMING5 are reserved for future expansion and are not currently used. (2) XINTCNF1 is reserved and not currently used. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 External wait-state ... - Page 102
... TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. 102 Device Support focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ... - Page 103
... TMS320 Device Family TECHNOLOGY C = Non-Flash (1.1/1.2-V Core/3.3-V I/O) Figure 5-1. Example of C2834x Device Nomenclature Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 C 28346 ZFE ... - Page 104
... SPRUFN4 TMS320x2834x Delfino External Interface (XINTF) Reference Guide. This document describes the XINTF, which is a nonmultiplexed asynchronous bus used on the x2834x device. 104 Device Support focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 LITERATURE NUMBER SPRUFN1 SPRUFN4 SPRUEU4 SPRUG80 SPRUG75 ... - Page 105
... TMS320 DSP assembly language source code for the TMS320C28x device. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 ... - Page 106
... TMS320x2833x/2823x to TMS320x2834x Delfino Migration Overview. This application report describes differences between the Texas Instruments TMS320x2833x/2823x and the TMS320x2834x devices to assist in application migration. 106 Device Support focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www.ti.com/c2000getstarted www.ti.com/c2000appsw www.ti.com/dpslib www.ti.com/dsppower overview ... - Page 107
... Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 http://www.ti.com/sc/docs/pic/home.htm Texas Instruments Embedded Processors Wiki. Established to help Submit Documentation Feedback SPRS516C – ... - Page 108
... For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for TMS320LF24xx and TMS320F28xx Devices Application Report (literature number SPRA963). 108 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 (1) (2) with respect with respect to V ... - Page 109
... Output current, pullup pulldown disabled C Input capacitance I Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 300-MHz devices 200-MHz devices C28346/C28344/C28342 (V = 1.2 V ± 5%) DD C28345/C28343/C28341 (V = 1.1 V ± 5 ... - Page 110
... Peripheral clocks are off. HALT (4) Input clock is disabled. (1) The I numbers in this table are valid for the TMS320C28346 and TMS320C28344 devices only. For the TMS320C28342 device, DD subtract the I current numbers for those peripherals that do not exist on this device (see DD shown in this table. ... - Page 111
... For the TMS320C28341 device, subtract the I that do not exist on this device (see Table 6-2. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 (1) Current Consumption by Power-Supply Pins at 200-MHz SYSCLKOUT ... - Page 112
... Figure 6-1. Temperature Versus Leakage Current (Typical) 112 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 6-3 indicates the typical reduction in current consumption current consumption (typical). DDIO NOTE Temperature (°C) Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback www ... - Page 113
... Whether 16-bit or 32-bit interface is used and • The load on these pins. • Whether internal pullups are enabled on the XINTF pins. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 (1) Peripherals PERIPHERAL I ... - Page 114
... TDO TCK MCU Figure 6-2. Emulator Connection Without Signal Buffering for the MCU 114 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 ) varies with the end application and product A J within the specified limits normally measured at the center of ... - Page 115
... The transmission line is intended as a load only not necessary to add or subtract the transmission line delay ( longer) from the data sheet timing. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Letters and symbols and their ... - Page 116
... This frequency is limited by GPIO switching characteristics. (4) Lower LSPCLK and HSPCLK will reduce device power consumption. (5) This is the value if SYSCLKOUT = 300 MHz. 116 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 6-5 list the cycle times of various clocks Cycle time c(OSC) ... - Page 117
... Lower LSPCLK and HSPCLK will reduce device power consumption. (5) This is the value if SYSCLKOUT = 200 MHz. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 ... - Page 118
... The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is intended to illustrate the timing parameters only and may differ based on actual configuration. B. XCLKOUT configured to reflect SYSCLKOUT. 118 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 (1) c(OSCCLK) (1) c(OSCCLK) (1) c(OSCCLK) ... - Page 119
... Voltages applied to pins on an unpowered device can bias internal P-N junctions in unintended ways and produce unpredictable results. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 ... - Page 120
... SVS Texas Instruments SVS 120 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 PART TPS650061 3-channel power management IC with one DC/DC switcher, two low-dropout (LDO) regulators (fixed at 3.3 V and 1.8 V), a spread spectrum clock (SSC), and a supervisory circuit solution (SVS) TPS65001 ... - Page 121
... PLL enabled. C. See Section 6.9 for requirements to ensure a high-impedance state for GPIO pins during power-up. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 (A) OSCCLK/64 t w(RSL1) ... - Page 122
... Boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled. 122 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 64t c(OSCCLK) Warm reset 64t c(OSCCLK) ... - Page 123
... Toggling frequency, GPO pins fGPO GPIO Figure 6-8. General-Purpose Output Timing Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Write to PLLCR OSCCLK/2 (CPU Frequency While PLL is Stabilizing With the Desired Frequency . This Period ... - Page 124
... Pulse duration, GPIO low/high w(GPI) (1) "n" represents the number of qualification samples as defined by GPxQSELn register. (2) For t , pulse width is measured from V w(GPI) 124 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 ( Sampling Period determined ... - Page 125
... Sampling window width = (SYSCLKOUT cycle QUALPRD = 0 XCLKOUT GPIOxn Figure 6-10. General-Purpose Input Timing Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 t w(GPI) ... - Page 126
... Address/Data (internal) XCLKOUT (A) WAKE INT A. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS. 126 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 6-14 shows the switching characteristics, and Without input qualifier With input qualifier Table 6-12. TEST CONDITIONS MIN (2) ... - Page 127
... Normal execution resumes. The device will respond to the interrupt (if enabled). Figure 6-12. STANDBY Entry and Exit Timing Diagram Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TEST CONDITIONS Without input qualification ... - Page 128
... Clocks to the core and peripherals are enabled. The HALT mode is now exited. The device will respond to the interrupt (if enabled), after a latency. H. Normal operation resumes. Figure 6-13. HALT Wake-Up Using GPIOn 128 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 t . MIN 32t c(SCO) (C) (E) ... - Page 129
... Pulse duration, TZx input low w(TZ) (1) For an explanation of the input qualifier parameters, see Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 6-19 shows the PWM timing requirements and TEST CONDITIONS ... - Page 130
... PARAMETER t Delay time, external clock to counter increment d(CNTR)xin t Delay time, QEP input edge to position compare sync d(PCS-OUT)QEP output 130 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 6-24 shows the eCAP switching characteristics. TEST CONDITIONS Asynchronous ... - Page 131
... Delay time, INT low/high to interrupt-vector fetch d(INT) (1) For an explanation of the input qualifier parameters, see Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 t w(ADCSOCL) Figure 6-16. External Interrupt Timing TEST CONDITIONS ... - Page 132
... Figure 6-17 and 132 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 6-30. I2C Timing TEST CONDITIONS I2C clock module frequency is between 7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately ... - Page 133
... Slave mode transmit 20-MHz MAX, slave mode receive 20-MHz MAX. (5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6). Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 (1) (2) (3) (4) (5) ... - Page 134
... SPISTE will go inactive 1 t that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes. Figure 6-17. SPI Master Mode External Timing (Clock Phase = 0) 134 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 ... - Page 135
... The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPI WHEN (SPIBRR + 1) IS EVEN OR SPI WHEN (SPIBRR + 1) IS ODD ... - Page 136
... SPISTE will go inactive 1 t that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes. Figure 6-18. SPI Master Mode External Timing (Clock Phase = 1) 136 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Master Out Data Is Valid 10 ... - Page 137
... The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 show the timing waveforms. Submit Documentation Feedback SPRS516C – ... - Page 138
... In the slave mode, the SPISTE signal should be asserted low at least 1 t edge and remain low for at least 1 t Figure 6-19. SPI Slave Mode External Timing (Clock Phase = 0) 138 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPISOMI Data Is Valid ... - Page 139
... Figure 6-20. SPI Slave Mode External Timing (Clock Phase = 1) Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 0.5t ... - Page 140
... Based on 300-MHz system clock speed. (3) If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers. 140 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 DURATION (ns) X2TIMING = 0 XRDLEAD × t c(XTIM) (XRDACTIVE + × t c(XTIM) XRDTRAIL × ... - Page 141
... Based on 300-MHz system clock speed (3) If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 c(XTIM) ... - Page 142
... Based on 300-MHz system clock speed (3) If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers. 142 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 LR ≥ 2 × t c(XTIM) LW ≥ 3 × t c(XTIM) AR ≥ 6 × t c(XTIM) AW ≥ ... - Page 143
... SYSCLKOUT C28x /2 CPU XINTCNF2 (XTIMCLK) Figure 6-21. Relationship Between XTIMCLK and SYSCLKOUT Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 XTIMCLK SYSCLKOUT 300 MHz 300 MHz SYSCLKOUT 300 MHz ... - Page 144
... XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will be with respect to the falling edge of XCLKOUT. Examples: 144 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 XZCSL Zone chip-select active low XRNWL XR/W active low XRDL XRD active low ... - Page 145
... During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – ... - Page 146
... XTIMING register parameters used for this example (based on 300-MHz system clock): XRDLEAD XRDACTIVE XRDTRAIL ≥ 2 ≥ 5 ≥ 0 (1) N/A = Not applicable (or “Don’t care”) for this example 146 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Active Lead t d(XCOHL-XRDL) t a(A) t a(XRD) Figure 6-22. Example Read Access USEREADY ... - Page 147
... This includes alignment cycles. ( Trail period, write access. See Table Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 6-35. Submit Documentation Feedback SPRS516C – MARCH 2009 – REVISED JULY 2011 ... - Page 148
... XTIMING register parameters used for this example (based on 300-MHz system clock): XRDLEAD XRDACTIVE XRDTRAIL (1) (1) (1) N/A N/A N/A (1) N/A = Not applicable (or “Don’t care”) for this example 148 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Active Lead t d(XCOHL-XWEL) t d(XWEL-XD) t en(XD)XWEL DOUT Figure 6-23. Example Write Access USEREADY X2TIMING XWRLEAD ... - Page 149
... Setup time, XREADY (asynchronous) high before XCLKOUT high/low su(XRDYAsynchH)XCOHL t Hold time, XREADY (asynchronous) held high after zone chip select high h(XRDYasynchH)XZCSH Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Table 6-35. Figure 6-24: − ... - Page 150
... XTIMING register parameters used for this example (based on 300-MHz system clock): XRDLEAD XRDACTIVE XRDTRAIL ≥ ≥ 0 (1) N/A = “Don’t care” for this example 150 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Active Lead t d(XCOHL-XRDL) t su(XD)XRD t a(XRD) t a(A) ... - Page 151
... XRDLEAD XRDACTIVE XRDTRAIL ≥ ≥ 0 (1) N/A = “Don’t care” for this example Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 WS (Async) Active Lead d(XCOH-XZCSL) d(XCOH-XA) t d(XCOHL-XRDL) ... - Page 152
... XREADY (asynchronous) is low sampled again each t For each sample, setup time from the beginning of the access can be calculated as (XWRLEAD + XWRACTIVE – where n is the sample number and so forth. 152 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 (1) (1) (1) 6-35) Figure 6-26: – ... - Page 153
... XTIMING register parameters used for this example (based on 300-MHz system clock): XRDLEAD XRDACTIVE XRDTRAIL (1) (1) (1) N/A N/A N/A (1) N/A = "Don't care" for this example. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 WS (Synch) Active Lead 1 d(XCOH-XZCSL) d(XCOH-XA) t d(XCOHL-XWEL) t d(XCOH-XRNWL) t ... - Page 154
... XTIMING register parameters used for this example (based on 300-MHz system clock): XRDLEAD XRDACTIVE XRDTRAIL (1) (1) (1) N/A N/A N/A (1) N/A = “Don’t care” for this example 154 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 WS (Async) Active Lead 1 d(XCOH-XZCSL) d(XCOH-XA) t d(XCOHL-XWEL) t d(XWEL- en(XD)XWEL t ... - Page 155
... Thus, for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur XTIMCLK cycle earlier than the maximum value specified. Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 ... - Page 156
... XZCS0 XZCS6 XZCS7 , , XA[19:0] Valid XD[31:0], XD[15:0] A. All pending XINTF accesses are completed. B. Normal XINTF operation resumes. Figure 6-28. External Interface Hold Waveform 156 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 t d(HL-HAL) High-Impedance High-Impedance Valid (A) Submit Documentation Feedback www.ti.com t d(HH-HAH) t d(HH-BV) Valid (B) Copyright © ... - Page 157
... Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer speed limit (40 MHz). Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 ... - Page 158
... C = CLKRX low pulse width = CLKRX high pulse width = P 158 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 PARAMETER CLKR/X int CLKR/X int CLKR/X int CLKR int CLKR ext CLKX int ... - Page 159
... CLKX FSX (int) FSX (ext) DX (XDATDLY=00b) DX (XDATDLY=01b) DX (XDATDLY=10b) Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 M1, M11 M2, M12 M3, M12 M4 M16 M18 Bit (n−1) (n−2) M17 Bit (n−1) M17 Figure 6-29 ... - Page 160
... LSPCLK/16 , that is 9.375 MHz and P = 6.67 ns. LSB CLKX M24 FSX M28 DX Bit 0 DR Bit 0 Figure 6-31. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 160 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 MASTER MIN 30 2P MASTER MIN ( – M32 ... - Page 161
... DR Bit 0 Figure 6-32. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 MASTER MIN ... - Page 162
... LSPCLK/16; that is, 9.375 MHz and P = 6.67 ns. LSB CLKX M43 FSX M47 DX Bit 0 DR Bit 0 Figure 6-33. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 162 Electrical Specifications focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 MASTER MIN 30 (1) 2P MASTER MIN 2P M51 MSB M44 M48 M45 ... - Page 163
... DR Bit 0 Figure 6-34. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 MASTER MIN ... - Page 164
... Section 6.11.3 Added "High-Resolution PWM Timing" section title 164 Revision History focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 ADDITIONS, DELETIONS, AND MODIFICATIONS Section 5.3. illustrates how the Start-of-Conversion signals for external ADCs are generated by the Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback www ... - Page 165
... JT Ψ JB θ JC θ JB Copyright © 2009–2011, Texas Instruments Incorporated focus.ti.com: TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516C – MARCH 2009 – REVISED JULY 2011 AIR FLOW 0 lfm 150 lfm 250 lfm 40.8 32.4 31.0 ... - Page 166
... PACKAGING INFORMATION Orderable Device (1) Package Type Package Status TMS320C28341ZFEQ ACTIVE BGA TMS320C28341ZFET ACTIVE BGA TMS320C28341ZHHT ACTIVE BGA MICROSTAR TMS320C28342ZFEQ ACTIVE BGA TMS320C28342ZFET ACTIVE BGA TMS320C28343ZFEQ ACTIVE BGA TMS320C28343ZFET ACTIVE BGA TMS320C28343ZHHT ACTIVE BGA MICROSTAR TMS320C28344ZFEQ ACTIVE BGA TMS320C28344ZFET ACTIVE BGA ... - Page 167
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part ... - Page 168
... - Page 169
... - Page 170
... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...
|
TMS320C206PZ
TMS320C28346
TMS320C2802
TMS320C2801