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TMS320C28341
TMS320C28341 | |
|---|---|
| Manufacturer Part Number | TMS320C28341 |
| Description | The TMS320C2834x (C2834x) Delfino™ microcontroller (MCU) devices build on TI's existing F2833x high-performance floating-point microcontrollers |
| Manufacturer | Texas Instruments |
| TMS320C28341 datasheets |
|
Availability: In stock
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Warranty: 60 days
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Specifications of TMS320C28341 | |||
|---|---|---|---|
| Cpu | C28x | Peak Mmacs | 200 |
| Fpu | Yes | Frequency(mhz) | 200 |
| Ram(kb) | 196 | Emif | 1 32/16-Bit |
| Dma(ch) | 1 6-Ch DMA | Pwm(ch) | 12 |
| Cap/qep | 4/2 | Mcbsp | 1 |
| I2c | 1 | Uart(sci) | 3 |
| Spi | 2 | Can | 2 |
| Timers | 3 32-Bit CPU,1 WD | Gpio | 88 |
| Pin/package | 179BGA MICROSTAR, 256BGA | Operating Temperature Range(c) | -40 to 105,-40 to 125 |
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(A) (B)
(D)
XCLKOUT = XTIMCLK
t
XZCS0 XZCS6 XZCS7
,
,
t
XA[0:19]
XRD
(E)
XWE0 XWE1
,
XR/W
XD[0:31], XD[0:15]
XREADY(Asynch)
Legend:
= Don’t care. Signal can be high or low during this time.
A.
All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
B.
During alignment cycles, all signals will transition to their inactive state.
C.
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
D.
Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E.
XWE1 is valid only in 32-bit data bus mode.
F.
For
each
sample,
setup
E = (XRDLEAD + XRDACTIVE -3 +n) t
so forth.
G.
Reference for the first sample is with respect to this point: F = (XRDLEAD + XRDACTIVE –2) t
Figure 6-25. Example Read With Asynchronous XREADY Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
XRDLEAD
XRDACTIVE
XRDTRAIL
≥ 2
5
≥ 0
(1) N/A = “Don’t care” for this example
Copyright © 2009–2011, Texas Instruments Incorporated
focus.ti.com:
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
WS (Async)
Active
Lead
d(XCOH-XZCSL)
d(XCOH-XA)
t
d(XCOHL-XRDL)
t
su(XD)XRD
t
a(XRD)
t
a(A)
t
su(XRDYasynchL)XCOHL
t
h(XRDYasynchL)
t
su(XRDYasynchH)XCOHL
(F)
(G)
time
from
the
beginning
of
the
– t
where n is the sample number: n = 1, 2, 3, and
c(XTIM)
su(XRDYasynchL)XCOHL
USEREADY
X2TIMING
XWRLEAD
(1)
1
0
N/A
Submit Documentation Feedback
SPRS516C – MARCH 2009 – REVISED JULY 2011
Trail
(C)
t
d(XCOHL-XZCSH)
t
d(XCOHL-XRDH)
t
h(XD)XRD
DIN
t
h(XRDYasynchH)XZCSH
access
can
be
calculated
as:
c(XTIM)
XWRACTIVE
XWRTRAIL
READYMODE
(1)
(1)
N/A
N/A
1 = XREADY
(Async)
Electrical Specifications
151
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