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TMS320C28341
TMS320C28341 | |
|---|---|
| Manufacturer Part Number | TMS320C28341 |
| Description | The TMS320C2834x (C2834x) Delfino™ microcontroller (MCU) devices build on TI's existing F2833x high-performance floating-point microcontrollers |
| Manufacturer | Texas Instruments |
| TMS320C28341 datasheets |
|
Availability: In stock
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Warranty: 60 days
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Specifications of TMS320C28341 | |||
|---|---|---|---|
| Cpu | C28x | Peak Mmacs | 200 |
| Fpu | Yes | Frequency(mhz) | 200 |
| Ram(kb) | 196 | Emif | 1 32/16-Bit |
| Dma(ch) | 1 6-Ch DMA | Pwm(ch) | 12 |
| Cap/qep | 4/2 | Mcbsp | 1 |
| I2c | 1 | Uart(sci) | 3 |
| Spi | 2 | Can | 2 |
| Timers | 3 32-Bit CPU,1 WD | Gpio | 88 |
| Pin/package | 179BGA MICROSTAR, 256BGA | Operating Temperature Range(c) | -40 to 105,-40 to 125 |
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TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
SPRS516C – MARCH 2009 – REVISED JULY 2011
6.15.8 External Interface Ready-on-Write Timing With One External Wait State
Table 6-44. External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
PARAMETER
t
Delay time, XCLKOUT high to zone chip-select active low
d(XCOH-XZCSL)
t
Delay time, XCLKOUT high or low to zone chip-select inactive high
d(XCOHL-XZCSH)
t
Delay time, XCLKOUT high to address valid
d(XCOH-XA)
t
Delay time, XCLKOUT high/low to XWE0, XWE1 low
d(XCOHL-XWEL)
t
Delay time, XCLKOUT high/low to XWE0, XWE1 high
d(XCOHL-XWEH)
t
Delay time, XCLKOUT high to XR/W low
d(XCOH-XRNWL)
t
Delay time, XCLKOUT high/low to XR/W high
d(XCOHL-XRNWH)
t
Enable time, data bus driven from XWE0, XWE1 low
en(XD)XWEL
t
Delay time, data valid after XWE0, XWE1 active low
d(XWEL-XD)
t
Hold time, address valid after zone chip-select inactive high
h(XA)XZCSH
t
Hold time, write data valid after XWE0, XWE1 inactive high
h(XD)XWE
t
Maximum time for processor to release the data bus after XR/W
dis(XD)XRNW
inactive high
(1) XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0.
(2) During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
(3) TW = trail period, write access (see
Table
Table 6-45. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
t
Setup time, XREADY (synchronous) low before XCLKOUT high/low
su(XRDYsynchL)XCOHL
t
Hold time, XREADY (synchronous) low
h(XRDYsynchL)
t
Setup time, XREADY (synchronous) high before XCLKOUT high/low
su(XRDYsynchH)XCOHL
t
Hold time, XREADY (synchronous) held high after zone chip select high
h(XRDYsynchH)XZCSH
(1) The first XREADY (synchronous) sample occurs with respect to E in
E =(XWRLEAD + XWRACTIVE) t
c(XTIM)
When first sampled, if XREADY (synchronous) is high, then the access will complete. If XREADY (synchronous) is low, it is sampled
again each t
until it is high.
c(XTIM)
For each sample, setup time from the beginning of the access can be calculated as:
F = (XWRLEAD + XWRACTIVE +n –1) t
where n is the sample number: n = 1, 2, 3, and so forth.
Table 6-46. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
t
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
su(XRDYasynchL)XCOHL
t
Hold time, XREADY (asynchronous) low
h(XRDYasynchL)
t
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
su(XRDYasynchH)XCOHL
t
Hold time, XREADY (asynchronous) held high after zone chip select high
h(XRDYasynchH)XZCSH
(1) The first XREADY (synchronous) sample occurs with respect to E in
E = (XWRLEAD + XWRACTIVE –2) t
c(XTIM)
XREADY (asynchronous) is low, it is sampled again each t
For each sample, setup time from the beginning of the access can be calculated as:
F = (XWRLEAD + XWRACTIVE –3 + n) t
where n is the sample number: n = 1, 2, 3, and so forth.
152
Electrical Specifications
focus.ti.com:
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341
(1)
(1)
(1)
6-35)
Figure
6-26:
– t
c(XTIM)
su(XRDYsynchL)XCOHL
Figure
6-26:
. When first sampled, if XREADY (asynchronous) is high, then the access will complete. If
until it is high.
c(XTIM)
– t
c(XTIM)
su(XRDYasynchL)XCOHL
Submit Documentation Feedback
www.ti.com
MIN
MAX
UNIT
0
2
ns
–0.2
0.9
ns
1.5
ns
–0.3
0.7
ns
–0.5
0.5
ns
–0.2
1.5
ns
0.3
0.6
ns
–7.5
ns
0
4
ns
(2)
ns
(3)
TW – 7.5
ns
0
ns
(1)
MIN
MAX
UNIT
8
ns
1t
ns
c(XTIM)
8
ns
0
ns
(1)
MIN
MAX
UNIT
8
1t
c(XTIM)
8
0
Copyright © 2009–2011, Texas Instruments Incorporated
ns
ns
ns
ns
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