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TMS320C28341
TMS320C28341 | |
|---|---|
| Manufacturer Part Number | TMS320C28341 |
| Description | The TMS320C2834x (C2834x) Delfino™ microcontroller (MCU) devices build on TI's existing F2833x high-performance floating-point microcontrollers |
| Manufacturer | Texas Instruments |
| TMS320C28341 datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
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Specifications of TMS320C28341 | |||
|---|---|---|---|
| Cpu | C28x | Peak Mmacs | 200 |
| Fpu | Yes | Frequency(mhz) | 200 |
| Ram(kb) | 196 | Emif | 1 32/16-Bit |
| Dma(ch) | 1 6-Ch DMA | Pwm(ch) | 12 |
| Cap/qep | 4/2 | Mcbsp | 1 |
| I2c | 1 | Uart(sci) | 3 |
| Spi | 2 | Can | 2 |
| Timers | 3 32-Bit CPU,1 WD | Gpio | 88 |
| Pin/package | 179BGA MICROSTAR, 256BGA | Operating Temperature Range(c) | -40 to 105,-40 to 125 |
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Table 2-2. Signal Descriptions (continued)
ZHH
ZFE
NAME
BALL #
BALL #
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the address
contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the
location pointed to by the PC. This pin is driven low by the MCU when a watchdog reset occurs.
XRS
P8
T10
During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK
cycles. (I/OD, ↑)
The output buffer of this pin is an open-drain with an internal pullup. It is recommended that this pin
be driven by an open-drain device.
XRS I/O Control (I) - This pin must be connected to the XRS pin on the target board. When XRS is
XRSIO
N8
T9
low (reset), the level detected on this pin puts all output buffers on the device in high-impedance
mode.
EXTSOC1A
N1
M2
External ADC SOC Group 1 A Output. Trigger for external ADC, this signal is logical OR of
ePWM1/2/3 SOCA internal signals (O)
EXTSOC1B
M3
M3
External ADC SOC Group 1 B Output. Trigger for external ADC, this signal is logical OR of
ePWM1/2/3 SOCB internal signals (O)
EXTSOC2A
M2
N1
External ADC SOC Group 2 A Output. Trigger for external ADC, this signal is logical OR of
ePWM4/5/6 SOCA internal signals (O)
EXTSOC2B
P1
N2
External ADC SOC Group 2 B Output. Trigger for external ADC, this signal is logical OR of
ePWM4/5/6 SOCB internal signals (O)
EXTSOC3A
N2
N3
External ADC SOC Group 3 A Output. Trigger for external ADC, this signal is logical OR of
ePWM7/8/9 SOCA internal signals (O)
EXTSOC3B
P2
P2
External ADC SOC Group3 B Output. Trigger for external ADC, this signal is logical OR of
ePWM7/8/9 SOCB internal signals (O)
EXTADCCLK
N3
R3
External ADC Clock Signal. Clock for external ADC support, derived from SYSCLK (O)
GPIO0
General purpose input/output 0 (I/O/Z)
EPWM1A
Enhanced PWM1 Output A and HRPWM channel (O)
B1
D2
-
-
-
-
GPIO1
General purpose input/output 1 (I/O/Z)
EPWM1B
Enhanced PWM1 Output B (O)
C1
E1
ECAP6
Enhanced Capture 6 input/output (I/O)
MFSRB
McBSP-B receive frame synch (I/O)
GPIO2
General purpose input/output 2 (I/O/Z)
EPWM2A
Enhanced PWM2 Output A and HRPWM channel (O)
F5
E2
-
-
-
-
GPIO3
General purpose input/output 3 (I/O/Z)
EPWM2B
Enhanced PWM2 Output B (O)
E4
E3
ECAP5
Enhanced Capture 5 input/output (I/O)
MCLKRB
McBSP-B receive clock (I/O)
GPIO4
General purpose input/output 4 (I/O/Z)
EPWM3A
Enhanced PWM3 output A and HRPWM channel (O)
E2
F1
-
-
-
-
GPIO5
General purpose input/output 5 (I/O/Z)
EPWM3B
Enhanced PWM3 output B (O)
E3
F2
MFSRA
McBSP-A receive frame synch (I/O)
ECAP1
Enhanced Capture input/output 1 (I/O)
GPIO6
General purpose input/output 6 (I/O/Z)
EPWM4A
Enhanced PWM4 output A and HRPWM channel (O)
F3
F3
EPWMSYNCI
External ePWM sync pulse input (I)
EPWMSYNCO
External ePWM sync pulse output (O)
GPIO7
General purpose input/output 7 (I/O/Z)
EPWM4B
Enhanced PWM4 output B (O)
F2
G1
MCLKRA
McBSP-A receive clock (I/O)
ECAP2
Enhanced capture input/output 2 (I/O)
Copyright © 2009–2011, Texas Instruments Incorporated
focus.ti.com:
TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
SPRS516C – MARCH 2009 – REVISED JULY 2011
DESCRIPTION
Reset
External ADC Interface Signals
GPIO and Peripheral Signals
Submit Documentation Feedback
Introduction
25
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