AM1808

Manufacturer Part NumberAM1808
ManufacturerTexas Instruments
AM1808 datasheet
 

Specifications of AM1808

ApplicationsIndustrial, Medical, Consumer ElectronicsOperating SystemsNeutrino,Integrity,Windows Embedded CE,Linux,VXWorks, Android
Arm Cpu1 ARM9Arm Mhz (max.)375, 456
Arm Mips(max.)375, 456On-chip L1 Cache32 KB (ARM9)
On-chip L2 Cache128 KB (ARM9)Display OptionsLCD
Dram16-bit (DDR2/LPDDR),SDRAM  Usb2
Emac10/100Sata1
Mmc/sd2Uart(sci)3
Pwm(ch)2I2c2
Upp1Mcbsp2
Mcasp1Spi2
Dma(ch)32-Ch EDMAIo Supply(v)1.8,3.3
Operating Temperature Range(c)-40 to 105,-40 to 90,0 to 90Pin/package361NFBGA
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AM1808 ARM Microprocessor
1 AM1808 ARM Microprocessor
1.1
Features
12
• Highlights
– 375/456-MHz ARM926EJ-S™ RISC Core
– ARM9 Memory Architecture
– Programmable Real-Time Unit Subsystem
– Enhanced Direct-Memory-Access Controller
3 (EDMA3)
– Two External Memory Interfaces
– Three Configurable 16550 type UART
Modules
– Two Serial Peripheral Interfaces (SPI)
– Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
– Two Master/Slave Inter-Integrated Circuit
– USB 2.0 OTG Port With Integrated PHY
– One Multichannel Audio Serial Port
– 10/100 Mb/s Ethernet MAC (EMAC)
– Three 64-Bit General-Purpose Timers
– One 64-bit General-Purpose/Watchdog Timer
– TwoEnhanced Pulse Width Modulators
– Three 32-Bit Enhanced Capture Modules
• 375/456MHz ARM926EJ-S™ RISC MPU
• ARM926EJ-S Core
– 32-Bit and 16-Bit (Thumb®) Instructions
– Single Cycle MAC
– ARM® Jazelle® Technology
– EmbeddedICE-RT™ for Real-Time Debug
• ARM9 Memory Architecture
– 16K-Byte Instruction Cache
– 16K-Byte Data Cache
– 8K-Byte RAM (Vector Table)
– 64K-Byte ROM
• Enhanced Direct-Memory-Access Controller 3
(EDMA3):
– 2 Channel Controllers
– 3 Transfer Controllers
– 64 Independent DMA Channels
– 16 Quick DMA Channels
– Programmable Transfer Burst Size
• 128K-Byte On-Chip Memory
• 1.8V or 3.3V LVCMOS IOs (except for USB and
DDR2 interfaces)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011
Check for Samples:
AM1808
• Two External Memory Interfaces:
– EMIFA
NOR (8-/16-Bit-Wide Data)
NAND (8-/16-Bit-Wide Data)
16-Bit SDRAM With 128 MB Address
Space
– DDR2/Mobile DDR Memory Controller
16-Bit DDR2 SDRAM With 512 MB
Address Space or
16-Bit mDDR SDRAM With 256 MB
Address Space
• Three Configurable 16550 type UART Modules:
– With Modem Control Signals
– 16-byte FIFO
– 16x or 13x Oversampling Option
• LCD Controller
• Two Serial Peripheral Interfaces (SPI) Each
With Multiple Chip-Selects
• Two Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
Interfaces
• Two Master/Slave Inter-Integrated Circuit (I
Bus™)
• One Host-Port Interface (HPI) With 16-Bit-Wide
Muxed Address/Data Bus For High Bandwidth
• Programmable Real-Time Unit Subsystem
(PRUSS)
– Two Independent Programmable Realtime
Unit (PRU) Cores
32-Bit Load/Store RISC architecture
4K Byte instruction RAM per core
512 Bytes data RAM per core
PRU Subsystem (PRUSS) can be disabled
via software to save power
Register 30 of each PRU is exported from
the subsystem in addition to the normal
R31 output of the PRU cores.
– Standard power management mechanism
Clock gating
Entire subsystem under a single PSC
clock gating domain
– Dedicated interrupt controller
– Dedicated switched central resource
Copyright © 2010–2011, Texas Instruments Incorporated
AM1808
2
C

AM1808 Summary of contents

  • Page 1

    ... AM1808 ARM Microprocessor 1 AM1808 ARM Microprocessor 1.1 Features 12 • Highlights – 375/456-MHz ARM926EJ-S™ RISC Core – ARM9 Memory Architecture – Programmable Real-Time Unit Subsystem – Enhanced Direct-Memory-Access Controller 3 (EDMA3) – Two External Memory Interfaces – Three Configurable 16550 type UART Modules – ...

  • Page 2

    ... Data Width on Each of Two Channels 16-bit Inclusive – Single Data Rate or Dual Data Rate Transfers 2 AM1808 ARM Microprocessor – Supports Multiple Interfaces with START, ENABLE and WAIT Controls • Serial ATA (SATA) Controller: – Supports SATA I (1.5 Gbps) and SATA II (3.0 Gbps) – ...

  • Page 3

    ... The device has a complete set of development tools for the ARM. These include C compilers, and scheduling, and a Windows™ debugger interface for visibility into source code execution. Copyright © 2010–2011, Texas Instruments Incorporated SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 AM1808 ARM Microprocessor 3 ...

  • Page 4

    ... USB1.1 ePWM eCAP OTG Ctlr OHCI Ctlr (x2) (x3) PHY PHY (1) Note: Not all peripherals are available at the same time due to multiplexing. 4 AM1808 ARM Microprocessor ARM Subsystem JTAG Interface System Control ARM926EJ-S CPU With MMU PLL/Clock Generator w/OSC 4KB ETB General- 16KB ...

  • Page 5

    ... AM1808 ARM Microprocessor .............................................. 1.1 Features ........................................... 1.2 Description ............................ 1.3 Functional Block Diagram .............................................. Revision History ........................................ 2 Device Overview ............................... 2.1 Device Characteristics ................................. 2.2 Device Compatibility ..................................... 2.3 ARM Subsystem ............................. 2.4 Memory Map Summary .................................... 2.5 Pin Assignments ............................ 2.6 Pin Multiplexing Control ................................. 2.7 Terminal Functions ......................... 2.8 Unused Pin Configurations ................................. 3 Device Configuration ......................................... 3.1 Boot Modes ................................... 3.2 SYSCFG Module .......................... 3.3 Pullup/Pulldown Resistors ...

  • Page 6

    ... Updated ASYNC1, ASYNC Mode 1.1 NOM value to 75 MHz. 5.13.1, MMCSD Peripheral Description: Added bullet for SD high capacity support 5-120, Timing Requirements for VPIF Channels 0/1 Video Capture Data and Control Inputs: Updated t 1.3V MIN to 0.5. h(VKIH-VDINV) Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 7

    ... PBGA (ZWT) Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 AM1808 DDR2, 16-bit bus width 156 MHz 16-bit SDRAM, NOR, NAND MMC and SD cards supported 2 channel controllers, 3 transfer controllers 3 (each with RTS and CTS flow control) ...

  • Page 8

    ... Memory Management Unit (MMU), and other ARM subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as supervisor or system mode. 8 Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com ...

  • Page 9

    ... Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the Config Bus and the external memories bus. Copyright © 2010–2011, Texas Instruments Incorporated SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 Device Overview 9 ...

  • Page 10

    ... SRAM. Likewise almost all of the on chip peripherals are accessible to the ARM by default. See Table 2-2 for a detailed top level device memory map that includes the ARM memory space. 10 Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com ...

  • Page 11

    ... UART 1 UART 2 McBSP0 McBSP0 FIFO Ctrl McBSP1 McBSP1 FIFO Ctrl USB0 UHPI LCD Controller Memory Protection Unit 1 (MPU 1) Memory Protection Unit 2 (MPU 2) UPP Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 Master LCDC Mem Map Peripheral Mem Map Map Device Overview 11 ...

  • Page 12

    ... EMIFA async data (CS3) EMIFA async data (CS4) EMIFA async data (CS5) EMIFA Control Regs On-Chip RAM DDR2 Control Regs Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Master LCDC Mem Map Peripheral Mem Map Map ...

  • Page 13

    ... ARM Mem Map EDMA Mem Map PRUSS Mem DDR2 Data ARM local ROM ARM Interrupt Controller ARM local RAM ARM Local RAM (PRU0 only) Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 Master LCDC Mem Map Peripheral Mem Map Map Device Overview 13 ...

  • Page 14

    ... DD18 SS VP_CLKOUT3/ PRU1_R30[0 DD18 GP6[1]/ PRU1_R31[ Figure 2-1. Pin Map (Quad A) Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com DDR_CLKP DDR_RAS DDR_D[15] W DDR_BA[0] DDR_D[13] V DDR_CS U DDR_BA[2] DDR_CAS DDR_D[12] DDR_BA[1] DDR_D[10] T DDR_WE DDR_DVDD18 DDR_DVDD18 DDR_DQM[1] ...

  • Page 15

    ... NC_M14 PLL1_VSSA TDI RTC_CVDD DVDD3318_C PLL0_VDDA TMS DVDD3318_C DVDD3318_B EMU1 RESET Figure 2-2. Pin Map (Quad B) Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 VP_DIN[1]/ VP_DIN[0]/ VP_DIN[2]/ UHPI_HD[9]/ UHPI_HD[8]/ UHPI_HD[10]/ UPP_D[9]/ UPP_D[8]/ UPP_D[10]/ RMII_MHZ_50_CLK / RMII_CRS_DV/ RMII_RXER / PRU0_R31[23] PRU1_R31[29] PRU0_R31[24] ...

  • Page 16

    ... EMA_BA[1]/ PRU0_R30[3]/ PRU1_R30[16]/ GP5[4] GP2[9] GP2[5]/ GP5[8] PRU0_R31[ Figure 2-3. Pin Map (Quad C) Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com RTC_XI RSVDN TDO J SPI1_SOMI/ RTC_VSS RTC_XO H GP2[11] SPI1_SCS[6]/ SPI1_SIMO/ I2C0_SDA/ ...

  • Page 17

    ... GP2[6]/ GP3[1] GP3[9] PRU0_R31[4] EMA_A[19]/ EMA_WEN_DQM[0]/ EMA_D[0]/ MMCSD0_DAT[2]/ GP2[3] GP4[8] PRU1_R30[27]/ GP4[3] EMA_A[21]/ EMA_D[2]/ MMCSD0_DAT[0]/ EMA_WE/ GP4[10] PRU1_R30[29]/ GP3[11] GP4[5] EMA_CAS/ EMA_A[22]/ EMA_D[1]/ PRU0_R30[2]/ MMCSD0_CMD/ GP4[9] PRU1_R30[30]/ GP2[4]/ GP4[6] PRU0_R31[ Device Overview AM1808 ...

  • Page 18

    ... IPU B K17 I/O IPD B Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com DESCRIPTION Device reset input Reset output JTAG test mode select JTAG test data input JTAG test data output JTAG test clock JTAG test reset ...

  • Page 19

    ... Product Folder Link(s): AM1808 SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 DESCRIPTION PLL Observation Clock Oscillator input Oscillator output Oscillator ground PLL analog V (1.2-V filtered supply) DD PLL analog V (for filter) SS PLL analog V (1.2-V filtered supply) DD PLL analog V (for filter) SS Device Overview AM1808 19 ...

  • Page 20

    ... TYPE PULL GROUP NO CP[0] A Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com DESCRIPTION (3) RTC 32-kHz oscillator input RTC 32-kHz oscillator output RTC Alarm RTC module core power (isolated from chip Oscillator ground ...

  • Page 21

    ... CP[17 I/O CP[17] B A10 O CP[18] B B10 O CP[18] B A11 O CP[18] B C10 O CP[18] B E11 O CP[18] B B11 O CP[18] B E12 O CP[18] B C11 O CP[19] B A12 O CP[19] B D11 O CP[19] B D13 O CP[19] B Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 DESCRIPTION EMIFA data bus EMIFA address bus Device Overview 21 ...

  • Page 22

    ... B B19 I CP[16] B Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com DESCRIPTION EMIFA address bus EMIFA bank address EMIFA clock EMIFA SDRAM clock enable EMIFA SDRAM row address strobe EMIFA SDRAM column address strobe ...

  • Page 23

    ... T8 O IPD DDR2 write enable W9 O IPD DDR2 row address strobe U9 O IPD DDR2 column address strobe V9 O IPD DDR2 chip select W13 O IPD DDR2 data mask outputs R10 O IPD Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 DESCRIPTION Device Overview 23 ...

  • Page 24

    ... Note even in the case of mDDR an external resistor divider connected to this pin is necessary. N10, P10, N9, P9, R9, P8, PWR — DDR PHY 1.8V power supply pins R8, P7, R7, N6 Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com DESCRIPTION ...

  • Page 25

    ... F18 I/O CP[14] F19 I/O CP[13] E18 I/O CP[13] F16 I/O CP[12] F17 I/O CP[12] G18 I/O CP[11] G16 I/O CP[11] G17 I/O CP[15] H17 I/O CP[15] Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 POWER DESCRIPTION (3) GROUP A SPI0 clock A SPI0 enable SPI0 chip selects SPI0 data A slave-in-master-out SPI0 data A slave-out-master-in A SPI1 clock A SPI1 enable ...

  • Page 26

    ... V18 O V19 O U19 O T16 O R18 O R19 O R15 O F18 O E19 O C17 O Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com POWER (2) DESCRIPTION (3) GROUP CP[23] C CP[23] C CP[24] C CP[24] C CP[24] C CP[24] C CP30] C CP[30] C CP[30] C CP[30] C CP[19] B CP[0] A PRU0 Output ...

  • Page 27

    ... V18 I V19 I U19 I T16 I R18 I R19 I R15 A16 B19 I B18 I Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 POWER (2) DESCRIPTION (3) GROUP CP[16] B CP[16] B CP[16] B PRU0 Output Signals CP[16] B CP[16] B CP[16] B CP[26] C CP[26] C CP[26] C CP[26] C CP[26] C CP[26] C CP[26] C CP[0] A CP[0] A CP[0] A CP[0] A CP[0] ...

  • Page 28

    ... B13 O T17 O T18 O R17 O R16 O W14 O V15 Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com POWER (2) DESCRIPTION (3) GROUP CP[18] B CP[18] B CP[18] B CP[18] B CP[18] B CP[18] B CP[18] B CP[18] B CP[19] B CP[19] B CP[19] B CP[19] B CP[19] B CP[19] B ...

  • Page 29

    ... C10 I E11 I T15 I V15 P17 I Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 POWER (2) DESCRIPTION (3) GROUP CP[26] C CP[31] C CP[30] C CP[30] C CP[30] C CP[30] C CP[18] B CP[18] B CP[18] B CP[18] B CP[18] B CP[18] B CP[24] C PRU1 Input CP[25] C Signals CP[28] C CP[28] C CP[28] C CP[28] ...

  • Page 30

    ... F3 I/O CP[6] eCAP1 E4 I/O CP[3] eCAP2 A4 I/O CP[1] Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com DESCRIPTION (3) enhanced capture 0 input or A auxiliary PWM 0 output enhanced capture 1 input or A auxiliary PWM 1 output enhanced capture 2 input or A auxiliary PWM 2 output ...

  • Page 31

    ... CP[14] A E19 I/O CP[14 CP[4] A Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 DESCRIPTION eHRPWM0 A output (with high-resolution) eHRPWM0 B output eHRPWM0 trip zone input eHRPWM0 sync input eHRPWM0 sync output eHRPWM1 A output (with high-resolution) eHRPWM1 B output eHRPWM1 trip zone input Device Overview ...

  • Page 32

    ... DVDD3318_C. 32 Device Overview (2) (3) TYPE PULL NO CP[29 CP[29 CP[29 CP[29 CP[29 CP[29 CP[29 CP[29] Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com (1) POWER DESCRIPTION (4) GROUP Boot Mode Selection Pins ...

  • Page 33

    ... I CP[0] UART2 F17 I CP[12] F16 O CP[12 CP[ CP[0] Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 DESCRIPTION (3) A UART0 receive data A UART0 transmit data A UART0 ready-to-send output A UART0 clear-to-send input A UART1 receive data A UART1 transmit data A UART1 ready-to-send output A UART1 clear-to-send input ...

  • Page 34

    ... Device Overview (1) TYPE PULL NO. I2C0 G18 I/O CP[11] G16 I/O CP[11] I2C1 F16 I/O CP[12] F17 I/O CP[12] Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com POWER (2) DESCRIPTION (3) GROUP A I2C0 serial data A I2C0 serial clock A I2C1 serial data A I2C1 serial clock ...

  • Page 35

    ... NO. TIMER0 E16 I E16 O TIMER1 (Watchdog) D17 I D17 O TIMER2 F18 I G16 O TIMER3 E19 I G18 O Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 POWER (1) (2) PULL DESCRIPTION (3) GROUP CP[10] A Timer0 lower input Timer0 lower CP[10] A output CP[10] A Timer1 lower input Timer1 lower CP[10] A output CP[14] A Timer2 lower input ...

  • Page 36

    ... I/O CP[6] A3 I/O CP[0] B1 I/O CP[0] B2 I/O CP[0] A2 I/O CP[0] A1 I/O CP[0] C2 I/O CP[0] D5 I/O CP[0] Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com DESCRIPTION ( McASP0 serial data McASP0 transmit master clock A McASP0 transmit bit clock A McASP0 transmit frame sync ...

  • Page 37

    ... CP[ CP[2] A Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 DESCRIPTION McBSP0 sample rate generator clock input McBSP0 receive clock McBSP0 receive frame sync McBSP0 receive data McBSP0 transmit clock McBSP0 transmit frame sync McBSP0 transmit data McBSP1 sample rate generator clock input ...

  • Page 38

    ... PWR M12 PWR — — Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com DESCRIPTION USB0 PHY data minus USB0 PHY data plus USB0 PHY 3.3-V supply USB0 PHY identification (mini-A or mini-B plug) USB0 bus voltage USB0 controller VBUS control output ...

  • Page 39

    ... CP[26] C U18 O CP[26] C Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 DESCRIPTION (3) EMAC MII Transmit enable output EMAC MII Transmit clock input EMAC MII Collision detect input EMAC MII transmit data EMAC MII receive error input EMAC MII carrier sense input ...

  • Page 40

    ... SPI0_SCS[0] / TM64P1_OUT12 / GP1[6] / MDIO_D / TM64P1_IN12 SPI0_SCS[1] / TM64P0_OUT12 / GP1[7] / MDIO_CLK / TM64P0_IN12 40 Device Overview POWER (1) (2) TYPE PULL GROUP NO. MDIO D17 I/O CP[10] A E16 O CP[10] A Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com DESCRIPTION (3) MDIO serial data MDIO clock ...

  • Page 41

    ... A11 I/O CP[18] B10 I/O CP[18] MMCSD1 G2 O CP[30] J4 I/O CP[30] F1 I/O CP[31] F2 I/O CP[31] H4 I/O CP[31] G4 I/O CP[31] H3 I/O CP[30] K3 I/O CP[30] J3 I/O CP[30] G1 I/O CP[30] Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 POWER (2) DESCRIPTION (3) GROUP B MMCSD0 Clock B MMCSD0 Command MMC/SD0 data MMCSD1 Clock C MMCSD1 Command MMC/SD1 data Device Overview 41 ...

  • Page 42

    ... I/O CP[28] W2 I/O CP[28] W1 I/O CP[28 CP[31 CP[31 CP[31 CP[31 CP[31] Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com POWER DESCRIPTION (3) GROUP LCD data bus LCD pixel clock C LCD horizontal sync ...

  • Page 43

    ... K2, L3, M1 Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 DESCRIPTION SATA receive data (positive) SATA receive data (negative) SATA transmit data (positive) SATA transmit data (negative) SATA PHY reference clock (positive) SATA PHY reference clock (negative) SATA mechanical presence switch input ...

  • Page 44

    ... U17 I CP[24] W15 I CP[24] U16 I CP[24] T15 I CP[24] W14 I CP[25] V15 I CP[25] T18 I CP[22] R16 O CP[23] Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com POWER (2) DESCRIPTION (3) GROUP UHPI data bus UHPI access control C ...

  • Page 45

    ... RESETOUT / UHPI_HAS / PRU1_R30[14] / GP6[15] Copyright © 2010–2011, Texas Instruments Incorporated SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 (1) TYPE PULL NO. R17 O CP[23] T17 I CP[21] Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 POWER (2) DESCRIPTION (3) GROUP C UHPI ready C UHPI address strobe Device Overview 45 ...

  • Page 46

    ... G3 I/O CP[30] U17 I/O CP[24] W15 I/O CP[24] U16 I/O CP[24] T15 I/O CP[24] Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com POWER DESCRIPTION (3) GROUP uPP 2x transmit clock C input C uPP channel B clock C uPP channel B start C uPP channel B enable C uPP channel B wait C uPP channel A clock ...

  • Page 47

    ... I/O CP[26] W17 I/O CP[26] W18 I/O CP[26] W19 I/O CP[26] V18 I/O CP[27] V19 I/O CP[27] U19 I/O CP[27] T16 I/O CP[27] R18 I/O CP[27] R19 I/O CP[27] R15 I/O CP[27] P17 I/O CP[27] Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 POWER DESCRIPTION (3) GROUP uPP data bus Device Overview ...

  • Page 48

    ... W17 I CP[26] W18 I CP[26] W19 I CP[26] VIDEO OUTPUT H3 I CP[30 CP[30] Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com POWER DESCRIPTION (3) GROUP VPIF capture channel 0 C input clock VPIF capture channel 1 C input clock ...

  • Page 49

    ... O CP[28 CP[28 CP[28 CP[28 CP[28 CP[28 CP[28 CP[28] Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 POWER DESCRIPTION (3) GROUP VPIF display channel 3 C input clock VPIF display channel 3 C output clock VPIF display data bus ...

  • Page 50

    ... Device Overview (1) (2) TYPE PULL NO. GP0 A1 I/O CP[0] B1 I/O CP[0] C2 I/O CP[0] B2 I/O CP[0] A2 I/O CP[0] A3 I/O CP[0] D5 I/O CP[0] F4 I/O CP[0] A4 I/O CP[1] B4 I/O CP[2] B3 I/O CP[2] C4 I/O CP[2] C5 I/O CP[2] D4 I/O CP[2] C3 I/O CP[2] E4 I/O CP[3] Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com POWER DESCRIPTION (3) GROUP GPIO Bank ...

  • Page 51

    ... H17 I/O CP[15] G17 I/O CP[15] A15 I/O CP[16] C15 I/O CP[16] B7 I/O CP[16] D8 I/O CP[16] A16 I/O CP[16] A9 I/O CP[16] C8 I/O CP[16] A5 I/O CP[16] B19 I/O CP[16] A18 I/O CP[16] Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 POWER DESCRIPTION (3) GROUP GPIO Bank GPIO Bank Device Overview ...

  • Page 52

    ... C9 I/O CP[17] E9 I/O CP[18] A10 I/O CP[18] B10 I/O CP[18] A11 I/O CP[18] C10 I/O CP[18] E11 I/O CP[18] B11 I/O CP[18] E12 I/O CP[18] Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com POWER DESCRIPTION (3) GROUP GPIO Bank ...

  • Page 53

    ... U17 I/O CP[24] W15 I/O CP[24] U16 I/O CP[24] T15 I/O CP[24] W14 I/O CP[25] V15 I/O CP[25] P17 I/O CP[27] H3 I/O CP[30] K3 I/O CP[30] J3 I/O CP[30] K4 I/O CP[30] R5 I/O CP[31] Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 POWER DESCRIPTION (3) GROUP GPIO Bank GPIO Bank Device Overview ...

  • Page 54

    ... CP[31] F3 I/O CP[6] C16 I/O CP[7] C18 I/O CP[7] C19 I/O CP[8] D18 I/O CP[8] E17 I/O CP[9] D16 I/O CP[9] K17 I/O IPD Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com POWER DESCRIPTION (3) GROUP GPIO Bank ...

  • Page 55

    ... Reserved. For proper device operation, the pin must be pulled up to supply I DVDD3318_B. — These pins may be left unconnected or connected to ground (VSS). — These pins should be left unconnected (do not connect to power or ground). Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 Device Overview 55 ...

  • Page 56

    ... PWR USB1 PHY 3.3-V supply PWR USB1 PHY 1.8-V supply PWR SATA PHY 1.2V logic supply GND SATA PHY ground reference PWR DDR PHY 1.8V power supply pins Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com DESCRIPTION Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 57

    ... VSS Configuration May be held high (CVDD) or low No Connect May be used as GPIO or other peripheral function Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 Use as USB0 function Use as USB0 function Use as USB0 function Use as USB0 function Use as USB0 function 3.3V 1.8V filter capacitor VSS or No Connect ...

  • Page 58

    ... VTPIO[14]=1. 58 Device Overview Configuration Connect to CVDD VSS Configuration No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com (1) ...

  • Page 59

    ... Enable and selection of the programmable pin pullups and pulldowns Copyright © 2010–2011, Texas Instruments Incorporated SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 (SPRAB41) Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 for more details on the ROM Boot Device Configuration 59 ...

  • Page 60

    ... Pin Multiplexing Control 8 Register Pin Multiplexing Control 9 Register Pin Multiplexing Control 10 Register Pin Multiplexing Control 11 Register Pin Multiplexing Control 12 Register Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Register Access — — — — — ...

  • Page 61

    ... DDR Slew Register DeepSleep Register Pullup / Pulldown Enable Register Pullup / Pulldown Selection Register RXACTIVE Control Register PWRDN Control Register Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 Register Access Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode — ...

  • Page 62

    ... For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal functions table. 62 Device Configuration pullup/pulldown resistor IL ), and the low-/high-level input voltages (V I 4.2, Recommended Operating Conditions. Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com be implemented. Although, internal level of IL level of all levels for the logic family of ...

  • Page 63

    ... Limit clamp current that flows through the I/O's internal diode protection cells. (default) (5) Human Body Model (HBM) (6) Charged Device Model (CDM) Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 -0 1 (2) -0 3.8V -0 CVDD + 0.3V -0.3V to DVDD + 0.3V DVDD + 20 20% of Signal Period ...

  • Page 64

    ... DDR_DVDD18 1.8V operating point 1.71 3.3V operating point 3.15 1.8V operating point 1.71 3.3V operating point 3.15 1.8V operating point 1.71 3.3V operating point 3.15 0 (4) 2 (4) 0.65*DVDD 0.8*RTC_CVDD 0.8*CVDD (4) (4) Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com NOM MAX UNIT 1.3 1.35 V 1.2 1.32 V 1.1 1.16 V 1.0 1.05 V 1.3 1.35 V 1.2 1.32 1.2 1.32 V 1.2 1. ...

  • Page 65

    ... CVDD = 1.0V 0 operating point CVDD = 1.3V 0 operating point CVDD = 1.2V 0 operating point CVDD = 1.1V 0 operating point CVDD = 1.0V 0 operating point Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 NOM MAX UNIT 0.2*RTC_CVDD V 0.2*CVDD V 5.25 V 2000 mV (5) 0.25P 456 375 MHz 200 100 456 ...

  • Page 66

    ... Temperature (Tj °C 1. °C 1. °C 1.2V -40 to 105 °C 1. °C 1.3V - °C 1.3V Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Power-On Hours [POH] (hours) 100,000 100,000 100,000 (1) 75,000 100,000 100,000 Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 67

    ... V = VSS to DVDD with opposing I (3) internal pulldown resistor V = VSS to DVDD with opposing I (3) internal pulldown resistor indicates the input leakage current. For bi-directional pins Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 MIN TYP MAX UNIT 2 0.4 V 0.2 V 0.45 V ± ...

  • Page 68

    ... Peripheral Information and Electrical Specifications Tester Pin Electronics Transmission Line Ω (see note) for both "0" and "1" logic levels. ref Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Data Sheet Timing Reference Point Output Under Test Device Pin (see note) V ...

  • Page 69

    ... Copyright © 2010–2011, Texas Instruments Incorporated SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 and V (or between Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 and monotonic USB1_VDDA18 and 69 ...

  • Page 70

    ... All device pins high-impedance state • The RTC peripheral is not reset during a warm reset. A software sequence is required to reset the RTC 70 Peripheral Information and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com ...

  • Page 71

    ... Copyright © 2010–2011, Texas Instruments Incorporated SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 Power Supplies Stable Clock Source Stable Config Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 (1) ( 1.3V, 1.2V 1.1V 1.0V MIN MAX MIN MAX MIN ...

  • Page 72

    ... TRST RESET 5 RESETOUT Boot Pins Driven or Hi-Z Figure 5-5. Warm Reset (RESET active, TRST high) Timing 72 Peripheral Information and Electrical Specifications Power Supplies Stable Config Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 73

    ... OSCOUT C 1 OSCV SS Figure 5-6. On-Chip Oscillator PARAMETER Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 Figure 5-6 and Figure Figure 5-7 Clock Input to PLL MIN MAX 12 30 AM1808 5-7. For UNIT MHz 73 ...

  • Page 74

    ... PLL Multiplier Control: PLLM • Software programmable PLL Bypass: PLLEN 74 Peripheral Information and Electrical Specifications OSCIN OSCOUT NC OSCV SS Figure 5-7. External 1.2V Clock Source 0.4 t 0.4 t Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Clock Input to PLL MIN MAX c(OSCIN) c(OSCIN) (1) 0.25P or 10 0.02P Copyright © ...

  • Page 75

    ... V 50R SS 50R 0.1 0.01 µF µF V 50R SS Figure 5-9 illustrates the high-level view of the PLL Topology. Table 5-4 before enabling the device to run from the PLL by Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 PLL0_VDDA PLL0_VSSA PLL1_VDDA PLL1_VSSA 75 ...

  • Page 76

    ... PLL POSTDIV PLLM 14h 17h SYSCLK1 OSCDIV SYSCLK2 18h SYSCLK3 19h OCSEL[OCSRC] Figure 5-9. PLL Topology Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com PLL Controller 0 0 PLLDIV1 (/1) SYSCLK1 PLLDIV2 (/2) SYSCLK2 1 PLLDIV4 (/4) SYSCLK4 PLLDIV5 (/3) SYSCLK5 PLLDIV6 (/1) SYSCLK6 PLLDIV7 (/6) SYSCLK7 PLLDIV3 (/3) ...

  • Page 77

    ... Max PLL Lock Time = N/A N (if internal oscillator is used (if external clock source is used) x20 x4 N/A 300 /1 /1 SPRUGM9 - AM1808/AM1810 ARM Microprocessor System Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 MAX UNIT N/A ns 2000 N m OSCIN where N = Pre-Divider Ratio cycles ...

  • Page 78

    ... Peripheral Information and Electrical Specifications www.ti.com for this processor. CLOCK DOMAIN 1.3V NOM Async Mode SDRAM Mode Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com 1.2V NOM 1.1V NOM 1.0V NOM - - - 228 MHz 187.5 MHz 100 MHz 50 MHz 114 MHz 93 ...

  • Page 79

    ... Support for nesting can be enabled/disabled by software, with the option of automatic nesting on a global or per host interrupt basis; or manual nesting. Copyright © 2010–2011, Texas Instruments Incorporated SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 79 ...

  • Page 80

    ... EMAC - Core 1 Transmit Interrupt EMAC - Core 1 Miscellaneous Interrupt DDR2 Controller GPIO Bank 0 Interrupt GPIO Bank 1 Interrupt GPIO Bank 2 Interrupt GPIO Bank 3 Interrupt GPIO Bank 4 Interrupt GPIO Bank 5 Interrupt Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com ...

  • Page 81

    ... Timer64P2 - Compare 2 Timer64P2 - Compare 3 Timer64P2 - Compare 4 Timer64P2 - Compare 5 Timer64P2 - Compare 6 Timer64P2 - Compare 7 Timer64P3 - Compare 0 Timer64P3 - Compare 1 Timer64P3 - Compare 2 Timer64P3 - Compare 3 Timer64P3 - Compare 4 Timer64P3 - Compare 5 Timer64P3 - Compare 6 Timer64P3 - Compare 7 PSC0 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 81 ...

  • Page 82

    ... EDMA3_1Channel Controller 0 Error Interrupt EDMA3_1 Transfer Controller 0 Error Interrupt Timer64P 3 - Combined TINT12 and TINT34 McBSP0 Receive Interrupt McBSP0 Transmit Interrupt McBSP1 Receive Interrupt McBSP1 Transmit Interrupt Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com ...

  • Page 83

    ... System Interrupt Status Enabled / Clear Registers SECR[1] SECR[2] SECR[3] - Reserved ESR[0] System Interrupt Enable Set Registers ESR[1] ESR[2] ESR[3] - Reserved ECR[0] System Interrupt Enable Clear Registers ECR[1] ECR[2] ECR[3] - Reserved Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 DESCRIPTION 83 ...

  • Page 84

    ... DSR[1] - Reserved HINLR[0] Host Interrupt Nesting Level Registers HINLR[1] - Reserved HIER[0] Host Interrupt Enable Register - Reserved HIPVR[0] - Host Interrupt Prioritized Vector Registers HIPVR[1] - Reserved Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com DESCRIPTION ...

  • Page 85

    ... MDSTAT7 Module 7 Status Register MDSTAT8 Module 8 Status Register MDSTAT9 Module 9 Status Register MDSTAT10 Module 10 Status Register MDSTAT11 Module 11 Status Register MDSTAT12 Module 12 Status Register MDSTAT13 Module 13 Status Register Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 85 ...

  • Page 86

    ... Module 22 Control Register MDCTL23 Module 23 Control Register MDCTL24 Module 24 Control Register MDCTL25 Module 25 Control Register MDCTL26 Module 26 Control Register MDCTL27 Module 27 Control Register MDCTL28 Module 28 Control Register Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com ...

  • Page 87

    ... AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) SwRstDisable AlwaysON (PD0) SwRstDisable — Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 REGISTER DESCRIPTION Auto Sleep/Wake Only — — — — — — — Enable Yes — ...

  • Page 88

    ... Enable AlwaysON (PD0) Enable AlwaysON (PD0) Enable AlwaysON (PD0) Enable PD_SHRAM Enable Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Auto Sleep/Wake Only — — — — — — — — — — ...

  • Page 89

    ... The transition from sleep to enabled state has some cycle latency associated with it not envisioned to use this mode when peripherals are fully operational and moving data. Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 89 ...

  • Page 90

    ... Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Event Name / Source MMCSD0 Receive MMCSD0 Transmit SPI1 Receive SPI1 Transmit PRU_EVTOUT6 PRU_EVTOUT7 GPIO Bank 2 Interrupt GPIO Bank 3 Interrupt I2C0 Receive ...

  • Page 91

    ... QSTAT1 Queue 1 Status Register QWMTHRA Queue Watermark Threshold A Register CCSTAT EDMA3CC Status Register Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 Table 5-14 is the list of EDMA3 Transfer REGISTER DESCRIPTION AM1808 91 ...

  • Page 92

    ... QDMA Event Enable Clear Register QEESR QDMA Event Enable Set Register QSER QDMA Secondary Event Register QSECR QDMA Secondary Event Clear Register Shadow Region 1 Channel Registers ER Event Register Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 93

    ... Source Active Memory Protection Proxy Register 0x01E3 8258 SACNTRLD Source Active Count Reload Register 0x01E3 825C SASRCBREF Source Active Source Address B-Reference Register 0x01E3 8260 SADSTBREF Source Active Destination Address B-Reference Register Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 93 ...

  • Page 94

    ... Parameters Set 3 (8 32-bit words) 0x01E3 4080 - 0x01E3 409F Parameters Set 4 (8 32-bit words) 0x01E3 40A0 - 0x01E3 40BF Parameters Set 5 (8 32-bit words) Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Table 5-16 shows the DESCRIPTION Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 95

    ... Source Address A_B_CNT A Count, B Count DST Destination Address SRC_DST_BIDX Source B Index, Destination B Index LINK_BCNTRLD Link Address, B Count Reload SRC_DST_CIDX Source C Index, Destination C Index CCNT C Count Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 DESCRIPTION PARAMETER ENTRY 95 ...

  • Page 96

    ... Finally, note that the EMIFA does not support Mobile SDRAM devices. Table 5-17 shows the supported SDRAM configurations for EMIFA. 96 Peripheral Information and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Section 5.10.1. It ...

  • Page 97

    ... Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 (1) Total Total Memory Memory Memory Density (Mbits) (Mbytes) (Mbits) 256 32 256 512 64 512 1024 128 1024 512 64 512 1024 ...

  • Page 98

    ... NAND Flash 4-Bit ECC Error Address Register 1 NAND Flash 4-Bit ECC Error Address Register 2 NAND Flash 4-Bit ECC Error Value Register 1 NAND Flash 4-Bit ECC Error Value Register 2 Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com ...

  • Page 99

    ... Output hold time, EMA_CLK rising to EMA_D[15:0] driving ena(CLKH-DLZ) Copyright © 2010–2011, Texas Instruments Incorporated SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 assume testing over recommended operating conditions. Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 1.3V, 1.2V 1.1V 1.0V UNIT MIN MAX MIN MAX ...

  • Page 100

    ... Peripheral Information and Electrical Specifications 1 BASIC SDRAM WRITE OPERATION Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com 6 2 EM_CLK Delay 18 ...

  • Page 101

    ... SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 READS and WRITES READS WRITES describe EMIF transactions that include extended wait states inserted during the STROBE Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 (1) 1.2V 1.1V 1.0V MIN MAX MIN MAX ...

  • Page 102

    ... WRITES (WS+WST+WH)*E-3 (WS+WST+WH+(EWC*16))* (WS+WST+WH+(EWC*16))* (WS)* (WH)*E-3 -3 (WS)*E-3 (WH)*E-3 (WS)*E-3 (WH)*E-3 (WS)*E-3 (WH)*E-3 Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com (1) (2) (3) UNIT Nom MAX (TA)*E (TA)* (RS+RST+RH)*E (RS+RST+RH)* (RS+RST+RH+(EWC*16))* (RS)*E (RS)*E (RH)*E (RH)* (RS)*E (RS)*E+3 ns ...

  • Page 103

    ... Figure 5-12. Asynchronous Memory Read Timing for EMIFA Submit Documentation Feedback Product Folder Link(s): AM1808 SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 (1) (2) (3) (continued) 1.3V, 1.2V, 1.1V, 1.0V Nom MAX (WST)*E-3 (WST)*E (WST+(EWC*16))*E (WST+(EWC*16))*E+3 3E-3 4E (WS)*E-3 (WS)*E (WH)*E-3 (WH)* Peripheral Information and Electrical Specifications AM1808 UNIT (WST)*E 4E+3 ns (WS)*E+3 ns (WH)*E+3 ns 103 ...

  • Page 104

    ... EMA_ WE _DQM[1:0] EMA_A_RW EMA_WE EMA_D[15:0] EMA_OE Figure 5-13. Asynchronous Memory Write Timing for EMIFA 104 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 105

    ... STROBE Extended Due to EMA_WAIT Asserted Deasserted Figure 5-14. EMA_WAIT Read Timing Requirements Figure 5-15. EMA_WAIT Write Timing Requirements Submit Documentation Feedback Product Folder Link(s): AM1808 SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 STROBE HOLD 11 Peripheral Information and Electrical Specifications AM1808 105 ...

  • Page 106

    ... Power down mode • Prioritized refresh • Programmable refresh rate and backlog counter • Programmable timing parameters • Little endian 106 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 107

    ... MAX MIN DDR2 125 156 125 mDDR 105 150 100 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 1.1V 1.0V UNIT MAX MIN MAX (1) (1) 150 — — MHz 133 ...

  • Page 108

    ... Interrupt Mask Clear Register DRPYC1R DDR PHY Control Register 1 VTP IO Control Register Figure 5-17. Pin numbers for the device can be obtained from the pin Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com REGISTER DESCRIPTION Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 109

    ... ( (2) (2) (2) 0.1 F 0.1 F Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 DDR2/mDDR ODT DQ0 DQ7 DQ7 LDM LDQS LDQS DQ8 DQ15 UDM UDQS UDQS BA0 BA2 A0 A13 CS CAS ...

  • Page 110

    ... Peripheral Information and Electrical Specifications ( (2) (2) (2) 0.1 F 0.1 F Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com ODT DQ0 - DQ7 BA0-BA2 A0-A13 DM DQS DQS CAS RAS WE CKE VREF BA0-BA2 A0-A13 CAS RAS WE CKE DM DQS ...

  • Page 111

    ... MIN MAX x8 x16 1 2 Devices Table Table 5-27. DESCRIPTION Top Routing Mostly Horizontal Ground Power Internal Routing Ground Bottom Routing Mostly Vertical MIN TYP MAX Z-5 Z Z+5 AM1808 UNIT Bits 5-26. UNIT Mils Mils Mils Mils Ω Ω 111 ...

  • Page 112

    ... The placement does not restrict the side of the PCB OFFSET DDR2/mDDR Y Device Y OFFSET A1 Recommended DDR2/mDDR Device Orientation Table 5-28. Placement Specifications (4) 5-27. Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com (1) (2) MIN MAX UNIT 1750 Mils 1280 Mils (3) 650 Mils ( Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 113

    ... Figure 5-19. DDR2/mDDR Keepout Region Copyright © 2010–2011, Texas Instruments Incorporated SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 A1 DDR2/mDDR Device A1 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 Figure 5-19. The size of this 113 ...

  • Page 114

    ... These devices should be placed as close as possible to the device being bypassed. (4) Only used on dual-memory systems. 114 Peripheral Information and Electrical Specifications Table 5-29. Bulk Bypass Capacitors (1) (1) (1) (2) (2) (1) (3) (3) (3) (4) (4) Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com MIN MAX UNIT 3 Devices 30 μF 1 Devices 22 μF 1 Devices 22 μ ...

  • Page 115

    ... Table 5-32. Signal Net Class Definitions PIN NAMES DDR_BA[2:0], DDR_A[13:0], DDR_CS, DDR_CAS, DDR_RAS, DDR_WE, DDR_CKE DDR_D[7:0], DDR_DQM0 DDR_D[15:8], DDR_DQM1 DDR_DQGATE0, DDR_DQGATE1 (4) Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 Table 5-32 lists the signal net (1) (2) (3) MIN TYP MAX UNIT 0 10 Ω 0 ...

  • Page 116

    ... VREF Bypass Capacitor A1 DDR2/mDDR A1 Neck down to minimum in BGA escape regions is acceptable. Narrowing to accomodate via congestion for short distances is also acceptable. Best performance is obtained if the width of VREF is maximized. Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 117

    ... Copyright © 2010–2011, Texas Instruments Incorporated SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 (1) (3) (1) (4) CACLM-50 (1) (1) (3) 5-27. Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 MIN TYP MAX ( (2) 4w CACLM CACLM+50 100 100 (2) 4w (2) 3w 100 ...

  • Page 118

    ... Peripheral Information and Electrical Specifications MIN (1) 4w DQLM-50 (1) (5) 4w (1) (6) 3w 5-27. Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com TYP MAX UNIT (2) DQLM DQLM+50 Mils 100 Mils 100 Mils (2) (2) Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 119

    ... SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 Table 5- Figure 5-23. DQGATE Routing MIN 4w DQLM-50 5-27. Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 contains the routing specification. TYP MAX UNIT (1) CKB0B (2) DQLM DQLM+50 Mils 100 Mils 119 ...

  • Page 120

    ... Programmable range 5, end address Programmable range 5, memory page protection attributes - Reserved Programmable range 6, start address Programmable range 6, end address Programmable range 6, memory page protection attributes - Reserved Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com REGISTER DESCRIPTION Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 121

    ... Programmable range 8, start address Programmable range 8, end address Programmable range 8, memory page protection attributes - Reserved Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 REGISTER DESCRIPTION REGISTER DESCRIPTION AM1808 121 ...

  • Page 122

    ... Programmable range 12, start address Programmable range 12, end address Programmable range 12, memory page protection attributes - Reserved Fault address FLTSTAT Fault status FLTCLR Fault clear - Reserved Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com REGISTER DESCRIPTION Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 123

    ... MMC Command Index Register SDIOCTL SDIO Control Register SDIOST0 SDIO Status Register 0 SDIOIEN SDIO Interrupt Enable Register SDIOIST SDIO Interrupt Status Register MMCFIFOCTL MMC FIFO Control Register Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 123 ...

  • Page 124

    ... Peripheral Information and Electrical Specifications assume testing over recommended operating conditions. (see Figure 5-25 and Figure 5-27) 1.3V, 1.2V MIN 4 2.5 4.5 2.5 Figure 5-24 1.3V, 1.2V MIN 0 0 6.5 6 Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com 1.1V 1.0V UNIT MAX MIN MAX MIN MAX 4 6 2.5 2 2.5 2.5 through Figure 5-27) 1.1V 1.0V UNIT MAX ...

  • Page 125

    ... D0 D1 Figure 5-26. MMC/SD Host Write Timing Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 13 13 Valid Valid END Valid END END End AM1808 125 ...

  • Page 126

    ... At CVDD = 1.2V, SATA Gen 2i (3.0 Gbps) and SATA Gen 1i (1.5 Gbps) are supported. • At CVDD = 1.1V, SATA Gen 1i (1.5 Gbps) only is supported. • At CVDD = 1.0V, SATA is not supported. 126 Peripheral Information and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com ...

  • Page 127

    ... Port Serial ATA Error Register Port Serial ATA Active Register Port Command Issue Register Port Serial ATA Notification Register Port DMA Control Register Port PHY Control Register Port PHY Status Register Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 127 ...

  • Page 128

    ... SATA_TXN SATA_TXP 10nF 10nF SATA_RXN SATA_RXP 10nF 10nF 10nF SATA_REG 0.1uF Table 5-43. SATA Supported Modes MIN MAX 1.5 Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com SATA Connector TX– TX+ RX– RX+ LVDS Oscillator CLK– CLK+ UNIT SUPPORTED 3.0 Gbps Yes Copyright © ...

  • Page 129

    ... SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 TYP MAX UNIT 6 Layers 3 Layers 0 Layers 0 Mils Mils 18 Mils 8 Mils Table 5-45 shows the routing TYP MAX UNIT 7000 Mils 2000 Mils 0 Stubs 100 Ohms 3 Vias (2) Table 5-46 TYP MAX UNIT 10 12 0603 10 Mils AM1808 (1) nF (1) (2) 129 ...

  • Page 130

    ... SATA_VSS Vss 130 Peripheral Information and Electrical Specifications MIN ( Configuration if SATA peripheral is not used Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com TYP MAX UNIT 375 MHz 50 ps pk- 700 ps Copyright © ...

  • Page 131

    ... Figure 5-29. McASP Block Diagram Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 Function Receive Master Clock Receive Bit Clock ft The McASP DOES NOT have a dedicated AMUTEIN pin ...

  • Page 132

    ... Left (even TDM time slot) channel status register (DIT mode) 1 Left (even TDM time slot) channel status register (DIT mode) 2 Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Table 5-51. Note that the AFIFO Write ...

  • Page 133

    ... Serializer control register 7 Serializer control register 8 Serializer control register 9 Serializer control register 10 Serializer control register 11 Serializer control register 12 Serializer control register 13 Serializer control register 14 Serializer control register 15 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 133 ...

  • Page 134

    ... Transmit buffer DMA port address. Cycles through transmit serializers, skipping over receive and inactive serializers. Starts at the lowest serializer at the beginning of each time slot. Writes to DMA port only if RBUSEL = 0 in RFMT. Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 135

    ... AHCLKR/X ext input (4) AHCLKR/X ext output AHCLKR/X int 11.5 (4) (5) AHCLKR/X ext AHCLKR/X int -1 AHCLKR/X ext input (4) (5) AHCLKR/X ext output Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 Figure 5-30 and (1) (2) 1.1V UNIT MAX MIN MAX (3) (3) 28 ...

  • Page 136

    ... AHCLKR/X ext input (4) AHCLKR/X ext output AHCLKR/X int (4) (5) AHCLKR/X ext AHCLKR/X int AHCLKR/X ext input (4) (5) AHCLKR/X ext output Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com (1) (2) 1.0V UNIT MIN MAX 35 ns 17 ...

  • Page 137

    ... ACLKR/X int ACLKR/X int ACLKR/X ext input ACLKR/X ext output ACLKR/X int ACLKR/X ext input ACLKR/X ext output ACLKR/X int ACLKR/X ext Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 (1) 1.3V, 1.2V 1.1V UNIT MIN MAX MIN MAX (2) (2) AH – ...

  • Page 138

    ... Peripheral Information and Electrical Specifications A30 A31 B0 B1 Figure 5-30. McASP Input Timings Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com 4 B30 B31 C31 Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 139

    ... SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 A30 A31 B0 B1 Figure 5-31. McASP Output Timings Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 B30 B31 C31 139 ...

  • Page 140

    ... Write FIFO Status Register RFIFOCTL Read FIFO Control Register RFIFOSTS Read FIFO Status Register McBSP FIFO Data Registers RBUF McBSP FIFO Receive Buffer XBUF McBSP FIFO Transmit Buffer Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 141

    ... CLKR int 14 CLKR ext 4 CLKR int 3 CLKR ext 3 CLKX int 14 CLKX ext 4 CLKX int 6 CLKX ext 3 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 (1) (see Figure 5-32) 1.1V UNIT MAX MIN MAX ( ...

  • Page 142

    ... CLKR int CLKR ext CLKR int CLKR ext CLKR int CLKR ext CLKR int CLKR ext CLKX int CLKX ext CLKX int CLKX ext Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com (1) (see Figure 5-32) 1.0V UNIT MIN MAX (2) ( 26.6 ( ...

  • Page 143

    ... CLKX int - 5 (7) (7) CLKX ext 14 (8) (8) FSX int -4 5 (8) (8) FSX ext -2 14.5 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 (1) (2) 1.1V UNIT MIN MAX (3) (4) ( ( ...

  • Page 144

    ... CLKR/X int CLKR/X int CLKR int CLKR ext CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext FSX int FSX ext Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com (1) (2) 1.0V UNIT MIN MAX 3 21.5 (3) (4) ( 26.6 (6) ( ...

  • Page 145

    ... CLKR int CLKR ext CLKR int CLKR ext CLKR int CLKR ext CLKX int CLKX ext CLKX int CLKX ext Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 (1) (see Figure 5-32) 1.1V MAX MIN MAX (2) (3) (2) ( (5) (6) ...

  • Page 146

    ... CLKX int - 6 (7) CLKX ext 16 (8) (8) FSX int -4 6.5 (8) (8) FSX ext -2 16.5 Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com (1) (2) 1.1V UNIT MIN MAX 1 (3) (4) ( (6) ( ...

  • Page 147

    ... Product Folder Link(s): AM1808 SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 (1) (2) 1.0V MIN MAX 1.5 23 (3) (4) ( 26.6 ( (7) ( (8) ( (9) ( (9) ( AM1808 UNIT 147 ...

  • Page 148

    ... Bit(n1 (A) Bit(n1) Figure 5-32. McBSP Timing 1.3V, 1.2V MIN MAX 4 4 1.3V, 1.2V MIN MAX Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com (n2) (n3) 13 (A) (n2) (n3) (B) Figure 5-33) 1.1V 1.0V MIN MAX MIN MAX 4 Figure 5-33) 1.1V 1.0V MIN MAX MIN MAX 5 ...

  • Page 149

    ... Copyright © 2010–2011, Texas Instruments Incorporated SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 16-Bit Shift Register 16-Bit Buffer Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 SPIx_SIMO SPIx_SOMI SPIx_ENA State GPIO SPIx_SCS Machine Control ...

  • Page 150

    ... Figure 5-35. Illustration of SPI Master-to-SPI Slave Connection 150 Peripheral Information and Electrical Specifications Optional − Slave Chip Select Optional Enable (Ready) Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com SPIx_SCS SPIx_ENA SPIx_CLK SPIx_SOMI SPIx_SIMO SLAVE SPI ...

  • Page 151

    ... SPIFMT2 Format Register 2 SPIFMT3 Format Register 3 INTVEC0 Interrupt Vector for SPI INT0 INTVEC1 Interrupt Vector for SPI INT1 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 DESCRIPTION AM1808 151 ...

  • Page 152

    ... SPI0_CLK falling Polarity = 0, Phase = 0, 4 from SPI0_CLK falling Polarity = 0, Phase = 1, 4 from SPI0_CLK rising Polarity = 1, Phase = 0, 4 from SPI0_CLK rising Polarity = 1, Phase = 1, 4 from SPI0_CLK falling Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Figure 5-36 (1) 1.1V 1.0V MIN MAX MIN MAX (2) (2) 30 256P 40 256P 0 ...

  • Page 153

    ... SPI0_CLK falling Polarity = 0, Phase = 1, 4 from SPI0_CLK rising Polarity = 1, Phase = 0, 4 from SPI0_CLK rising Polarity = 1, Phase = 1, 4 from SPI0_CLK falling Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 (1) 1.1V 1.0V UNIT MIN MAX MIN MAX (2) ( ...

  • Page 154

    ... SPI0_CLK rising (Table 5-68). 1.3V, 1.2V MIN MAX Polarity = 0, Phase = 0, 2P-1 to SPI0_CLK rising Polarity = 0, Phase = 1, 0.5M+2P-1 to SPI0_CLK rising Polarity = 1, Phase = 0, 2P-1 to SPI0_CLK falling Polarity = 1, Phase = 1, 0.5M+2P-1 to SPI0_CLK falling (Table 5-68). Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com (1) (2) (3) 1.1V 1.0V UNIT MIN MAX MIN MAX 3P+5 3P+6 0.5M+3P+5 0.5M+3P+6 3P+5 3P+6 0.5M+3P+5 0.5M+3P+6 0.5M+P+5 0.5M+P+6 P+5 P+6 ...

  • Page 155

    ... SPI0_CLK rising C2TDELAY+P (Table 5-69). Submit Documentation Feedback Product Folder Link(s): AM1808 SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 (1)(2)(3) (continued) 1.1V 1.0V MAX MIN MAX MIN 0.5M+P-2 0.5M+P-3 P-2 P-3 0.5M+P-2 0.5M+P-3 P-2 P-3 (1) (2) (3) 1.1V 1.0V MIN MAX MIN MAX 0.5M+P+5 0.5M+P+6 P+5 P+6 0.5M+P+5 0.5M+P+6 P+5 P+6 0.5M+P-2 0.5M+P-3 P-2 P-3 0.5M+P-2 0.5M+P-3 P-2 P-3 C2TDELAY+P C2TDELAY+P Peripheral Information and Electrical Specifications AM1808 UNIT MAX ns UNIT 155 ...

  • Page 156

    ... SPI0_CLK rising Polarity = 0, Phase = 1, 0.5M+3P+5 to SPI0_CLK rising Polarity = 1, Phase = 0, 3P+5 to SPI0_CLK falling Polarity = 1, Phase = 1, 0.5M+3P+5 to SPI0_CLK falling 1.3V, 1.2V MIN MAX 1.5P-3 2.5P+17.5 1.5P-3 – 0.5M+1.5P-3 – 0.5M+2.5P+17.5 – 0.5M+1.5P-3 1.5P-3 2.5P+17.5 1.5P-3 – 0.5M+1.5P-3 – 0.5+2.5P+17.5 – 0.5M+1.5P-3 (Table 5-69). Submit Documentation Feedback Product Folder Link(s): AM1808 (1)(2)(3) (continued) 1.1V 1.0V MIN MAX MIN MAX 2P-2 2P-3 0.5M+2P-2 0.5M+2P-3 2P-2 2P-3 0.5M+2P-2 0.5M+2P-3 3P+5 3P+6 0.5M+3P+5 0.5M+3P+6 3P+5 3P+6 0.5M+3P+5 0.5M+3P+6 (1) (2) (3) 1.1V 1.0V MIN MAX ...

  • Page 157

    ... Submit Documentation Feedback Product Folder Link(s): AM1808 SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 (1) (2) (3) 1.1V 1.0V MIN MAX MIN MAX 1.5 0.5M+P+4 0.5M+P+5 P+4 P+5 0.5M+P+4 0.5M+P+5 P+4 P+5 P+20 P+27 P+20 P+27 (1) (2) (3) 1.1V 1.0V MIN MAX MIN MAX 1.5 0.5M+P+4 0.5M+P+5 P+4 P+5 0.5M+P+4 0.5M+P+5 P+4 P+5 P+20 P+27 P+20 P+ Peripheral Information and Electrical Specifications AM1808 UNIT UNIT 157 ...

  • Page 158

    ... MIN MAX Polarity = 0, Phase = 0, 2.5P+17.5 from SPI0_CLK falling Polarity = 0, Phase = 1, 2.5P+17.5 from SPI0_CLK rising Polarity = 1, Phase = 0, 2.5P+17.5 from SPI0_CLK rising Polarity = 1, Phase = 1, 2.5P+17.5 from SPI0_CLK falling Submit Documentation Feedback Product Folder Link(s): AM1808 (1)(2)(3) (continued) 1.1V 1.0V MIN MAX MIN MAX 2.5P+20 2.5P+27 2.5P+20 2.5P+27 2.5P+20 2.5P+27 2.5P+20 2.5P+27 Copyright © 2010–2011, Texas Instruments Incorporated www ...

  • Page 159

    ... SPI1_CLK falling Polarity = 0, Phase = 1, 4 from SPI1_CLK rising Polarity = 1, Phase = 0, 4 from SPI1_CLK rising Polarity = 1, Phase = 1, 4 from SPI1_CLK falling Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 (1) 1.1V 1.0V UNIT MIN MAX MIN MAX (2) (2) 30 256P 40 ...

  • Page 160

    ... SPI1_CLK falling Polarity = 0, Phase = 1, 4 from SPI1_CLK rising Polarity = 1, Phase = 0, 4 from SPI1_CLK rising Polarity = 1, Phase = 1, 4 from SPI1_CLK falling Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com (1) 1.1V 1.0V UNIT MIN MAX MIN MAX (2) (2) 50 ...

  • Page 161

    ... Polarity = 1, Phase = 1, 0.5M+2P-1 to SPI1_CLK falling Polarity = 0, Phase = 0, 0.5M+P-1 from SPI1_CLK falling Polarity = 0, Phase = 1, P-1 Polarity = 1, Phase = 0, 0.5M+P-1 from SPI1_CLK rising Polarity = 1, Phase = 1, P-1 from SPI1_CLK rising (Table Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 (2) (3) 1.1V 1.0V MIN MAX MIN MAX 3P+5 3P+6 0.5M+3P+5 0.5M+3P+6 3P+5 3P+6 0.5M+3P+5 0.5M+3P+6 0.5M+P+5 0.5M+P+6 P+5 P+6 0 ...

  • Page 162

    ... SPI1_CLK rising Polarity = 1, Phase = 1, P-1 from SPI1_CLK rising C2TDELAY+P Polarity = 0, Phase = 0, 2P-1 to SPI1_CLK rising Polarity = 0, Phase = 1, 0.5M+2P-1 to SPI1_CLK rising Polarity = 1, Phase = 0, 2P-1 to SPI1_CLK falling Polarity = 1, Phase = 1, 0.5M+2P-1 to SPI1_CLK falling (Table 5-77). Submit Documentation Feedback Product Folder Link(s): AM1808 (2) (3) 1.1V 1.0V MIN MAX MIN MAX 0.5M+P+5 0.5M+P+6 P+5 P+6 0.5M+P+5 0.5M+P+6 P+5 P+6 0.5M+P-5 0.5M+P-6 P-5 P-6 0.5M+P-5 ...

  • Page 163

    ... SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 (2)(3) (continued) 1.1V 1.0V MIN MAX MIN MAX 3P+5 3P+6 0.5M+3P+5 0.5M+3P+6 3P+5 3P+6 0.5M+3P+5 0.5M+3P+6 (2) (3) 1.1V 1.0V MIN MAX MIN 1.5P-10 2.5P+17 1.5P-12 2.5P+19 –0.5M+1.5P-10 –0.5M+2.5P+17 –0.5M+1.5P-12 –0.5M+2.5P+19 1.5P-10 2.5P+17 1.5P-12 2.5P+19 –0.5M+1.5P-10 –0.5M+2.5P+17 –0.5M+1.5P-12 –0.5M+2.5P+19 (2) (3) 1.1V 1.0V MAX MIN MAX MIN P+1.5 P+1.5 Peripheral Information and Electrical Specifications AM1808 UNIT ns UNIT MAX ns UNIT MAX ns 163 ...

  • Page 164

    ... SPI1 Slave Timings, 4-Pin Chip Select Option 1.3V, 1.2V MIN MAX Polarity = 0, Phase = 0, 0.5M+P+4 from SPI1_CLK falling Polarity = 0, Phase = 1, P+4 from SPI1_CLK falling Polarity = 1, Phase = 0, 0.5M+P+4 from SPI1_CLK rising Polarity = 1, Phase = 1, P+4 from SPI1_CLK rising P+15 P+15 Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com (2)(3) (continued) 1.1V 1.0V UNIT MIN MAX MIN MAX 0.5M+P+5 0.5M+P+6 P+5 P+6 ns 0.5M+P+5 0.5M+P+6 P+5 P+6 ...

  • Page 165

    ... SPI1_CLK rising P+15 P+15 15 Polarity = 0, Phase = 0, 2.5P+15 from SPI1_CLK falling Polarity = 0, Phase = 1, 2.5P+15 from SPI1_CLK rising Polarity = 1, Phase = 0, 2.5P+15 from SPI1_CLK rising Polarity = 1, Phase = 1, 2.5P+15 from SPI1_CLK falling (Table 5-77). Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 (2) (3) 1.1V 1.0V UNIT MIN MAX MIN MAX P+1.5 P+1.5 0.5M+P+5 0.5M+P+6 P+5 P+6 0.5M+P+5 0.5M+P+6 P+5 P+6 P+17 P+19 P+17 ...

  • Page 166

    ... MI(0) MI( MO(0) MO( MI(0) MI( MO(0) MO( MI(0) MI(1) Figure 5-36. SPI Timings—Master Mode Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com MASTER MODE POLARITY = 0 PHASE = 0 6 MO(n−1) MO(n) MI(n−1) MI(n) MASTER MODE POLARITY = 0 PHASE = 1 MO(n−1) MO(n) MI(n−1) MI(n) MASTER MODE POLARITY = 1 PHASE = 0 6 MO(n−1) MO(n) MI(n−1) MI(n) MASTER MODE POLARITY = 1 PHASE = 1 MO(n− ...

  • Page 167

    ... SI(0) SI(1) 13 SO(0) SO( SI(0) SI( SO(0) SO(1) Figure 5-37. SPI Timings—Slave Mode Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 SLAVE MODE POLARITY = 0 PHASE = 0 SI(n−1) SI(n) 14 SO(n−1) SO(n) SLAVE MODE POLARITY = 0 PHASE = 1 SI(n−1) SI(n) SO(n−1) SO(n) SLAVE MODE POLARITY = 1 PHASE = 0 SI(n−1) SI(n) 14 SO(n−1) SO(n) SLAVE MODE POLARITY = 1 PHASE = 1 SI(n− ...

  • Page 168

    ... MASTER MODE 4 PIN WITH CHIP SELECT 19 MO(0) MO(n−1) MO(1) MI(0) MI(1) MI(n−1) MASTER MODE 5 PIN 22 MO(1) 23 MO(0) MO(n−1) MI(0) MI(1) MI(n− DESELECTED IS PROGRAMMABLE EITHER HIGH OR 3−STATE (REQUIRES EXTERNAL PULLUP) Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com 18 MO(n) MI(n) 20 MO(n) MI( MO(n) MI(n) (A) DESEL Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 169

    ... SLAVE MODE 4 PIN WITH CHIP SELECT 25 27 SO(n−1) SO(0) SO(1) SI(0) SI(1) SI(n−1) SI(n) SLAVE MODE 5 PIN SO(1) SO(0) SO(n−1) 29 SI(0) SI(1) SI(n−1) SI(n) (A) A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR 3−STATE (REQUIRES EXTERNAL PULLUP) Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 24 SO( SO( SO(n) (A) DESEL 169 ...

  • Page 170

    ... Pin Function I2CPDOUT Register Pin Direction I2CPDSET Register Pin Data In I2CPDCLR Register Figure 5-40. I2C Module Block Diagram Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Own Address Register Slave Address Register Mode Register Extended Mode Register Data Count Peripheral Register ...

  • Page 171

    ... I2C Pin Direction Register ICPDIN I2C Pin Data In Register ICPDOUT I2C Pin Data Out Register ICPDSET I2C Pin Data Set Register ICPDCLR I2C Pin Data Clear Register Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 171 ...

  • Page 172

    ... N/A Standard Mode MIN 10 4.7 4 4.7 4 250 0 4.7 4 Table 5-86. Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Figure 5-41 and Fast Mode UNIT MIN MAX 2.5 μs 0.6 μs 0.6 μs 1.3 μs 0.6 μs 100 ns 0 0.9 μs 1.3 μ ...

  • Page 173

    ... SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 Repeated Start Figure 5-41. I2C Receive Timings Repeated Start Figure 5-42. I2C Transmit Timings Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 Stop Stop 173 ...

  • Page 174

    ... Divisor MSB Latch 0x01D0 D028 REVID1 Revision Identification Register 1 0x01D0 D030 PWREMU_MGMT Power and Emulation Management Register 0x01D0 D034 MDR Mode Definition Register Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com REGISTER DESCRIPTION Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 175

    ... SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 PARAMETER (see Figure 5-43) PARAMETER 3 2 Start Bit Data Bits 5 4 Start Bit Data Bits Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 (1) (see Figure 5-43) 1.3V, 1.2V, 1.1V, 1.0V UNIT MIN MAX 0.96U 1.05U ns 0.96U 1.05U ns 1.3V, 1.2V, 1.1V, 1.0V UNIT MIN MAX (2) (3) ...

  • Page 176

    ... Function Address Register Power Management Register Interrupt Register for Endpoint 0 plus Transmit Endpoints Interrupt Register for Receive Endpoints Interrupt enable register for INTRTX Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 177

    ... Transmit and Receive FIFO Register for Endpoint 2 Transmit and Receive FIFO Register for Endpoint 3 Transmit and Receive FIFO Register for Endpoint 4 OTG Device Control Device Control Register Dynamic FIFO Control Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 177 ...

  • Page 178

    ... Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 179

    ... Control Status Register for Host Receive Endpoint (host mode) Number of Bytes in Host Receive endpoint FIFO Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint. Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 179 ...

  • Page 180

    ... Transmit Channel 1 Global Configuration Register Receive Channel 1 Global Configuration Register Receive Channel 1 Host Packet Configuration Register A Receive Channel 1 Host Packet Configuration Register B Transmit Channel 2 Global Configuration Register Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 181

    ... Queue Manager Queue 1 Status Register A Queue Manager Queue 1 Status Register B Queue Manager Queue 1 Status Register Queue Manager Queue 63 Status Register A Queue Manager Queue 63 Status Register B Queue Manager Queue 63 Status Register C Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 181 ...

  • Page 182

    ... High Speed per − Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com 1.3V, 1.2V, 1.1V, 1.0V FULL SPEED HIGH SPEED 12 Mbps 480 Mbps MAX MIN MAX MIN MAX 300 4 20 0.5 300 4 20 0.5 – ...

  • Page 183

    ... HC Root Hub Status Register HC Port 1 Status and Control Register HC Port 2 Status and Control Register (1) (1) (2) (1) 1.3 (3) -25 (4) = 50pF L Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 REGISTER DESCRIPTION (1) (1) (1) (1) (1) (1) (1) (2) (3) 1.3V,1.2V, 1.1V, 1.0V LOW SPEED FULL SPEED MIN MAX MAX ...

  • Page 184

    ... Receive Channel 3 Flow Control Threshold Register Receive Channel 4 Flow Control Threshold Register Receive Channel 5 Flow Control Threshold Register Receive Channel 6 Flow Control Threshold Register Receive Channel 7 Flow Control Threshold Register Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com ...

  • Page 185

    ... Receive Channel 7 DMA Head Descriptor Pointer Register Transmit Channel 0 Completion Pointer Register Transmit Channel 1 Completion Pointer Register Transmit Channel 2 Completion Pointer Register Transmit Channel 3 Completion Pointer Register Transmit Channel 4 Completion Pointer Register Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 185 ...

  • Page 186

    ... Transmit Late Collision Frames Register Transmit Underrun Error Register Transmit Carrier Sense Errors Register TXOCTETS Transmit Octet Frames Register FRAME64 Transmit and Receive 64 Octet Frames Register Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com REGISTER DESCRIPTION Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 187

    ... EMAC Control Module Interrupt Core 1 Transmit Interrupts Per Millisecond Register EMAC Control Module Interrupt Core 2 Receive Interrupts Per Millisecond Register EMAC Control Module Interrupt Core 2 Transmit Interrupts Per Millisecond Register Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 REGISTER DESCRIPTION 187 ...

  • Page 188

    ... Figure 5-46. MII_TXCLK Timing (EMAC - Transmit) 188 Peripheral Information and Electrical Specifications Table 5-97. EMAC Control Module RAM DESCRIPTION EMAC Local Buffer Descriptor Memory Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com Figure 5-45) 1.3V, 1.2V, 1.1V 1.0V 10 Mbps 100 Mbps 10 Mbps MIN MAX MIN ...

  • Page 189

    ... Copyright © 2010–2011, Texas Instruments Incorporated SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 PARAMETER 1 (1) 10/100 Mbit/s (see Figure 5-48) PARAMETER 1 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 (1) (see Figure 5-47) 1.3V, 1.2V, 1.1V, 1.0V UNIT MIN MAX 1.3V, 1.2V, 1 ...

  • Page 190

    ... RMII_MHz_50_CLK 5 RMII_TXEN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRS_DV RMII_RXER 190 Peripheral Information and Electrical Specifications PARAMETER (2) PARAMETER Figure 5-49. RMII Timing Diagram Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com (1) 1.3V, 1.2V, 1.1V MIN TYP MAX (1) 1.3V, 1.2V, 1.1V MIN TYP MAX 2 ...

  • Page 191

    ... MDIO User Access Register 0 MDIO User PHY Select Register 0 MDIO User Access Register 1 MDIO User PHY Select Register 1 – Reserved Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 REGISTER NAME AM1808 191 ...

  • Page 192

    ... Peripheral Information and Electrical Specifications Figure 5- Figure 5-50. MDIO Input Timing (see Figure 5-51 Figure 5-51. MDIO Output Timing Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com and Figure 5-51) 1.3V, 1.2V, 1.1V 1.0V UNIT MIN MAX MIN MAX 400 400 ns 180 ...

  • Page 193

    ... LCD DMA Frame Buffer 0 Base Address Register LCD DMA Frame Buffer 0 Ceiling Address Register LCD DMA Frame Buffer 1 Base Address Register LCD DMA Frame Buffer 1 Ceiling Address Register Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 SPRAB93. 193 ...

  • Page 194

    ... Figure 5-52. Character Display HD44780 Write 194 Peripheral Information and Electrical Specifications PARAMETER PARAMETER CS_DELAY R_SU ( 31) W_HOLD ( Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com 1.3V, 1.2V, 1.0V 1.1V MIN MAX MIN MAX 1.3V, 1.2V, 1.0V 1.1V MIN MAX MIN ...

  • Page 195

    ... SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 R_HOLD CS_DELAY (1–5) (0− Read Data 13 12 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 W_HOLD (1–15) W_SU W_STROBE CS_DELAY (0–31) (1–63) (0 − Write Instruction Data[7: ...

  • Page 196

    ... Figure 5-54. Micro-Interface Graphic Display 6800 Write 196 Peripheral Information and Electrical Specifications W_HOLD (1−15) W_STROBE CS_DELAY (1−63) (0− Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com W_HOLD (1−15) W_SU W_STROBE CS_DELAY (0−31) (1−63) (0− Write Data Data[15: ...

  • Page 197

    ... SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 W_HOLD (1−15) W_STROBE CS_DELAY (1−63) (0− Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 R_SU (0−31) R_STROBE R_HOLD CS_DELAY (1−63 (1−15) (0− Data[15:0] Read Data ...

  • Page 198

    ... Figure 5-56. Micro-Interface Graphic Display 6800 Status 198 Peripheral Information and Electrical Specifications R_SU (0−31) CS_DELAY (1−15) (0− Read 7 Data 13 12 Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com R_STROBE R_HOLD CS_DELAY (1−63) (1−15) (0−3) Clock Data[15:0] Read Status 7 6 CS0 ...

  • Page 199

    ... SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 W_HOLD (1−15) W_STROBE CS_DELAY (1−63) (0− Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1808 AM1808 W_HOLD (1−15) W_SU W_STROBE CS_DELAY (0−31) (1−63) (0 − DATA[15:0] Write Data ...

  • Page 200

    ... Figure 5-58. Micro-Interface Graphic Display 8080 Read 200 Peripheral Information and Electrical Specifications W_HOLD R_SU (1−15) (0−31) W_STROBE CS_DELAY (1−63) (0− Submit Documentation Feedback Product Folder Link(s): AM1808 www.ti.com R_STROBE R_HOLD CS_DELAY (1−63) (1−15) (0−3) Clock Data[15:0] Read 6 7 Data ...