D
2-V to 5.5-V V
Operation
CC
D
Max t
of 6.5 ns at 5 V
pd
D
Typical V
(Output Ground Bounce)
OLP
<0.8 V at V
= 3.3 V, T
= 25°C
CC
A
D
Typical V
(Output V
Undershoot)
OHV
OH
>2.3 V at V
= 3.3 V, T
= 25°C
CC
A
D
Support Mixed-Mode Voltage Operation on
All Ports
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
These quadruple bus buffer gates are designed
for 2-V to 5.5-V V
operation.
CC
The ’LV126A devices feature independent line
drivers with 3-state outputs. Each output is
disabled when the associated output-enable (OE)
input is low.
To ensure the high-impedance state during power
up or power down, OE should be tied to GND
through a pulldown resistor; the minimum value of
the resistor is determined by the current-sourcing
capability of the driver.
T A
SOIC − D
SOIC − D
SOP − NS
SSOP − DB
−40°C to 85°C
−40°C to 85°C
TSSOP − PW
TSSOP − PW
TVSOP − DGV
CDIP − J
−55°C to 125°C
−55 C to 125 C
CFP − W
LCCC − FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LV126A . . . J OR W PACKAGE
SN74LV126A . . . D, DB, DGV, NS, OR PW PACKAGE
1OE
2OE
GND
SN54LV126A . . . FK PACKAGE
1Y
NC
2OE
NC
2A
NC − No internal connection
ORDERING INFORMATION
ORDERABLE
PACKAGE †
PART NUMBER
Tube of 50
SN74LV126AD
Reel of 2500
SN74LV126ADR
Reel of 2000
SN74LV126ANSR
Reel of 2000
SN74LV126ADBR
Tube of 90
SN74LV126APW
Reel of 2000
SN74LV126APWR
Reel of 250
SN74LV126APWT
Reel of 2000
SN74LV126ADGVR
Tube of 25
SNJ54LV126AJ
Tube of 150
SNJ54LV126AW
Tube of 55
SNJ54LV126AFK
•
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SCES131H − MARCH 1998 − REVISED APRIL 2005
(TOP VIEW)
V
1
14
CC
1A
4OE
2
13
1Y
4A
3
12
4
11
4Y
2A
5
10
3OE
6
9
2Y
3A
7
8
3Y
(TOP VIEW)
3 2 1 20 19
4A
4
18
NC
5
17
16
4Y
6
15
7
NC
14
8
3OE
9 10 11 12 13
TOP-SIDE
MARKING
LV126A
LV126A
74LV126A
LV126A
LV126A
LV126A
LV126A
SNJ54LV126AJ
SNJ54LV126AW
SNJ54LV126AFK
Copyright 2005, Texas Instruments Incorporated
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