IR3502BMPBF International Rectifier, IR3502BMPBF Datasheet
IR3502BMPBF
Specifications of IR3502BMPBF
Related parts for IR3502BMPBF
IR3502BMPBF Summary of contents
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... Remote sense amplifier with true converter voltage sensing Small thermally enhanced 32L 5mm x 5mm MLPQ package RoHS Compliant ORDERING INFORMATION Device IR3502BMTRPBF * IR3502BMPBF Samples only Page XPHASE3 TM Phase IC provides a full featured and flexible way Package Order Quantity ...
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APPLICATION CIRCUIT +12V PGOOD RMON IOUT CMON RMON1 VOSEN- VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 ENABLE VRHOT RHOTSET1 CHOTSET IR3502B + FAST VDAC - IVDAC IROSC Page CVCCL RVCCLDRV 1 24 VID7 GND ROSC ...
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ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the ...
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ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over: 8V≤Vin≤16V, VCCL = 6.8V±3.4%, -0.3V ≤ VOSEN- ≤ 0.3V ≤ T ≤ 100 C, 7.75KΩ ≤ PARAMETER VDAC Reference System Set-Point Accuracy Source & Sink ...
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PARAMETER Source Current Sink Resistance Unity Gain Bandwidth Input Filter Time Constant Max Output Voltage Soft Start and Delay Start Delay (TD1) Soft Start Time (TD2) VID Sample Delay (TD3) PGOOD Delay (TD4 + TD5) OC Delay Time SS/DEL to ...
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PARAMETER Minimum Voltage Open Voltage Loop Detection Threshold Open Voltage Loop Detection Delay Enable Input VR 11 Threshold Voltage VR 11 Threshold Voltage VR 11 Hysteresis Bias Current Blanking Time Over-Current Comparator Input Offset Voltage Input Filter Time Constant Over-Current ...
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PARAMETER PGOOD Output Output Voltage Leakage Current Under Voltage Threshold-VO decreasing Under Voltage Threshold-VO increasing Under Voltage Threshold Hysteresis VCCL_DRV Activation Threshold I(PG)=4mA, V(PG)<300mV, V(VCCL)=0 Open Sense Line Detection Sense Line Detection Active Comparator Threshold Voltage Sense Line Detection Active ...
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PIN DESCRIPTION PIN# PIN SYMBOL 1-8 VID7-0 Inputs to VID Converter. 9 ENABLE Enable input. A logic low applied to this pin puts the IC into fault mode. Do not float this pin as the logic state ...
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SYSTEM THEORY OF OPERATION System Description The system consists of one control IC and a scalable array of phase converters, each requiring one phase IC. The control IC communicates with the phase ICs using three digital buses, i.e., CLOCK, PHSIN, ...
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PHSIN of the first phase IC, and PHSOUT of the first phase IC is connected to PHSIN of the second phase IC, etc. The PHSOUT of the last phase IC is connected back to ...
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PHASE IC CLOCK PULSE EAIN PWMRMP VDAC GATEH GATEL STEADY-STATE OPERATION TM Body Braking In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; The ...
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R was used. The mismatch of the time constants does not affect the measurement of L inductor DC current, but affects the AC component of the inductor current. Figure 6 Inductor Current Sensing and Current ...
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IR3502B THEORY OF OPERATION Block Diagram The block diagram of the IR3502B is shown in Figure 7. VID Control The control IC allows the processor voltage to be set by a parallel eight bit digital VID bus. The VID codes ...
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ENABLE COMPARATOR ENABLE - 250nS BLANKING + INTEL DELAY 850mV COMPARATOR 800mV + VCCLDRV - 80mV VCCL REGULATOR 120mV AMPLIFIER VCCL + 4.0V - 6.8V VCCL OUTPUT COMPARATOR 6.45V + VCCL UVLO 5.45V - SS/DEL VID7 VID7 VID INPUT VID7 ...
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TABLE 1 VR11 VID TABLE (PART1) Hex (VID7:VID0) Dec (VID7:VID0) 00 00000000 01 00000001 02 00000010 03 00000011 04 00000100 05 00000101 06 00000110 07 00000111 08 00001000 09 00001001 0A 00001010 0B 00001011 0C 00001100 0D 00001101 0E 00001110 ...
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TABLE 1 VR11 VID TABLE (PART 2) Hex (VID7:VID0) Dec (VID7:VID0) 80 10000000 81 10000001 82 10000010 83 10000011 84 10000100 85 10000101 86 10000110 87 10000111 88 10001000 89 10001001 8A 10001010 8B 10001011 8C 10001100 8D 10001101 8E ...
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Control IC VDAC 100k VDAC Buffer Thermal + Comp Amplifier - Remote Sense Amplifier Figure 8 Adaptive voltage positioning with thermal compensation. Start-up Sequence The IR3502B has a programmable soft-start function to limit the surge current during the converter start-up. ...
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VCC (12V) ENABLE 1.1V VDAC 4.0V 3.92V 3V 1.4V SS/DEL EAOUT VOUT VRRDY START DELAY (TD1) Figure 9 Start-up sequence of converter with boot voltage Current Monitor (IMON) The control IC generates a current monitor signal IMON using the VDRP ...
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Constant Over-Current Control during Soft Start The over current limit is fixed by 1.17V above the VDAC. If the VDRP pin voltage, which is proportional to the average current plus VDAC voltage, exceeds (VDAC+1.17V) during soft start, the constant over-current ...
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If an over-current condition is again encountered during the soft start cycle, the over-current action will repeat and the converter will be in hiccup mode. Linear Regulator Output (VCCL) The IR3502B has a built-in linear regulator controller, ...
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OUTPUT OVP VOLTAGE THRESHOLD (VO) VCCL-800 mV IIN (ISHARE) GATEH (PHASE IC) GATEL (PHASE IC) FAULT LATCH ERROR AMPLIFIER VDAC OUTPUT (EAOUT) Figure 13 Over-voltage protection during normal operation 12V VCC VCCL+0.7V VCCL+0.7V VCCLDRV 1.8V OUTPUT VOLTAGE (VOSEN+) VCCL UVLO ...
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VCCL+0.7V VCC VCCL+0.7V VCCLDRV 1.8V OUTPUT VOLTAGE (VOSEN+) 1.73V VCCL UVLO ROSC/OVP 1.6V Figure 15 Over-voltage protection with pre-charging converter output Vo > 1.73V 12V VCC VCCL+0.7V VCCL+0.7V VCCLDRV OUTPUT 1.73V VOLTAGE (VOSEN+) VID + 0.13V VCCL UVLO VCCL ...
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In the event of a high side MOSFET short before power up, the OVP flag is activated with as little supply voltage as possible, as shown in Figure 14. The VOSEN+ pin is compared against a fixed voltage of 1.73V ...
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A high level at the PGOOD pin indicates that the converter is in operation and has no fault. The PGOOD stays high as long as the output voltage is within 300 mV of the programmed VID. During start-up, ...
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Phase Number Determination After a daisy chain pulse is started, the IR3502B checks the timing of the input pulse at PHSIN pin to determine the phase number. This information is used to have symmetrical phase delay between phase switching without ...
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DESIGN PROCEDURES - IR3502B AND IR3507 CHIPSET IR3502B EXTERNAL COMPONENTS Oscillator Resistor Rosc The oscillator of IR3502B generates square-wave pulses to synchronize the phase ICs. The switching frequency of the each phase converter equals the PHSOUT frequency, which is set ...
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C SS The soft start delay time (TD1) and VR ready delay time (TD3) are determined by (8) to (9) respectively Once C is chosen, the minimum over-current fault latch delay time SS/DEL t OCDEL VDAC Slew Rate ...
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RTHERM Droop Resistor The inductor DC resistance is utilized to sense the inductor current. The copper wire of inductor has a constant temperature coefficient of 3850 ppm/°C, and therefore the maximum inductor DCR can be calculated from ...
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Thermistor R and Over Temperature Setting Resistors R HOTSET3 The threshold voltage of VRHOT comparator is fixed at 1.6V, and a negative temperature coefficient (NTC) thermistor R is required to sense the temperature of the power stage pre-select ...
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DESIGN EXAMPLE – HIGH FREQUENCY CONVERTER (FIG. 20) SPECIFICATIONS Input Voltage DAC Voltage: V =1.2 V DAC No Load Output Voltage Offset: V Continuous Output Current: I OTDC Maximum DC Output Current: I OMAX Current Report ...
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DEL DAC CHG The VR ready delay time is ...
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Droop Resistor Based on the above calculation R Pre-select R =1 kΩ and using find out R . DRP R DRP Over Current Threshold The OCP is fixed at 1.17 V above the VDAC voltage. Therefore, it ...
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IR3502 Frequency vs. ROSC Resistor 200 300 400 500 600 700 Figure 18: Frequency variation with ROSC. 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 0.000 0.020 ...
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LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. Dedicate at least one middle layer for a ground plane LGND. ...
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PCB Metal and Component Placement Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to prevent shorting. Lead land length should be equal to maximum part ...
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Solder Resist The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non ...
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Stencil Design The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the ...
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PACKAGE INFORMATION 32L MLPQ ( Body) – θ IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 Visit us at www.irf.com for sales contact information. www.irf.com Page ...