FSQ0565RQ Fairchild Semiconductor, FSQ0565RQ Datasheet - Page 15

• Manufacturer Part Number: FSQ0565RQ
• Description: A Quasi-Resonant Converter (QRC) generally shows lower EMI and higher power conversion efficiency than a conventional hard-switched converter with a fixed switching frequency
• Manufacturer: Fairchild Semiconductor

FSQ0565RS/RQ Rev. 1.0.3
© 2008 Fairchild Semiconductor Corporation
FSQ-series uses V
output voltage. If V
activated, resulting in the termination of the switching
operation. To avoid undesired activation of OVP during
normal operation, V
4.4.2
FSQ0565RQ: If the secondary-side feedback circuit
malfunctions or a solder defect causes an opening in the
feedback path, the current through the opto-coupler
transistor becomes almost zero. V
similar manner to the overload situation, forcing the
preset maximum current to be supplied to the SMPS
until the overload protection triggers. Because more
energy than required is provided to the output, the output
voltage may exceed the rated voltage before the
overload protection triggers, resulting in the breakdown
of the devices in the secondary side. To prevent this
situation, an OVP circuit is employed. In general, the
peak voltage of the sync signal is proportional to the
output voltage and the FSQ-series uses a sync signal
instead of directly monitoring the output voltage. If the
sync signal exceeds 8V, an OVP is triggered, shutting
down the SMPS. To avoid undesired triggering of OVP
during normal operation, two points are considered, as
depicted in Figure 33. The peak voltage of the sync
signal should be designed below 6V and the spike of the
SYNC pin must be as low as possible to avoid getting
longer than t
shown at V
4.5 Thermal Shutdown with Hysteresis (TSD): The
SenseFET and the control IC are built in one package.
This enables the control IC to detect the abnormally high
temperature of the SenseFET. If the temperature
V
V
Vcc_coil
sync
Figure 33. OVP Triggering of FSQ0565RQ
&V
Sync
CC
CC
OVP
Improper OVP triggering
V
t
winding coil.
OVP
CC
Over-Voltage
by decreasing the leakage inductance
CC
CC
CC
Absolue max V
instead of directly monitoring the
should be designed below 19V.
V
V
exceeds 19V, an OVP circuit is
V
OVP
SH2
V
Vcc_coil
CLAMP
(4.8V)
(8V)
CC
Protection
(20V)
FB
climbs up in a
FSQ0565RQ Rev.00
V
DC
t
OVP
(OVP)
N
N
pri
Vcc
of
15
exceeds approximately 140°C, the thermal shutdown
triggers IC shutdown. The IC resumes operation when
the junction temperature decreases 60°C from TSD
temperature and V
5. Soft-Start: The FPS has an internal soft-start circuit
that increases PWM comparator inverting input voltage
with the SenseFET current slowly after it starts. The
typical soft-start time is 17.5ms. The pulse width to the
power switching device is progressively increased to
establish the correct working conditions for transformers,
inductors, and capacitors. The voltage on the output
capacitors is progressively increased with the intention of
smoothly establishing the required output voltage. This
mode helps prevent transformer saturation and reduces
stress on the secondary diode during startup.
6. Burst Operation: To minimize power dissipation in
standby mode, the FPS enters burst-mode operation. As
the load decreases, the feedback voltage decreases. As
shown in Figure 34, the device automatically enters
burst-mode when the feedback voltage drops below
V
output voltages start to drop at a rate dependent on
standby current load. This causes the feedback voltage
to rise. Once it passes V
resumes. The feedback voltage then falls and the
process repeats. Burst-mode operation alternately
enables and disables switching of the power SenseFET,
thereby reducing switching loss in standby mode.
BURL
0.55V
0.35V
Vo
V
V
I
V
DS
FB
DS
set
O
Figure 34. Waveforms of Burst Operation
(350mV). At this point, switching stops and the
FSQ0565 Rev. 00
t1
CC
Switching
reaches startup voltage (V
disabled
BURH
t2 t3
Switching
disabled
(550mV), switching
www.fairchildsemi.com
t4
start
time
).