FAN5069 Fairchild Semiconductor, FAN5069 Datasheet
FAN5069
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FAN5069 Summary of contents
Page 1
... Current limit for PWM is also programmable. The PWM regulator employs a summing-current-mode control with external compensation to achieve fast load transient response and provide design optimization. FAN5069 is offered in both industrial temperature grade (-40°C to +85°C) as well as commercial temperature grade (-10°C to +85°C). Package ...
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... Typical Application R VCC +12V + PWM OUT Q3 R7 LDO OUT FBLDO C8 R6 © 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5 VCC FAN5069 ILIM 3 10 PWM R( AGND GLDO 6 16 ULDO CONTROL 1 5 Figure 1. Typical Application Diagram ...
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... VCC. Provides bias power to the IC and the drive voltage for LDRV. Bypass with a ceramic capacitor as close to this pin as possible. This pin has a shunt regulator which draws current when the input voltage is above 5.6V. 16 GLDO Gate Drive for the LDO. Turned off (low) until SS is greater than 2.2V. © 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5 FBLDO 1 GLDO 16 R ...
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... Recommended Operating Conditions Symbol Parameter V Supply Voltage CC T Ambient Temperature A T Junction Temperature J © 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5 (1) Parameter Continuous Transient (t < 50nS, F < 500kHz) HBM CDM Parameter = 25° strong function of PCB material, board thickness, thickness and JA ...
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... Gate Drive R HDRV Pull-up Resistor HUP R HDRV Pull-down Resistor HDN R LDRV Pull-up Resistor LUP R LDRV Pull-down Resistor LDN © 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5 = 25°C, using circuit in Figure 1. A Conditions HDRV, LDRV Open 5.0V 20nC 200kHz FET ...
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... V CC regulator is sinking current to keep voltage on VCC pin constant. 7. Test Conditions 1.5V and V LDO_IN © 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5 (Continued) = 25°C, using circuit in Figure 1. A Conditions set point; 2μS noise fil- ter set point; 2μS noise fil- ...
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... Typical Performance Characteristics Figure 3. Dead Time Waveform Figure 4. PWM Load Transient (0 to 5A) Figure 5. PWM Load Transient (0 to 10A) © 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5 Figure 6. PWM Load Transient (0 to 15A) Figure 7. LDO Load Transient (0 to 2A) Figure 8. LDO Load Transient (0 to 5A) 7 ...
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... Typical Performance Characteristics Figure 9. PWM/LDO Power Up Figure 10. PWM/LDO Power Down Figure 11. Auto Restart © 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5 (Continued) Figure 12. Enable ON (I Figure 13. Enable OFF ( 5A) PWM = 5A) PWM www.fairchildsemi.com ...
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... INPUT VOLTAGE (V) Figure 15. LDO Line Regulation PWM Load Regulation (V 1.510 1.505 1.500 1.495 1.490 LOAD CURRENT (A) Figure 16. PWM Load Regulation © 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5 (Continued) = 1.5V) OUT 1.210 1.205 I = 10A L 1.200 1.195 1.190 ...
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... LDO can be from 1.5V to 5V, respectively. An internal shunt regulator at the VCC pin facilitates the controller operation from either 12V power source. V Bias Supply CC FAN5069 can be configured to operate from 5V or 12V for V . When 5V supply is used for V CC required to be connected between the supply and the V ...
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... PWM Operation Refer to Figure 20 for the PWM control mechanism. The FAN5069 uses the summing mode method of control to generate the PWM pulses. The amplified output of the current-sense amplifier is summed with an internally generated ramp and the combined signal is amplified and compared with the output of the error amplifier to get the pulse width to drive the high-side MOSFET ...
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... SW calculates to be 323.17KΩ. Auto Restart (PWM) The FAN5069 supports two modes of response when the internal fault latch is set. The user can configure it to keep the power supply latched in the OFF state OR in the Auto Restart mode. When the EN pin is tied to V the power supply is latched OFF ...
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... RMS currents. Optimum minimum inductance value enables the converter to © 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5 operate at the boundary of continuous and discontinuous conduction modes. Setting the Output Voltage (PWM) The internal reference for the PWM controller ...
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... For stable operation, the minimum capacitance of 100µF with ESR around 100mΩ is recommended. For other val- ues, contact the factory. Power MOSFET Selection (PWM) The FAN5069 is capable of driving N-Channel MOSFETs as circuit switch elements. For better performance, MOSFET selection must address these key parameters: ■ ...
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... RAMP Ramp Generator Figure 24. Closed-Loop System with Type-3 Network © 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5 R-C components for the snubber are selected as follows: (EQ. 14) a) Measure the SW node ringing frequency (F low capacitance scope probe Connect a capacitor (C so that it reduces this ringing by half. ...
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... FAN5069 has a high gain error amplifier around which the loop is closed. Figure 24 shows a Type-3 compensa- tion network. For Type-2 compensation, R3 and C3 are not used. Since the FAN5069 architecture employs sum- ming current mode, Type-2 compensation can be used for most applications. Type 3 Feedback Component Calculations ...
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... cross ------------------------------------------------- - 2 π × × × cross ----------------- - ( ) K 1 – © 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5 1 π C × × ---------------------------------------------------------- - L ⎛ ⎞ e × π × × ------ - ⎝ ⎠ ⎛ ...
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... The spreadsheet calculator, which is part of AN-6010, can be used to calculate all external component values for designing around FAN5069. The spreadsheet pro- vides optimized compensation components and gener- ates a Bode Plot to ensure loop stability. Based on the input values entered, AN-6010’s PSPICE ...
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... Resistor, 49.9K, 1%, 1/16W Resistor, 243K, 1%, 1/16W Resistor,453K, 1%, 1/16W Resistor,10K, 1%, 1/16W Resistor, 4.99K, 1%, 1/16W Resistor, 220Ω, 1%, 1/4W Resistor, 5.90K, 1%, 1/16W Resistor, 2.2Ω, 1%, 1/4W Connector Header 0.100 Vertical, Tin - 1 Pin IC, System Regulator, TSSOP16, FSID: FAN5069 © 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1 220 ...
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... Typical Application Board Layout Figure 26. Assembly Diagram Figure 27. Top Layer Figure 28. Mid Layer 1 © 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5 Figure 29. Mid Layer 2 Figure 30. Bottom Layer 20 www.fairchildsemi.com ...
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... Mechanical Dimensions Dimensions are in millimeters unless otherwise noted. © 2005 Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5 Figure 31. 16-Lead TSSOP 21 www.fairchildsemi.com ...
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... Fairchild Semiconductor Corporation FAN5069 Rev. 1.1.5 22 www.fairchildsemi.com ...