AD9951 Analog Devices, AD9951 Datasheet
AD9951
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AD9951 Summary of contents
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... SYNC 4 Control Registers M U System Clock X 4x-20x Clock Multipler IO Port One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 AD9951 14 19 DAC COS(x) Σ System Clock 14 -1 θ Reset www.analog.com © 2003 Analog Devices, Inc. All rights reserved. DAC ...
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... D/A converter programmable, complete high-frequency synthesizer capable of generating a frequency-agile analog output sinusoidal waveform 200 MHz. The AD9951 is designed to provide fast ABSOLUTE MAXIMUM RATINGS Maximum Junction Temp. ............................. +150 °C Vs ............................................................................ +4 V Digital Input Voltage............................... -0 +Vs Digital Output Current ....................................... Absolute maximum ratings are limiting values applied individually, and beyond which the serviceability of the circuit may be impaired ...
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... Synchronization; Register Updates (I/O UPDATE) Functionality of the SyncClk and I/O UPDATE Figure D- I/O Synchronization Block Diagram Figure E - I/O Synchronization Timing Diagram Synchronizing Multiple AD9951s Using a Single Crystal To Drive Multiple AD9951 Clock InputsError! Bookmark not defined. Serial Port Operation Instruction Byte Serial Interface Port Pin Description MSB/LSB Transfers ...
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... PRELIMINARY TECHNICAL DATA AD9951 PRELIMINARY ELECTRICAL SPECIFICATIONS =+1.8 V ±5%, R (Unless otherwise noted Multiplier enabled at 20×) Parameter REF CLOCK INPUT CHARACTERISTICS Frequency Range REFCLK Multiplier Disabled REFCLK Multiplier Enabled at 4X REFCLK Multiplier Enabled at 20X Input Capacitance Input Impedance Duty Cycle Duty Cycle with REFCLK Multiplier Enabled ...
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... DAC_BP, and that the recommended PLL loop filter values are used. 3 SYSCLK refers to the actual clock frequency used on-chip by the AD9951. If the Reference Clock Multiplier is used to multiply the external reference frequency, then the SYSCLK frequency is the external frequency multiplied by the Reference Clock Multiplier multiplication factor ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9951 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Figure 1 AD9951 Pinmap Page RESET PwrDwnCtl 34 DVDD 33 DGND AGND 32 AGND 31 30 AGND AVDD 29 ...
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... External Power Down Control section of this document for details. I Active high hardware reset pin. Assertion of the RESET pin forces the AD9951 to the initial state, as described in the IO Port Register map. I Asynchronous active high reset of the serial port controller. When high, the current IO operation is ...
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... I Digital power supply (for IO cells only, 3.3v optional) I Input signal used to synchronize multiple AD9951s. This input is connected to the SYNC_CLK output of a different AD9951. O Clock output pin, which serves as a synchronizer for external hardware ...
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... The AD9951 frequency tuning word(s) are unsigned numbers, where 80000000(hex) represents the highest output frequency possible, commonly referred to as the Nyquist frequency. Values ranging from than 80000001(hex) to FFFFFFFF (hex) will be expressed as aliased frequencies less than Nyquist. An example using a 3-bit phase accumulator will illustrate this principle. For a tuning word of 001, the phase accumulator output (PAO) increments from all zeros to all ones and repeats when the accumulator overflows after clock cycle number 8 ...
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... The AD9951 supports various clock methodologies. Support for differential or single-ended input clocks, enabling of an on-chip oscillator and/or phase-locked loop (PLL) multiplier are all controlled via user programmable bits. The AD9951 may be configured in one of six operating modes to generate the system clock. The modes are configured using the ClkModeSelect pin, CFR2< ...
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... The PLL is bypassed by programming a value outside the range of 4-20 (decimal). When bypassed, the PLL is shut down to conserve power. DAC Output The AD9951 incorporates an integrated 14-bit current output DAC. Two complementary outputs provide a combined full-scale output current (I common-mode noise that might be present at the DAC output, offering the advantage of an increased signal-to-noise ratio ...
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... Motorola 6905/11 SPI and Intel 8051 SSR protocols. The interface allows read/write access to all registers that configure the AD9951. MSB first or LSB first transfer formats are supported. In addition, the AD9951’s serial interface port can be configured as a single pin I/O (SDIO), which allows a two-wire interface or two unidirectional pins for in/out (SDIO/SDO), which enables a three wire interface ...
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... PRELIMINARY TECHNICAL DATA AD9951 Register Map Register Bit (MSB) Name Range Bit 7 (Serial (Internal address) address) <7:0> Digital (00h) Power Down Control Function <15:8> Register #1 Open (01h) (CFR1) <23:16> Automatic (00h) Sync (02h) Enable <31:24> (03h) Open Control Function <7:0> Register #2 (04h) (CFR2) <15:8> (01h) (05h) <23:16> (06h) Amplitude < ...
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... PRELIMINARY TECHNICAL DATA Control Register Bit Descriptions Control Function Register #1 (CFR1) The CFR1 is used to control the various functions, features, and modes of the AD9951. The functionality of each bit is detailed below. CFR1<26>: Amplitude ramp rate load control bit. When CFR1<26> (default), the amplitude ramp rate timer is loaded only upon timeout (timer ==1) and is NOT loaded due to an I/O UPDATE input signal. When CFR1< ...
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... When CFR1<22> the software controlled manual synchronization feature is executed. The SYNC_CLK rising edge is advanced by one SYSCLK cycle and this bit is cleared. To advance the rising edge multiple times, this bit needs to be set for each advance. See the Synchronizing Multiple AD9951s section of this document . CFR1<20>: Amplitude dither enable bit. ...
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... CFR1<9>: SDIO Input Only. When CFR1<9> (default), the SDIO pin has bi-directional operation (2-wire serial programming mode). When CFR1<9> the serial data I/O pin (SDIO) is configured as an input only pin (3-wire serial programming mode). REV. PrA 3/4/03 Page 17 AD9951 Analog Devices, Inc. ...
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... In this mode, when the PwrDwnCtl input pin is high, all functions are powered down. This includes the DAC and PLL, which take a significant amount of time to power up. CFR1<1>: SyncClk Disable bit. When CFR1<1> (default), the SyncClk pin is active. REV. PrA 3/4/03 Page 18 AD9951 Analog Devices, Inc. ...
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... Control Function Register #2 (CFR2) The CFR2 is comprised of three bytes located in parallel addresses 06h-04h. The CFR2 is used to control the various functions, features, and modes of the AD9951, primarily related to the analog sections of the chip. All bits of the CFR2 will be routed directly to the Analog section of the AD9951 as a single 24-bit bus labeled CFR2< ...
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... The exact value of phase offset is given by the following formula: Mode of Operation REV. PrA 3/4/03 POW Φ = 14 2 Page 20 AD9951 ° * 360 Analog Devices, Inc. ...
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... Continuous Clear and “Clear and Release” Phase Accumulator Clear Functions The AD9951 allows for a programmable continuous zeroing of the phase accumulator as well as a “clear and release”, or automatic zeroing function. Each feature is individually controlled via bits the CFR1. CFR1<13> is the Automatic Clear Phase Accumulator bit. CFR1<10> clears the Phase Accumulator ...
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... When high, amplitude dithering is enabled. Shaped On-Off Keying General Description: The Shaped On-Off keying function of the AD9951 allows the user to control the ramp-up and ramp-down time of an “on-off” emission from the DAC. This function is used in “burst transmissions” of digital data to reduce the adverse spectral impact of short, abrupt bursts of data ...
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... To DAC 1 OSK Enable CFR<25> OSK Pin Out inc/dec Enable Auto Scale Factor Generator Page 23 AUTO OSK Enable CFR<24> Load OSK Timer SyncClock CFR1<26> Amplitude Ramp Rate Register (ARR) HOLD Data Load Up/Dn EN Ramp Rate Timer Analog Devices, Inc. AD9951 Clock ...
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... CFR1<24> logic 0. When configured for external Shaped On-Off Keying, the content of the ASFR becomes the scale factor for the data path. The scale factors are synchronized to dds_Clock via the I/O UPDATE functionality. REV. PrA 3/4/03 Increment/decrement size Page 24 AD9951 Analog Devices, Inc. ...
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... Synchronization; Register Updates (I/O UPDATE) Functionality of the SyncClk and I/O UPDATE Data into the AD9951 is synchronous to the SyncClk pin. That is, the I/O UPDATE pin is sampled on the rising edge of the SyncClk clock provided by the AD9951. As shown in the Figure D, sysclk is fed to a divide-by-4 frequency divider to produce sync_clk which is also provided to the user on the SyncClk pin. This enables synchronization of external hardware with the AD9951’ ...
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... Edge Detection Logic SYNCCLK Gating I/O Buffer Latches Figure D- I/O Synchronization Block Diagram A B Data(2) Data(2) The device registers an I/O Update at point A. The data is tranferred from the asynchronously loaded I/O buffers at point B. Page I/O UPDATE SCLK SDI CS Data(3) Analog Devices, Inc. AD9951 Data(3) ...
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... The AD9951 crystal oscillator output signal is available on the CrystalOut pin, enabling one crystal to drive multiple AD9951s. In order to drive multiple AD9951s with one crystal, the CrystalOut pin of the AD9951 using the external crystal should be connected to the REFCLK input of the other AD9951. The CrystalOut pin is static until the CFR2<1> bit is set, enabling the output. The drive strength of the CrystalOut pin is typically very low, so this signal should be buffered prior to using it to drive any loads ...
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... At the completion of any communication cycle, the AD9951 serial port controller expects the next 8 rising SCLK edges to be the instruction byte of the next communication cycle.All data input to the AD9951 is registered on the rising edge of SCLK. All data is driven out of the AD9951 on the falling edge of SCLK. Figures are useful in understanding the general operation of the AD9951 Serial Port ...
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... R/-Wb—Bit 7 of the instruction byte determines whether a read or write data transfer will occur after the instruction byte write. Logic high indicates read operation. Logic zero indicates a write operation. REV. PrA 3/4/ Table 6 Instruction Byte Page 29 AD9951 D1 LSB A1 A0 Analog Devices, Inc. ...
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... IO operation is complete. All data written to (read from) the AD9951 must be (will be) in MSB first order. If the LSB mode is active, the serial port controller will generate the least significant byte address first followed by the next greater significant byte addresses until the IO operation is complete ...
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... Since the Amplitude Scale Factor register is two bytes wide, this ends the communication cycle. Notes on Serial Port Operation 1) The AD9951 serial port configuration bits reside in bits 8 and 9 of CFR1 (address 00h). The configuration changes immediately upon writing to this register. For multi-byte transfers, writing to this register may occur during the middle of a communication cycle ...
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... PwrDwnCtl input pin is low, the external power down control is inactive. When the CFR1<3> bit is zero, and the PwrDwnCtl input pin is high, the AD9951 is put into a “fast recovery power down” mode. In this mode, the digital logic and the DAC digital logic are powered down ...
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... PRELIMINARY TECHNICAL DATA AD9951 Application Suggestions REFCLK Figure F Synthesized L.O For Upconversion/DownConversion Ref Signal Filter Figure G Digitally Programmable “Divide-by-N” Function in PLL REV. PrA 3/4/03 RF/IF Input AD9951 LPF Phase Loop Comparator Filter AD9951 Tuning Word Page 33 AD9951 Modulated/ Demodulated Signal VCO Analog Devices, Inc. ...
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... PRELIMINARY TECHNICAL DATA Frequency Saw Crystal Frequency Figure H Two AD9951s Synchronized to Provide I & Q Carriers with Independent Phase Offsets for Nulling REV. PrA 3/4/03 Phase Tuning Offset Word Word 1 REFCLK AD9951 DDS Iout LPF REFCLK Crystal Out Sync Out Sync In AD9951 DDS Iout ...