AD9954 Analog Devices, AD9954 Datasheet
AD9954
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AD9954 Summary of contents
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... DDS Clock RAM Data <31:18> Timing & Control Logic SYNC 4 Control Registers M U System Clock X 4x-20x Clock Multipler PS<1:0> One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 AD9954 Phase Offset 14 19 DAC COS(x) Σ System Clock θ Comparator ...
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... Control Function Register #1 (CFR2) Other Register Descriptions Amplitude Scale Factor (ASF) Amplitude Ramp Rate (ARR) REV. PrB 3/4/03 into the AD9954 via a serial I/O port. The AD9954 includes an integrated 1024x32 Static RAM to support flexible frequency sweep capability in several modes. The AD9954 also supports a to form ...
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... Synchronization; Register Updates (I/O UPDATE) Functionality of the SyncClk and I/O UPDATE Figure D- I/O Synchronization Block Diagram Figure E - I/O Synchronization Timing Diagram Synchronizing Multiple AD9954s Using a Single Crystal To Drive Multiple AD9954 Clock Inputs Serial Port Operation Instruction Byte Serial Interface Port Pin Description MSB/LSB Transqfers Example Operation ...
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... PRELIMINARY TECHNICAL DATA Digital and Input Clock Power Down AD9954 Application Suggestions REV. PrB 3/4/03 Error! Bookmark not defined. Page 4 AD9954 52 Analog Devices, Inc. ...
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... PRELIMINARY TECHNICAL DATA AD9954 PRELIMINARY ELECTRICAL SPECIFICATIONS =+1.8 V ±5%, R (Unless otherwise noted Multiplier enabled at 20×) Parameter REF CLOCK INPUT CHARACTERISTICS Frequency Range REFCLK Multiplier Disabled REFCLK Multiplier Enabled at 4X REFCLK Multiplier Enabled at 20X Input Capacitance Input Impedance Duty Cycle Duty Cycle with REFCLK Multiplier Enabled ...
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... 1.25 I 0.6 I 2 1.35 I 0.4 Analog Devices, Inc. AD9954 Units dBc dBc pF kΩ µ MHz ps RMS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc ...
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... DAC_BP, and that the recommended PLL loop filter values are used. 5 SYSCLK refers to the actual clock frequency used on-chip by the AD9954. If the Reference Clock Multiplier is used to multiply the external reference frequency, then the SYSCLK frequency is the external frequency multiplied by the Reference Clock Multiplier multiplication factor ...
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... Figure 1 AD9954 Pinmap Page RESET PwrDwnCtl 34 DVDD 33 DGND AGND 32 COMP_INB 31 30 COMP_IN AVDD 29 ...
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... A resistor (3.85KΩ nominal) connected from AGND to DAC_Rset establishes the reference current for the DAC. O Comparator Output I Comparator input I Comparator complementary input I Input pin used as an external power down control. See the External Power Down Control section of this document for details. Page 9 AD9954 Analog Devices, Inc. ...
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... PS0, PS1 REV. PrB 3/4/03 I Active high hardware reset pin. Assertion of the RESET pin forces the AD9954 to the initial state, as described in the IO Port Register map. I Asynchronous active high reset of the serial port controller. When high, the current IO operation is immediately terminated enabling a new IO operation ...
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... The AD9954 frequency tuning word(s) are unsigned numbers, where 80000000(hex) represents the highest output frequency possible, commonly referred to as the Nyquist frequency. Values ranging from than 80000001(hex) to FFFFFFFF (hex) will be expressed as aliased frequencies less than Nyquist. An example using a 3-bit phase accumulator will illustrate this principle. For a tuning word of 001, the phase accumulator output (PAO) increments from all zeros to all ones and repeats when the accumulator overflows after clock cycle number 8 ...
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... The AD9954 supports various clock methodologies. Support for differential or single-ended input clocks, enabling of an on-chip oscillator and/or phase-locked loop (PLL) multiplier are all controlled via user programmable bits. The AD9954 may be configured in one of six operating modes to generate the system clock. The modes are configured using the ClkModeSelect pin, CFR2< ...
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... The PLL is bypassed by programming a value outside the range of 4-20 (decimal). When bypassed, the PLL is shut down to conserve power. DAC Output The AD9954 incorporates an integrated 14-bit current output DAC. Two complementary outputs provide a combined full-scale output current (I common-mode noise that might be present at the DAC output, offering the advantage of an increased signal-to-noise ratio ...
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... Motorola 6905/11 SPI and Intel 8051 SSR protocols. The interface allows read/write access to all registers that configure the AD9954. MSB first or LSB first transfer formats are supported. In addition, the AD9954’s serial interface port can be configured as a single pin I/O (SDIO), which allows a two-wire interface or two unidirectional pins for in/out (SDIO/SDO), which enables a three wire interface ...
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... PRELIMINARY TECHNICAL DATA AD9954 Register Map – when Linear Sweep Enable Bit is False (CFR1<21>=0) (NOTE: RAM Enable Bit CFR1<31> only activates the RAM itself, not the RAM Segment Control Words) Register Bit (MSB) Name Range Bit 7 (Serial address) <7:0> Digital Power Down ...
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... RAM Segment 3 Beginning Address <9:6> Active RAM Segment 3 Beginning Address <5:0> RAM Segment 3 Final Address <7:0> RAM Segment 3 Address Ramp Rate <15:8> RAM Segment 3 Address Ramp Rate <7:0> RAM [1023:0] <31:0> (Read Instructions write out RAM Signature Register data) Page 16 AD9954 00h 00h 00h 00h PS0=0 PS1=0 RAM Segment 0 PS0=0 Final Address < ...
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... PRELIMINARY TECHNICAL DATA AD9954 Register Map – when Linear Sweep enable bit is true (CFR1<21> (NOTE: RAM Enable Bit CFR1<31> only activates the RAM itself, not the RAM Segment Control Words) Register Bit (MSB) Name Range Bit 7 (Serial (Internal address) address) <7:0> Digital ...
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... Control Register Bit Descriptions Control Function Register #1 (CFR1) The CFR1 is used to control the various functions, features, and modes of the AD9954. The functionality of each bit is detailed below. CFR1<31>: RAM Enable bit. When CFR1<31> (default). When CFR1<31> is inactive, the RAM is disabled for operation ...
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... DDS core). CFR1<29:27>: Internal Profile Control bits. These bits cause the Profile Bits to be ignored and put the AD9954 into an automatic “profile loop sequence” that allows the user to implement a frequency/phase composite sweep that runs without external inputs. See the Internal Profile Control section of this document for details. CFR1< ...
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... See the Synchronizing Multiple AD9954s section of this document for details. . CFR1<21>: Linear Frequency Sweep Enable. When CFR1<21> (default), the linear frequency sweep capability of the AD9954 is inactive. When CFR1<21> the linear frequency sweep capability of the AD9954 is enabled. When enabled, either the Rising or Falling Delta Frequency Tuning Word is applied to the Frequency accumulator at the programmed ramp rate causing the output frequency to ramp up or ramp down, controlled by the Profile 0 input ...
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... When CFR1<15> (default), the linear sweep ramp rate timer is loaded only upon timeout (timer ==1) and is NOT loaded due to an I/O UPDATE input signal. When CFR1<15> the linear sweep ramp rate timer is loaded upon timeout (timer == the time of an I/O UPDATE input signal. REV. PrB 3/4/03 Page 21 AD9954 Analog Devices, Inc. ...
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... When CFR1<11> (default), the frequency accumulator functions as normal. When CFR1<11> the frequency accumulator memory elements are asynchronously cleared. CFR1<10>: Clear Phase Accumulator. When CFR1<10> (default), the phase accumulator functions as normal. When CFR1<10> the phase accumulator memory elements are asynchronously cleared. REV. PrB 3/4/03 Page 22 AD9954 Analog Devices, Inc. ...
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... When CFR1<5> the DAC is disabled and is in its lowest power dissipation state. CFR1<4>: Clock Input Power Down bit. When CFR1<4> (default), the clock input circuitry is enabled for operation. When CFR1<4> the clock input circuitry is disabled and the device is in its lowest power dissipation state. REV. PrB 3/4/03 Page 23 AD9954 Analog Devices, Inc. ...
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... CFR1<0>: Not used. Leave at 0. NOTE: Assertion of this bit may cause the SyncClk pin to momentarily stop generating a Sync Clock signal. The device will not be operational during the re-synchronization period. REV. PrB 3/4/03 Page 24 AD9954 Analog Devices, Inc. ...
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... Control Function Register #2 (CFR2) The CFR2 is comprised of three bytes located in parallel addresses 06h-04h. The CFR2 is used to control the various functions, features, and modes of the AD9954, primarily related to the analog sections of the chip. All bits of the CFR2 will be routed directly to the Analog section of the AD9954 as a single 24-bit bus labeled CFR2< ...
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... When the RAM enable bit is set, CFR1<31> and the RAM destination is cleared, CFR1<30>=0, the RAM supplies the phase offset word and this register has no affect on device operation. REV. PrB 3/4/03 POW Φ = 14 2 Page 26 AD9954 ° * 360 Analog Devices, Inc. ...
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... Similarly, when the RAM output drives the phase offset adder the Frequency Tuning Word (FTW, hex address 04h) drives the phase accumulator. When CFR1<31> is logic zero, the RAM is inactive unless being written to via the serial port. The power up state of the AD9954 is single REV. PrB 3/4/03 ...
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... RAM Controlled Modes of Operation Direct Switch Mode Direct Switch Mode enables FSK or PSK modulation. The AD9954 is programmed for Direct Switch Mode by writing the RAM Enable bit true and programming the RAM Segment Mode Control bits of each desired profile to logic 000(b). This mode simply reads the RAM contents at the RAM Segment Beginning Address for the current profile ...
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... Phase Offset Word drives the phase-offset adder. 2-tone FSK is accomplished by using only one Profile pin for data. Programming the AD9954 for PSK modulation is similar to FSK except the RAM destination bit is set to a logic 1, enabling the RAM output to drive the phase offset adder. The FTW drives the input to the phase accumulator. Toggling the profile pins changes (modulates) the current phase value. The upper 14-bits of the RAM drive the phase adder (bits < ...
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... Bi-directional Ramp Mode Bi-directional Ramp mode allows the AD9954 to offer a symmetrical sweep between two frequencies using the Profile<0> signal as the control input. The AD9954 is programmed for Bi- directional Ramp mode by writing the RAM Enable bit true and the RAM Mode Control bits of RSCW0 to logic 010(b). In Bi-directional Ramp mode, the Profile< ...
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... Continuous Bi-directional Ramp Mode Continuous Bi-directional Ramp mode allows the AD9954 to offer an automatic symmetrical sweep between two frequencies. The AD9954 is programmed for Continuous Bi-directional Ramp mode by writing the RAM Enable bit true and the RAM Mode Control bits of each profile to be used to logic 011(b). Upon entering this mode (via an I/O_update or changing Profile< ...
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... Setting the RAM destination bit true such that the RAM output drives the phase-offset adder is valid. While the above discussion describes a frequency sweep, a phase sweep operation is also available. RAM Controlled Modes of Operation Summary The AD9954 offers 5 modes of RAM controlled operation, as shown in table 3 below. RSCW<7:5> (binary) 000 ...
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... OPEN Internal Profile Control The AD9954 offers a mode in which a composite frequency sweep can be built, for which the timing control is software programmable. The “internal profile control” capability disengages the Profile<1:0> pins and enables the AD9954 to take control of switching between profiles. Modes are defined that allow continuous or single burst profile switches for three combinations of profile selection bits. These are listed in the table below. When the any of the CFR1< ...
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... Profile<0> pin is acting as the sweep direction indicator, any transfer of data from the I/O buffers to the internal registers can only be initiated by a rising edge on the I/O UPDATE pin. The linear sweep function of the AD9954 requires the lowest frequency to be loaded into FTW0 register and the highest frequency into FTW1 register. For piece-wise, non-linear frequency transitions necessary to reprogram the registers while the frequency transition is in progress to affect the desired response ...
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... The frequency continues to sweep up at the rate set by the rising sweep ramp rate at the resolution set by the rising delta frequency tuning word until it reaches the terminal frequency. Upon reaching the terminal frequency, the output frequency immediately returns to the REV. PrB 3/4/03 A Linear S weep Mode P rofile< 0> Page 35 AD9954 B Time P rofile< 0> Analog Devices, Inc. ...
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... This accumulation of the RDFTW at the rate given by the ramp rate (RSRR) continues until the output of the frequency adder is equal to the FTW1 register value. At this time, the accumulation is stopped causing the AD9954 to output the frequency given by the FTW1. The output remains at FTW1 for as long as the profile 0 pin remain logic 1. ...
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... This accumulation of the negated FDFTW at the rate given by the ramp rate (FSRR) continues until the output of the frequency adder is equal to the FTW0 register value. At this time, the accumulation is stopped causing the AD9954 to output the frequency given by the FTW0. The output remains at FTW0 for as long as the profile 0 pin remain logic 0. ...
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... The ramp rate that is loaded is a function of the profile<0> input pin. Continuous and “Clear and Release” Frequency and Phase Accumulator Clear Functions The AD9954 allows for a programmable continuous zeroing of the frequency sweep logic and the phase accumulator as well as a “clear and release”, or automatic zeroing function. Each feature is individually controlled via bits the CFR1. CFR1< ...
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... The third method of phase control involves the RAM and the profile input pins. The AD9954 can be configured such that the RAM drives the phase adjust circuitry. The user can control the phase offset via the RAM in an identical manner allowed for frequency sweeping ...
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... The downside to dithering is a rise in the noise floor. Amplitude dithering is similar, except it affects the output signal routed to the DAC. The AD9954 uses a 32-bit linear feedback shift register (LFSR), shown in Figure 7 below, to generate the pseudo random binary sequence that is used for both phase and amplitude dither data. ...
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... To DAC 1 OSK Enable CFR<25> OSK Pin Out inc/dec Enable Auto Scale Factor Generator Page 41 AUTO OSK Enable CFR<24> Load OSK Timer SyncClock CFR1<26> Amplitude Ramp Rate Register (ARR) HOLD Data Load Up/Dn EN Ramp Rate Timer Analog Devices, Inc. AD9954 Clock ...
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... The second method in which the sweep ramp rate timer can be loaded before reaching a count the Load OSK Timer bit (CFR1<26>) bit is set and an I/O UPDATE (or change in profile) is issued. REV. PrB 3/4/03 Increment/decrement size Page 42 AD9954 Analog Devices, Inc. ...
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... Synchronization; Register Updates (I/O UPDATE) Functionality of the SyncClk and I/O UPDATE Data into the AD9954 is synchronous to the sync_clk signal (supplied externally to the user on the SYNC_CLK pin). The I/O UPDATE pin is sampled on the rising edge of the sync_clk. Internally, sysclk is fed to a divide-by-4 frequency divider to produce the sync_clk signal. ...
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... SYNCCLK Gating Register I/O Buffer Latches Memory Figure D- I/O Synchronization Block Diagram A B Data(2) Data(2) The device registers an I/O Update at point A. The data is tranferred from the asynchronously loaded I/O buffers at point B. Page 44 SyncClk Disable I/O UPDATE Profile<1:0> SCLK SDI CS Data(3) Data(3) Analog Devices, Inc. AD9954 ...
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... The AD9954 crystal oscillator output signal is available on the CrystalOut pin, enabling one crystal to drive multiple AD9954s. In order to drive multiple AD9954s with one crystal, the CrystalOut pin of the AD9954 using the external crystal should be connected to the REFCLK input of the other AD9954. REV. PrB 3/4/03 ...
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... At the completion of any communication cycle, the AD9954 serial port controller expects the next 8 rising SCLK edges to be the instruction byte of the next communication cycle. All data input to the AD9954 is registered on the rising edge of SCLK. All data is driven out of the AD9954 on the falling edge of SCLK. Figures are useful in understanding the general operation of the AD9954 Serial Port ...
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... PRELIMINARY TECHNICAL DATA Instruction Byte The instruction byte contains the following information as shown in the table below: Instruction Byte Information MSB REV. PrB 3/4/ Table 7 Instruction Byte Page 47 AD9954 D1 LSB A1 A0 Analog Devices, Inc. ...
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... Serial Interface Port Pin Description SCLK — Serial Clock. The serial clock pin is used to synchronize data to and from the AD9954 and to run the internal state machines. SCLK maximum frequency is 25 MHz. CSB — Chip Select Bar. Active low input that allows more than one device on the same serial communications line ...
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... PRELIMINARY TECHNICAL DATA operation is complete. All data written to (read from) the AD9954 must be (will be) in MSB first order. If the LSB mode is active, the serial port controller will generate the least significant byte address first followed by the next greater significant byte addresses until the IO operation is complete ...
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... PRELIMINARY TECHNICAL DATA Notes on Serial Port Operation 1) The AD9954 serial port configuration bits reside in bits 8 and 9 of CFR1 (address 00h). The configuration changes immediately upon writing to this register. For multi-byte transfers, writing to this register may occur during the middle of a communication cycle. Care must be taken to compensate for this new configuration for the remainder of the current communication cycle ...
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... PRELIMINARY TECHNICAL DATA When the CFR1<3> bit is zero, and the PwrDwnCtl input pin is high, the AD9954 is put into a “fast recovery power down” mode. In this mode, the digital logic and the DAC digital logic are powered down. The DAC bias circuitry, comparator, PLL, oscillator, and clock input circuitry is NOT powered down. The comparator can be powered down by setting the Comparator Power Down Bit, CFR1< ...
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... PRELIMINARY TECHNICAL DATA AD9954 Application Suggestions REFCLK Figure F Synthesized L.O For Upconversion/DownConversion Ref Signal Filter Figure G Digitally Programmable “Divide-by-N” Function in PLL Figure H Frequency Agile Clock Generator REV. PrB 3/4/03 RF/IF Input AD9954 LPF Phase Loop Comparator Filter AD9954 Tuning Word Tuning Word Iout ...
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... PRELIMINARY TECHNICAL DATA Frequency SAW Crystal Frequency Figure I Two AD9954s Synchronized to Provide I & Q Carriers with Independent Phase Offsets for Nulling REV. PrB 3/4/03 Phase Tuning Offset Word Word 1 REFCLK AD9954 DDS Iout LPF Iout REFCLK Crystal Out Sync Out Sync In Iout AD9954 DDS ...