AT45DB642D ATMEL Corporation, AT45DB642D Datasheet
AT45DB642D
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AT45DB642D Summary of contents
Page 1
... JEDEC Standard Manufacturer and Device ID Read • 100,000 Program/Erase Cycles Per Page Minimum • Data Retention – 20 Years • Green (Pb/Halide-free/RoHS Compliant) Packaging Options • Temperature Range – Industrial: -40° +85° C 64-megabit 2.7-volt Dual-interface ® DataFlash AT45DB642D 3542H–DFLASH–4/08 ...
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... To allow for simple in-system reprogrammability, the AT45DB642D does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB642D is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK 8-bit interface consisting of the input/output pins (I/O7 - I/O0) and the clock pin (CLK) ...
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... RDY/BUSY and page-to-buffer transfers. The busy status indicates that the Flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed. 3542H–DFLASH–4/08 AT45DB642D Asserted State Type Low Input – ...
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... RDY/BUSY 1 RESET VCC 6 GND SCK/CLK AT45DB642D 4 pin is used to supply the source voltage to the device. CC voltages may produce spurious results and should not be attempted I/O7 25 I/O6 24 I/O5 23 I/O4 22 VCCP 21 GNDP 20 I/O3 19 I/O2 18 I/O1 17 ...
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... SER/BYTE 4. Memory Array To provide optimal flexibility, the memory array of the AT45DB642D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illus- trates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis ...
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... The don’t care bytes that follow the address bytes are needed to initialize the read operation. Following the don’t care bytes, additional clock pulses on the SCK/CLK pin will result in data being output on either the SO (serial output) pin or the eight out- put pins (I/O7- I/O0). AT45DB642D 6 Table 15-1 on page 28 through Table 15-6 on 3542H– ...
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... A0). Following the address bytes, additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin. 3542H–DFLASH–4/08 specification. The Continuous Array Read bypasses both data buff- CAR1 specification. The Continuous Array Read bypasses both CAR1 AT45DB642D . To perform a CAR1 . To perform a continuous CAR2 7 ...
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... BFA0). To perform a buffer read from the binary buffer (1024 bytes), the opcode must be clocked into the device followed by three address bytes comprised of 14 don’t care bits and 10 buffer address bits (BFA9 - BFA0). AT45DB642D 8 specification. The Main Memory Page Read bypasses SCK ...
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... When a low-to-high transition occurs on the CS pin, the part will program the data stored in the buffer into the specified page in the main memory necessary that the 3542H–DFLASH–4/08 AT45DB642D . During this time, the status register and the EP ...
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... AT45DB642D 10 PA8/ PA7/ PA6/ PA5/ A18 A17 A16 A15 • • • • ...
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... During this time, the Status Register will indicate that the device is busy. CE AT45DB642D PA4/ PA3/ PA2/ PA1/ A14 A13 A12 A11 • ...
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... Sector Protection Register. The status of whether or not sector protection has been enabled or disabled by either the software or the hardware controlled methods can be deter- mined by checking the Status Register. AT45DB642D 12 Byte 1 Chip Erase ...
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... Opcode Byte Each transition represents 8 bits Byte 1 Disable Sector Protection CS Opcode Byte Each transition represents 8 bits AT45DB642D Byte 2 Byte 3 3DH 2AH 7FH Opcode Opcode Opcode Byte 2 Byte 3 Byte 4 Byte 2 Byte 3 3DH 2AH 7FH Opcode Opcode ...
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... Time Period WP Pin Enable Sector Protection Command 1 High 2 Low Command Issued During Period High AT45DB642D 14 time. When the WP pin is deasserted; however, the sector protection WPE 2 Command Not Issued Previously – Issue Command X – Issue Command time) as long as the Enable Sec- ...
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... Sector Protection Register and before 3542H–DFLASH–4/08 Sector Protection Register Sector 0 (0a, 0b) (Page 0-7) Bit 7, 6 (1) 1. The default value for bytes 0 through 31 when shipped from Atmel is 00H don’t care AT45DB642D 0 (0a, 0b) See Table 9 (Page 8-255) Bit 5, 4 Bit 3, 2 ...
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... The Sector Protection Register can be reprogrammed while the sector protection enabled or dis- abled. Being able to reprogram the Sector Protection Register with the sector protection enabled allows the user to temporarily disable the sector protection to an individual sector rather than dis- abling sector protection completely. AT45DB642D 16 Byte 1 3DH ...
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... Each transition represents 8 bits 3542H–DFLASH–4/08 Opcode Opcode Opcode Byte 2 Byte 3 Byte Dummy Byte Serial Interface = 3 Dummy Bytes AT45DB642D Byte 1 Byte 2 Byte 3 3DH 2AH 7FH Data Byte Data Byte Data Byte Byte 1 Byte 2 Byte 3 32H xxH ...
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... Sector Lockdown com- mand if necessary. Command Sector Lockdown Figure 10-1. Sector Lockdown CS Opcode Byte Each transition represents 8 bits AT45DB642D 18 Byte 1 3DH Opcode Opcode Opcode Address Byte 2 Byte 3 Byte 4 Bytes , during which time the Status P ...
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... Sector 0 (0a, 0b) (Page 0-7) Bit 7, 6 details the values read from the Sector Lockdown Register. Sector Lockdown Register xx = Dummy Byte Serial Interface = 3 Dummy Bytes AT45DB642D 0 (0a, 0b) See Below 0a 0b (Page 8-255) Bit 5, 4 Bit ...
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... Therefore not possible to only program the first two bytes of the register and then pro- gram the remaining 62 bytes at a later time. The Program Security Register command utilizes the internal SRAM buffer for processing. Therefore, the contents of the buffer will be altered from its previous state when this command is issued. AT45DB642D 20 Security Register • • • 0 ...
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... Figure 10-4. Read Security Register Opcode Each transition represents 8 bits 3542H–DFLASH–4/08 Opcode Opcode Opcode Data Byte Byte 2 Byte 3 Byte Data Byte AT45DB642D Data Byte Data Byte Data Byte Data Byte ...
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... The operation is internally self-timed and should take place in a maximum time of t and the RDY/BUSY pin will indicate that the part is busy. AT45DB642D 22 ), the status register can be read or the RDY/BUSY can be XFR ), the status register and the RDY/BUSY pin will indicate that the part is busy ...
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... The device density is indicated using bits and 2 of the status register. For the AT45DB642D, the four bits are 1111 The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices ...
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... Deep Power-down, the device will return to the normal standby mode. Command Resume from Deep Power-down Figure 12-2. Resume from Deep Power-Down AT45DB642D 24 time. Once the device has entered the Deep Power-down mode, all EDPD ...
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... Section , during which time the Status Register will indicate that the device Opcode Byte 1 Each transition represents 8 bits AT45DB642D Section 27. ”Ordering Information” on 13.1). Byte 1 Byte 2 Byte 3 3DH 2AH 80H Opcode Opcode Opcode Byte 2 Byte 3 ...
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... Manufacturer ID codes that are two, three or even four bytes long with the first byte(s) in the sequence being 7FH. A system should detect code 7FH as a “Continuation Code” and continue to read Manufacturer ID bytes. The first non-7FH byte would signify the last byte of Manufacturer ID data. For Atmel (and some other manufacturers), the Manufacturer ID data is comprised of only one byte. AT45DB642D 26 Bit 3 ...
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... Group C can be executed. The Group B commands using buffer 1 should use Group C commands using buffer 2 and vice versa. Finally, during the internally self- timed portion of a Group D command, only the Status Register Read command should be executed. 3542H–DFLASH–4/08 AT45DB642D 27 ...
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... Buffer 1 to Main Memory Page Program without Built-in Erase Buffer 2 to Main Memory Page Program without Built-in Erase Page Erase Block Erase Sector Erase Chip Erase Main Memory Page Program Through Buffer 1 Main Memory Page Program Through Buffer 2 AT45DB642D 28 Serial/8-bit Opcode Both D2H Both E8H ...
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... Auto Page Rewrite through Buffer 1 Auto Page Rewrite through Buffer 2 Deep Power-down Resume from Deep Power-down Status Register Read Manufacturer and Device ID Read 3542H–DFLASH–4/08 AT45DB642D Serial/8-Bit Opcode Both 3DH + 2AH + 7FH + A9H Both 3DH + 2AH + 7FH + 9AH Both ...
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... E8h Notes Don’t Care A = Address Bit *The number with (*) is for 8-bit interface. AT45DB642D 30 Address Byte Address Byte ...
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... N/A N AT45DB642D Address Byte ...
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... RDY/BUSY bit of the status register or the RDY/BUSY pin to determine whether the program or erase operation was completed. Fixed tim- ing is not recommended. AT45DB642D 32 . During power-up, the internal Power-on Reset circuitry keeps the device in VCSL ...
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... This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT45DB642D -40° 85° C 2.7V to 3.6V Min Typ Max 9 ...
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... Block Erase Time (8,192/8,448 bytes Sector Erase Time (262,144/270,336 bytes Chip Erase Time CE t RESET Pulse Width RST t RESET Recovery Time REC Note: 1. Values are based on device characterization, not 100% tested in production. AT45DB642D 34 Min Typ Max 6.8 6.8 0.1 0 100 ...
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... Input Test Waveforms and Measurement Levels < (10 20. Output Test Load 3542H–DFLASH–4/08 Min 0 DRIVING 1.5V MEASUREMENT LEVELS LEVEL 0.45V DEVICE UNDER TEST 30 pF AT45DB642D Typ Max 100 400 400 ...
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... Waveform 2 – SPI Mode 3 Compatible (for Frequencies MHz) CS SCK/CLK SO SI Note: To operate the device at 50 MHz in SPI mode, the combined CPU setup time and rise/fall time should be less than 2 ns. AT45DB642D 36 period. These timing waveforms are valid over the full frequency range (max ...
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... WL CSS t V VALID OUT VALID MHz) MAX CSS HIGH Z VALID OUT VALID IN AT45DB642D CSH DIS HIGH IMPEDANCE CSH t DIS HIGH IMPEDANCE CSH DIS HIGH IMPEDANCE CSH ...
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... Last bit of BYTE-MOSI is clocked out from the Master. E. Last bit of BYTE-MOSI is clocked into the slave. F. Slave clocks out first bit of BYTE-SO. G. Master clocks in first bit of BYTE-SO. H. Slave clocks out second bit of BYTE-SO. I. Master clocks in last bit of BYTE-SO. AT45DB642D 38 Function ...
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... The CS signal should be in the high state before the RESET signal is deasserted. 3542H–DFLASH–4/08 Function BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE a BYTE b HIGH IMPEDANCE AT45DB642D BYTE c BYTE d BYTE e BYTE f BYTE g BYTE h t REC t CSS t RST HIGH IMPEDANCE 39 ...
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... Write Operations The following block diagram and waveforms illustrate the various write sequences available. PAGE (1024/1056 BYTES) BUFFER 1 TO MAIN MEMORY PAGE PROGRAM BUFFER 1 (1024/1056 BYTES) BUFFER 1 AT45DB642D 40 CMD 8 bits 8 bits Page Address (A22 - A10) ...
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... Starts self-timed erase/program operation BINARY PAGE SIZE A22-A10 + 10 DON'T CARE BITS CMD PA12-5 FLASH MEMORY ARRAY MAIN MEMORY READ PAGE READ I/O INTERFACE SO AT45DB642D Completes writing into selected buffer n n+1 Last Byte XXXX XX PA4-0, XXX n = 1st byte read n+1 = 2nd byte read MAIN MEMORY PAGE TO ...
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... SO or I/O7 - I/O0 (OUTPUT) 23.3 Buffer Read Each transition represents 8 bits AT45DB642D 42 ADDRESS FOR BINARY PAGE SIZE A15-A8 A22-A16 A7-A0 PA12-5, PA4-0 BA10-8 BA7-0 CMD BINARY PAGE SIZE A22-A10 + 10 DON'T CARE BITS CMD PA12-5 BINARY PAGE SIZE 14 DON'T CARE + BFA9-BFA0 ...
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... A X MSB MSB OPCODE ADDRESS BITS A23- MSB AT45DB642D DATA BYTE MSB BIT 8191/8447 OF PAGE ...
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... SCK OPCODE MSB HIGH-IMPEDANCE SO 24.6 Buffer Read (Low Frequency: Opcode D1H or D3H SCK MSB HIGH-IMPEDANCE SO AT45DB642D ADDRESS BITS 32 DON'T CARE BITS MSB MSB 6 7 ...
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... MSB OPCODE DON'T CARE MSB AT45DB642D DATA BYTE MSB MSB ...
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... Status Register Read (Opcode D7H SCK SI 1 MSB HIGH-IMPEDANCE SO 24.11 Manufacturer and Device Read (Opcode 9FH) CS SCK SI HIGH-IMPEDANCE SO Note: Each transition AT45DB642D OPCODE STATUS REGISTER DATA MSB ...
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... ADDR ADDR X X CMD HIGH IMPEDANCE ADDRESS BYTES t BINARY & STANDARD SU DATAFLASH PAGE SIZE DUMMY BYTES X CMD X ADDR ADDR t HIGH IMPEDANCE AT45DB642D 25 26 DATA DATA DATA DATA DATA DATA BYTE 1023/1055 BYTE PAGE n PAGE n ...
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... A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. AT45DB642D 48 CS CLK ...
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... MAIN MEMORY PAGE TO BUFFER TRANSFER (53H, 55H) BUFFER WRITE (84H, 87H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) (2) AUTO PAGE REWRITE (58H, 59H) INCREMENT PAGE (2) ADDRESS POINTER END AT45DB642D If planning to modify multiple bytes currently stored within a page of the Flash array 49 ...
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... Parts ordered with suffix SL955 are shipped in tape and reel with the page size set to 1024 bytes. Parts will have a 954 or SL954 marked on them. 28T 28-lead 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) 8CN3 8-pad ( mm) Chip Array Small Outline No Lead Package (CASON) AT45DB642D – ...
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... Orchard Parkway San Jose, CA 95131 R 3542H–DFLASH–4/08 PIN SEATING PLANE A1 TITLE 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) AT45DB642D 0º ~ 5º GAGE PLANE COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A – ...
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... All dimensions and tolerance conform to ASME Y 14.5M, 1994. 2. The surface finish of the package shall be EDM Charmille #24-27. 3. Unless otherwise specified tolerance: Decimal ±0.05, Angular ±2 4. Metal Pad Dimensions. 2325 Orchard Parkway San Jose, CA 95131 R AT45DB642D 52 D Top View Side View Pin1 Pad Corner L1 ...
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... Table 18-4. SCKR SCKF Added additional text for “power of 2” binary page size option. Changed t from 30 µ µs. RDPD Added t and t parameters to Table 18-5. CLKR CLKF Added part number ordering code details for suffixes SL954/955. Added ordering code details. AT45DB642D 53 ...
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... Use Block Erase (opcode 50H alternative. The Block Erase function is not affected by the Chip Erase issue. 30.1.3 Resolution The Chip Erase feature may be fixed with a new revision of the device. Please contact Atmel for the estimated availability of devices with the fix. AT45DB642D 54 3542H–DFLASH–4/08 ...
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