AT91SAM7S32 ATMEL Corporation, AT91SAM7S32 Datasheet
AT91SAM7S32
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AT91SAM7S32 Summary of contents
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... Double PWM Generation, Capture/Waveform Mode, Up/Down Capability ® ® Thumb Processor AT91 ARM Thumb Microcontrollers AT91SAM7S32 Summary Preliminary Note: This is a summary document. A complete document is not available at this time. For more information, please contact your local Atmel sales office. ® ® ...
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... Description AT91SAM7S32 Summary Preliminary 2 Atmel’s AT91SAM7S32 is a member of a series of low pin count Flash microcontrollers based on the 32-bit ARM RISC processor. It features a 32 Kbyte high-speed Flash and an 8 Kbyte SRAM, a large set of peripherals and a complete set of system functions minimizing the number of external components. The device is an ideal migration path for 8-bit microcontroller users looking for additional performance and extended memory ...
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... Block Diagram Figure 1. AT91SAM7S32 Block Diagram TDI TDO TMS TCK JTAGSEL TST FIQ IRQ0 PCK0-PCK2 PLLRC PLL XIN OSC XOUT VDDCORE BOD POR VDDCORE NRST DRXD DTXD RXD0 TXD0 SCK0 RTS0 CTS0 NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK ADTRG AD0 ...
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... Test Mode Select DRXD Debug Receive Data DTXD Debug Transmit Data IRQ0 External Interrupt Input FIQ Fast Interrupt Input PA0 - PA20 Parallel IO Controller A AT91SAM7S32 Summary Preliminary 4 Table 1 gives details on the signal names classified by peripheral. Type Power Power Power Power Power Power Power ...
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... Two-wire Serial Data TWCK Two-wire Serial Clock AD0-AD3 Analog Inputs AD4-AD7 Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference PGMEN0-PGMEN1 Programming Enabling PGMM0-PGMM3 Programming Mode 6071AS–ATARM–20-Oct-04 AT91SAM7S32 Summary Preliminary Active Type I/O I/O Input Output Input Synchronous Serial Controller Output Input I/O I/O I/O I/O Timer/Counter ...
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... Table 1. Signal Description List (Continued) Signal Name Function PGMD0 - PGMD7 Programming Data PGMRDY Programming Ready PGMNVALID Data Direction PGMNOE Programming Read PGMCK Programming Clock PGMNCMD Programming Command AT91SAM7S32 Summary Preliminary 6 Active Type Level Comments I/O Output High Output Low Input Low Input Input Low 6071AS– ...
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... PA20/AD3 24 6071AS–ATARM–20-Oct-04 AT91SAM7S32 Summary Preliminary The AT91SAM7S32 is available in a 48-lead LQFP package. Figure 2 shows the orientation of the 48-lead LQFP package. A detailed mechanical description is given in the section Mechanical Characteristics of the product datasheet. Figure 2. 48-lead LQFP Package Pinout (Top View) ...
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... The AT91SAM7S32 has a static current of less than 60 µA on VDDCORE at 25°C, including the RC oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. Activating the brownout detector adds 20 µA static current ...
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... Typical Powering Schematics 6071AS–ATARM–20-Oct-04 AT91SAM7S32 Summary Preliminary The AT91SAM7S32 supports a 3.3V single supply mode. The internal regulator is con- nected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. Figure 3. 3.3V System Single Power Supply Schematic DC/DC Converter Power Source ranges from 4 ...
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... GND, so that it can be left unconnected for normal operations. The pin TST is used for manufacturing test or fast programming mode of the AT91SAM7S32 when asserted high. The pin TST integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. ...
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... Processor and Architecture ARM7TDMI Processor Debug and Test Features Memory Controller 6071AS–ATARM–20-Oct-04 AT91SAM7S32 Summary Preliminary • RISC processor based on ARMv4T Von Neumann architecture – Runs MHz, providing 0.9 MIPS/MHz • Two instruction sets ® – ARM high-performance 32-bit instruction set ® ...
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... Peripheral Data Controller AT91SAM7S32 Summary Preliminary 12 • Handles data transfer between peripherals and memories • Nine channels – Two for the USART0 – Two for the Debug Unit – Two for the Serial Synchronous Controller – Two for the Serial Peripheral Interface – ...
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... Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0. The AT91SAM7S32 features one bank of 32 Kbytes of Flash. At any time, the Flash is mapped to address 0x0010 0000 also accessible at address 0x0 after the reset and before the Remap Command ...
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... Security Bit Feature AT91SAM7S32 Summary Preliminary 14 The Flash of the AT91SAM7S32 is organized in 256 pages of 128 bytes. The 32,768 bytes are organized in 32-bit words. The Flash contains a 128-byte write buffer, accessible through a 32-bit interface. The Flash benefits from the integration of a power reset cell and from the brownout detector ...
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... Calibration Bits Fast Flash Programming Interface 6071AS–ATARM–20-Oct-04 AT91SAM7S32 Summary Preliminary Two general purpose NVM (GPNVM) bits are used for controlling the brownout detector (BOD), so that even after a power loss, the brownout detector operations remain as defined by the user. These two GPNVM bits can be cleared or set respectively through the commands " ...
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... NRST RCOSC XIN OSC XOUT PLL PLLRC periph_nreset periph_nreset periph_clk[2] dbgu_rxd PA0-PA31 AT91SAM7S32 Summary Preliminary 16 The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. System Controller Advanced fiq Interrupt Controller int MCK dbgu_irq Debug ...
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... FF00 0xFFFF FFFF 6071AS–ATARM–20-Oct-04 AT91SAM7S32 Summary Preliminary The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF. Figure 6 shows the mapping of the System Controller. Note that the Memory Controller configuration user interface is also mapped within this address space ...
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... NRST pin output. It allows to shape a signal on the NRST line, guaranteeing that the length of the pulse meets any requirement. The AT91SAM7S32 embeds a brownout detection circuit and a power-on reset cell. Both are supplied with and monitor VDDCORE. Both signals are provided to the Flash to prevent any code corruption during power-up or power-down sequences or if brown- outs occur on the VDDCORE power supply ...
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... Clock Generator 6071AS–ATARM–20-Oct-04 AT91SAM7S32 Summary Preliminary The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: • RC Oscillator ranges between 22 KHz and 42 KHz • Main Oscillator frequency ranges between 3 and 20 MHz • ...
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... Power Management Controller Advanced Interrupt Controller AT91SAM7S32 Summary Preliminary 20 The Power Management Controller uses the Clock Generator outputs to provide: • the Processor Clock PCK • the Master Clock MCK • all the peripheral clocks, independently controllable • three programmable clock outputs The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating frequency of the device ...
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... Debug Unit Periodic Interval Timer Watchdog Timer Real-time Timer PIO Controller Voltage Regulator Controller 6071AS–ATARM–20-Oct-04 AT91SAM7S32 Summary Preliminary • Fast Forcing – Permits redirecting any interrupt source on the fast interrupt • General Interrupt Mask – Provides processor synchronization on events without triggering an interrupt • ...
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... Peripherals Peripheral Mapping AT91SAM7S32 Summary Preliminary 22 Each peripheral is allocated 16 Kbytes of address space. Figure 9. User Peripheral Mapping 0xF000 0000 Reserved 0xFFF9 FFFF 0xFFFA 0000 TC0, TC1, TC2 0xFFFA 3FFF 0xFFFA 4000 Reserved 0xFFFA FFFF 0xFFFB 0000 Reserved 0xFFFB 3FFF 0xFFFB 4000 Reserved ...
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... RF 6071AS–ATARM–20-Oct-04 AT91SAM7S32 Summary Preliminary The AT91SAM7S32 features one PIO controller, PIOA, that multiplexes the I/O lines of the peripheral set. PIO Controller A controls 21 lines. Each line can be assigned to one of two peripheral functions Some of them can also be multiplexed with the analog inputs of the ADC Controller ...
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... AT91SAM7S32 Summary Preliminary 24 The AT91SAM7S32 embeds a wide range of peripherals. Table 4 defines the Peripheral Identifiers of the AT91SAM7S32. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. ...
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... Two-wire Interface USART Serial Synchronous Controller Timer Counter 6071AS–ATARM–20-Oct-04 AT91SAM7S32 Summary Preliminary • Master Mode only • Compatibility with standard two-wire serial memories • One, two or three bytes for slave address • Sequential read/write operations • Programmable Baud Rate Generator • ...
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... PWM Controller Analog-to-digital Converter AT91SAM7S32 Summary Preliminary 26 • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs, as defined in Table 5 Table 5. Timer Counter Clocks Assignment TC Clock Input TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 – Two multi-purpose input/output signals – ...
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... Ordering Information 6071AS–ATARM–20-Oct-04 AT91SAM7S32 Summary Preliminary Table 6. Ordering Information Ordering Code AT91SAM7S32-AI Temperature Operating Package Range LQFP 48 Industrial (-40°C to 85°C) 27 ...
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... Document Details Title Literature Number Revision History Version A AT91SAM7S32 Summary Preliminary 28 AT91SAM7S32 6071S Publication Date: 20-Oct-04 6071AS–ATARM–20-Oct-04 ...
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... Fax: (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...