AT91SAM7X256-AU-001 ATMEL Corporation, AT91SAM7X256-AU-001 Datasheet
AT91SAM7X256-AU-001
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AT91SAM7X256-AU-001 Summary of contents
Page 1
... Embedded ICE In-circuit Emulation, Debug Communication Channel Support • Internal High-speed Flash – 256 Kbytes (AT91SAM7X256) Organized in 1024 Pages of 256 Bytes – 128 Kbytes (AT91SAM7X128) Organized in 512 Pages of 256 Bytes – Single Cycle Access MHz in Worst Case Conditions – ...
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... VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply – 1.8V VDDCORE Core Power Supply with Brownout Detector • Fully Static Operation MHz at 1.65V and 85 C Worst Case Conditions • Available in a 100-lead LQFP Green Package AT91SAM7X256/128 Preliminary 2 6120A–ATARM–01-Sep-05 ...
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... Description Atmel's AT91SAM7X256/128 is a member of a series of highly integrated Flash microcontrollers based on the 32-bit ARM RISC processor. It features 256/128 Kbyte high-speed Flash and 64/32 Kbyte SRAM, a large set of peripherals, including an 802.3 Ethernet MAC, a CAN control- ler, an AES 128 Encryption accelerator and a Triple Data Encryption System. A complete set of system functions minimizes the number of external components ...
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... AT91SAM7X256/128 Block Diagram Figure 3-1. JTAGSEL IRQ0-IRQ1 PCK0-PCK3 VDDCORE VDDFLASH VDDCORE SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK AT91SAM7X256/128 Preliminary 4 AT91SAM7X256/X128 Block Diagram TDI TDO ICE JTAG TMS SCAN TCK System Controller TST FIQ AIC ...
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... DTXD Debug Transmit Data IRQ0 - IRQ1 External Interrupt Inputs FIQ Fast Interrupt Input PA0 - PA30 Parallel IO Controller A PB0 - PB30 Parallel IO Controller B 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Active Type Power Power Power Power Power Power Power Ground Clocks, Oscillators and PLLs ...
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... Master In Slave Out SPIx_MOSI Master Out Slave In SPIx_SPCK SPI Serial Clock SPIx_NPCS0 SPI Peripheral Chip Select 0 SPIx_NPCS1-NPCS3 SPI Peripheral Chip Select TWD Two-wire Serial Data TWCK Two-wire Serial Clock AT91SAM7X256/128 Preliminary 6 Type USB Device Port Analog Analog USART I/O I/O Input Output Input Input ...
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... Receive Error ECRS Carrier Sense ECOL Collision Detected EMDC Management Data Clock EMDIO Management Data Input/Output EF100 Force 100 Mbits/sec. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Type Analog-to-Digital Converter Analog Analog Input Analog Fast Flash Programming Interface Input Input I/O Output ...
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... Package The AT91SAM7X256/128 is available in 100-lead LQFP package. 5.1 100-lead LQFP Mechanical Overview Figure 5-1 tion is given in the Mechanical Characteristics section of the full datasheet. Figure 5-1. 5.2 AT91SAM7X256/128 Pinout Table 5-1. Pinout in 100-lead TQFP Package 1 ADVREF 26 2 GND 27 3 AD4 28 4 AD5 29 5 AD6 30 6 AD7 31 7 VDDOUT ...
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... Power Consumption The AT91SAM7X256/128 has a static current of less than 60 µA on VDDCORE at 25°C, includ- ing the RC oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. Activating the brownout detector adds 28 µA static current. ...
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... Typical Powering Schematics The AT91SAM7X256/128 supports a 3.3V single supply mode. The internal regulator input con- nected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. the power schematics to be used for USB bus-powered systems. Figure 6-1. AT91SAM7X256/128 Preliminary 10 3.3V System Single Power Supply Schematic ...
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... AT91SAM7X256/128 when asserted high. The TST pin integrates a permanent pull-down resis- tor of about GND, so that it can be left unconnected for normal operations ...
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... The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive permanently. The remaining I/O lines can draw only 8 mA. However, the total current drawn by all the I/O lines cannot exceed 200 mA. AT91SAM7X256/128 Preliminary 12 6120A–ATARM–01-Sep-05 ...
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... Abort generation in case of misalignment • Remap Command – Remaps the SRAM in place of the embedded non-volatile memory – Allows handling of dynamic exception vectors 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary ® high-performance 32-bit instruction set ® high code density 16-bit instruction set ...
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... Low bus arbitration overhead – One Master Clock cycle needed for a transfer from memory to peripheral – Two Master Clock cycles needed for a transfer from peripheral to memory • Next Pointer management for reducing interrupt latency requirements AT91SAM7X256/128 Preliminary 14 wait states to-digital Converter ...
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... Full chip erase time – 10,000 write cycles, 10-year data retention capability – 8 lock bits, each protecting 8 sectors of 64 pages – Protection Mode to secure contents of the Flash • 32 Kbytes of Fast SRAM – Single-cycle access at full speed 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary 15 ...
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... After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0. 9.3.2 Internal ROM The AT91SAM7X256/128 embeds an Internal ROM. At any time, the ROM is mapped at address 0x30 0000. The ROM contains FFPI and SAM-BA program. 9.3.3 Internal Flash • ...
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... Embedded Flash 9.4.1 Flash Overview • The Flash of the AT91SAM7X256 is organized in 1024 pages of 256 bytes. It reads as 65,536 32-bit words. • The Flash of the AT91SAM7X128 is organized in 512 pages of 256 bytes. It reads as 32,768 32-bit words. The Flash contains a 256-byte write buffer, accessible through a 32-bit interface. ...
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... Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. 9.4.4 Security Bit Feature The AT91SAM7X256/128 features a security bit, based on a specific NVM-Bit. When the secu- rity is enabled, any access to the Flash, either through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code pro- grammed in the Flash. This security bit can only be enabled, through the Command “ ...
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... Communication via the USB Device Port is limited to an 18.432 MHz crystal. The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when the GPNVM Bit 2 is set to 0. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary 19 ...
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... System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. Figure 10-1. System Controller Block Diagram NRST XIN XOUT PLLRC PA0-PA30 PB0-PB30 AT91SAM7X256/128 Preliminary 20 System Controller irq0-irq1 Advanced fiq Interrupt Controller periph_irq[2..19] pit_irq rtt_irq ...
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... FD4F 0xFFFF FD60 0xFFFF FC6F 0xFFFF FD70 0xFFFF FEFF 0xFFFF FF00 0xFFFF FFFF 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary shows the mapping of the System Controller. Note that the Memory Controller con- Peripheral Peripheral Name AIC Advanced Interrupt Controller DBGU Debug Unit ...
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... Brownout Detector and Power-on Reset The AT91SAM7X256/X128 embeds one brownout detection circuit and a power-on reset cell. The power-on reset is supplied with and monitors VDDCORE. Both signals are provided to the Flash to prevent any code corruption during power-up or power- down sequences or if brownouts occur on the power supplies. ...
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... Main Oscillator frequency ranges between 3 and 20 MHz • Main Oscillator can be bypassed • PLL output ranges between 80 and 220 MHz It provides SLCK, MAINCK and PLLCK. Figure 10-3. Clock Generator Block Diagram 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Clock Generator Embedded Slow Clock RC SLCK ...
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... Other sources control the peripheral interrupts or external interrupts – Programmable edge-triggered or level-sensitive internal sources – Programmable positive/negative edge-triggered or high/low level-sensitive external • 8-level Priority Controller – Drives the normal interrupt nIRQ of the processor – Handles priority of the interrupt sources AT91SAM7X256/128 Preliminary 24 Master Clock Controller SLCK Prescaler MAINCK /1,/2,/4, ...
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... Offers visibility of COMMRX and COMMTX signals from the ARM Processor • Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of – Chip ID is 0x271B 0940 (VERSION 0) for AT91SAM7X256 – Chip ID is 0x271A 0740 (VERSION 0) for AT91SAM7X128 10.7 Period Interval Timer • ...
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... Synchronous output, provides Set and Clear of several I/O lines in a single write 10.11 Voltage Regulator Controller The purpose of this controller is to select the Power Mode of the Voltage Regulator between Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set). AT91SAM7X256/128 Preliminary 26 6120A–ATARM–01-Sep-05 ...
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... Peripherals 11.1 Peripheral Mapping Each peripheral is allocated 16 Kbytes of address space. Figure 11-1. User Peripheral Mapping 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary 0xF000 0000 Reserved 0xFFF9 FFFF 0xFFFA 0000 TC0, TC1, TC2 0xFFFA 3FFF 0xFFFA 4000 AES 128 0xFFFA 7FFF 0xFFFA 8000 TDES 0xFFFA BFFF ...
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... Peripheral Multiplexing on PIO Lines The AT91SAM7X256/128 features two PIO controllers, PIOA and PIOB, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls 31 lines. Each line can be assigned to one of two peripheral func- tions Some of them can also be multiplexed with the analog inputs of the ADC Controller ...
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... PA21 TF PA22 TK PA23 TD PA24 RD PA25 RK PA26 RF PA27 DRXD PA28 DTXD PA29 FIQ PA30 IRQ0 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Peripheral B Comments High-Drive High-Drive SPI1_NPCS1 High-Drive SPI1_NPCS2 High-Drive SPI1_NPCS3 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 PCK1 IRQ1 TCLK2 SPI1_NPCS0 SPI1_SPCK SPI1_MOSI SPI1_MISO SPI1_NPCS1 SPI1_NPCS2 ...
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... PB21 PWM2 PB22 PWM3 PB23 TIOA0 PB24 TIOB0 PB25 TIOA1 PB26 TIOB1 PB27 TIOA2 PB28 TIOB2 PB29 PCK1 PB30 PCK2 AT91SAM7X256/128 Preliminary 30 Peripheral B Comments PCK0 SPI1_NPCS1 SPI1_NPCS2 TCLK0 SPI0_NPCS1 SPI0_NPCS2 SPI1_NPCS3 SPI0_NPCS3 ADTRG TCLK1 PCK0 PCK1 PCK2 DCD1 DSR1 DTR1 RI1 ...
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... Peripheral Identifiers The AT91SAM7X256/128 embeds a wide range of peripherals. eral Identifiers of the AT91SAM7X256/128. Unique peripheral identifiers are defined for both the Advanced Interrupt Controller and the Power Management Controller. Table 11-3. Peripheral 20-29 30 ...
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... Programmable delay between consecutive transfers – Selectable mode fault detection – Maximum frequency Master Clock 11.8 Two-wire Interface • Master Mode only • Compatibility with standard two-wire serial memories AT91SAM7X256/128 Preliminary 32 peripherals Sensors between clock and data ® and 3-wire EEPROMs ...
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... Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 11.11 Timer Counter • Three 16-bit Timer Counter Channels – Three output compare or two input capture • Wide range of functions including: – Frequency measurement – Event counting – Interval measurement – Pulse generation 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary 33 ...
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... Endpoint 0: 8 bytes – Endpoint 1 and 2: 64 bytes ping-pong – Endpoint 3: 64 bytes – Endpoint 4 and 5: 256 bytes ping-pong – Ping-pong Mode (two memory banks) for bulk endpoints • Suspend/resume logic AT91SAM7X256/128 Preliminary 34 Table 11-4 Timer Counter Clocks Assignment Clock MCK/2 ...
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... Triple Data Encryption Standard • Single Data Encryption Standard (DES) and Triple Data Encryption • Algorithm (TDEA or TDES) supports • Compliant with FIPS Publication 46-3, Data Encryption Standard (DES) • 64-bit Cryptographic Key • Two-key or Three-key Algorithms 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary 35 ...
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... Timer Counter outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all • Four of eight analog inputs shared with digital signals AT91SAM7X256/128 Preliminary 36 enabled channels 6120A–ATARM–01-Sep-05 ...
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... Two Instruction Sets – ARM – Thumb • Three-Stage Pipeline Architecture – Instruction Fetch (F) – Instruction Decode (D) – Execute (E) 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary ® High-performance 32-bit Instruction Set ® High Code Density 16-bit Instruction Set ® ® and 16-bit Thumb ...
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... At any one time 16 registers are visible to the user. The remainder are synonyms used to speed up exception processing. Register 15 is the Program Counter (PC) and can be used in all instructions to reference data relative to the current instruction. R14 holds the return address after a subroutine call. R13 is used (by software convention stack pointer. AT91SAM7X256/128 Preliminary 38 6120A–ATARM–01-Sep-05 ...
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... R13 is banked across exception modes to provide each exception handler with a private stack pointer. The fast interrupt mode also banks registers that interrupt processing can begin with- out having to save these registers. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary ARM7TDMI ARM Modes and Registers Layout Supervisor Mode Abort Mode ...
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... Coprocessor instructions • Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bit[31:28]). Table 12-2 AT91SAM7X256/128 Preliminary 40 supports five types of exception and a privileged processing mode for each type. gives the ARM instruction mnemonic list. 6120A–ATARM–01-Sep-05 ...
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... In Thumb mode, eight general-purpose registers R7, are available that are the same physical registers when executing ARM instructions. Some Thumb instructions also access to the Program Counter (ARM Register 15), the Link Register (ARM Register 14) and the 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary ARM Instruction Mnemonic List Operation Move ...
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... TST AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH AT91SAM7X256/128 Preliminary 42 gives the Thumb instruction mnemonic list. Thumb Instruction Mnemonic List Operation Move Add Subtract Compare Test Logical AND Logical Exclusive OR Logical Shift Left Arithmetic Shift Right ...
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... A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment. 13.2 Block Diagram Figure 13-1. Debug and Test Block Diagram Boundary TAP ARM7TDMI PDC 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary ICE/JTAG TAP Reset ICE and Test DBGU TMS TCK ...
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... Application Examples 13.3.1 Debug Environment Figure 13-2 standard debugging functions, such as downloading code and single-stepping through the program. Figure 13-2. Application Debug Environment Example AT91SAM7X256/128 Preliminary 44 shows a complete debug environment example. The ICE/JTAG interface is used for ICE/JTAG Interface ICE/JTAG Connector RS232 AT91SAM7Xxx Connector AT91SAM7Xxx-based Application Board ...
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... NRST TST TCK TDI TDO TMS JTAGSEL DRXD DTXD 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary shows a test environment example. Test vectors are sent and interpreted by the Test Adaptor JTAG Interface ICE/JTAG Chip n Connector AT91SAM7Xxx AT91SAM7Xxx-based Application Board In Test Debug and Test Pin List ...
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... A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The AT91SAM7X256 Debug Unit Chip ID value is 0x271B 0940 on 32-bit width. The AT91SAM7X128 Debug Unit Chip ID value is 0x271A 0740 on 32-bit width. For further details on the Debug Unit, see the Debug Unit section. ...
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... The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. Table 13-2. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary AT91SAM7X JTAG Boundary Scan Register Bit Number Pin Name ...
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... Table 13-2. Number AT91SAM7X256/128 Preliminary 48 AT91SAM7X JTAG Boundary Scan Register (Continued) Bit Pin Name 163 162 PA7/SCK1/SPI0_NPCS1 161 160 ERASE 159 158 PB27/TIOA2/PWM0/AD0 157 156 155 PB28/TIOB2/PWM1/AD1 154 153 152 PB29/PCK1/PWM2/AD2 151 150 149 PB30/PCK2/PWM3/AD3 148 147 146 PA8/RTS1/SPI0_NPCS2 145 144 143 ...
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... Table 13-2. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary AT91SAM7X JTAG Boundary Scan Register (Continued) Bit Number Pin Name 129 128 PA14/SPI0_NPCS2/IRQ1 127 126 125 PA15/SPI0_NPCS3/TCLK2 124 123 122 PA16/SPI0_MISO 121 120 119 PA17/SPI0_MOSI 118 117 116 PA18/SPI0_SPCK 115 114 113 PB9/EMDIO 112 ...
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... Table 13-2. Number AT91SAM7X256/128 Preliminary 50 AT91SAM7X JTAG Boundary Scan Register (Continued) Bit Pin Name 96 95 PB15/ERXDV/ECRSDV PB17/ERXCK/SPI0_NPCS3 PB7/ERXER PB12/ETXER/TCLK0 PB0/ETXCK/EREFCK/PCK0 PB1/ETXEN PB2/ETX0 PB3/ETX1 PB10/ETX2/SPI1_NPCS1 PB11/ETX3/SPI1_NPCS2 PA19/CANRX 64 Associated BSR Pin Type Cells INPUT ...
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... Table 13-2. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary AT91SAM7X JTAG Boundary Scan Register (Continued) Bit Number Pin Name 63 62 PA20/CANTX PA21/TF/SPI1_NPCS0 PA22/TK/SPI1_SPCK PB16/ECOL/SPI1_NPCS3 PB4/ECRS PA23/TD/SPI1_MOSI PA24/RD/SPI1_MISO PA25/RK/SPI1_NPCS1 PA26/RF/SPI1_NPCS2 ...
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... Table 13-2. Number AT91SAM7X256/128 Preliminary 52 AT91SAM7X JTAG Boundary Scan Register (Continued) Bit Pin Name 30 29 PB20/PWM1/PCK0 PB21/PWM2/PCK2 PB22/PWM3/PCK2 PB23/TIOA0/DCD1 PB24/TIOB0/DSR1 PB25/TIOA1/DTR1 PB26/TIOB1/RI1 PA27DRXD/PCK3 PA28/DTXD PA29/FIQ/SPI1_NPCS3 1 Associated BSR Pin Type Cells INPUT IN/OUT OUTPUT ...
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... Set to 0x0. • PART NUMBER[27:12]: Product Part Number AT91SAM7X256: 0x5B10 AT91SAM7X128: 0x5B0F • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. AT91SAM7X256: JTAG ID Code value is 05B1_003F AT91SAM7X128: JTAG ID Code value is 05B0_F03F 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary ...
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... AT91SAM7X256/128 Preliminary 54 6120A–ATARM–01-Sep-05 ...
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... The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. A brownout detection is also available to prevent the processor from falling into an unpredictable state. 14.2 Block Diagram Figure 14-1. Reset Controller Block Diagram 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Reset Controller bod_rst_en Brownout Manager brown_out Main Supply Startup ...
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... The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts AT91SAM7X256/128 Preliminary 56 Figure 14-2 shows the block diagram of the NRST Manager. ...
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... The bit BODSTS can trigger an interrupt if the bit BODIEN is set in the RSTC_MR. At factory, the brownout reset is disabled. Figure 14-3. Brownout Manager 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs bod_rst_en RSTC_SR brown_out ...
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... When VDDCORE is detected low by the Main Supply POR Cell, all reset signals are asserted immediately. Figure 14-4. Power-up Reset SLCK MCK Main Supply POR output proc_nreset periph_nreset NRST (nrst_out) AT91SAM7X256/128 Preliminary 58 Figure 14-4, is hardcoded to comply with the Slow Clock Oscillator Startup Time Processor Startup = 3 cycles EXTERNAL RESET LENGTH = 2 cycles Any Freq. ...
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... Figure 14-5. User Reset State SLCK MCK NRST Resynch. 2 cycles proc_nreset RSTTYP periph_nreset NRST (nrst_out) 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Any Freq. Any >= EXTERNAL RESET LENGTH Resynch ...
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... Brownout Reset. Figure 14-6. Brownout Reset State SLCK MCK Any Freq. brown_out or bod_reset proc_nreset RSTTYP Any periph_nreset NRST (nrst_out) AT91SAM7X256/128 Preliminary 60 Resynch. Processor Startup 2 cycles = 3 cycles XXX EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 0x5 = Brownout Reset 6120A–ATARM–01-Sep-05 ...
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... Progress) is set in the Status Register (RSTC_SR cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. Figure 14-7. Software Reset 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary SLCK Any MCK Freq. ...
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... WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. Figure 14-8. Watchdog Reset Only if WDRPROC = 0 AT91SAM7X256/128 Preliminary 62 SLCK Any MCK Freq. wd_fault ...
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... BODSTS bit: This bit indicates a brownout detection when the brownout reset is disabled (bod_rst_en = 0). It triggers an interrupt if the bit BODIEN in the RSTC_MR register enables the interrupt. Reading the RSTC_SR register resets the BODSTS bit and clears the interrupt. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary proc_nreset signal. Figure 63 ...
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... Figure 14-9. Reset Controller Status and Interrupt MCK Peripheral Access 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) AT91SAM7X256/128 Preliminary 64 read RSTC_SR 2 cycle resynchronization 6120A–ATARM–01-Sep-05 ...
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... Reset Controller (RSTC) User Interface Table 14-1. Reset Controller (RSTC) Register Mapping Offset Register 0x00 Control Register 0x04 Status Register 0x08 Mode Register 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR Read/Write Reset Value - 0x0000_0000 0x0000_0000 65 ...
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... If KEY is correct, resets the peripherals. • EXTRST: External Reset effect KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM7X256/128 Preliminary KEY ...
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... SRCMP: Software Reset Command in Progress software command is being performed by the reset controller. The reset controller is ready for a software command software reset command is being performed by the reset controller. The reset controller is busy. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary – ...
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... This field defines the external reset length. The external reset is asserted during a time of 2 allows assertion duration to be programmed between 60 µs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM7X256/128 Preliminary ...
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... Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary 0 RTT_SR RTTRST 1 ...
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... Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. Figure 15-2. RTT Counting MCK RTPRES - 1 Prescaler 0 RTT RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface AT91SAM7X256/128 Preliminary 70 APB cycle ... 0 ALMV-1 ALMV APB cycle ALMV+1 ALMV+2 ALMV+3 read RTT_SR 6120A– ...
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... Real-time Timer (RTT) User Interface Table 15-1. Real-time Timer (RTT) Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Name Access RTT_MR Read/Write RTT_AR Read/Write RTT_VR Read-only RTT_SR Read-only Reset Value 0x0000_8000 0xFFFF_FFFF ...
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... RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. AT91SAM7X256/128 Preliminary – ...
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... Defines the alarm value (ALMV+1) compared with the Real-time Timer. 15.4.3 Real-time Timer Value Register Register Name: RTT_VR Access Type: Read-only • CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary ALMV ALMV ALMV ALMV 29 ...
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... The Real-time Alarm occurred since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR The Real-time Timer has been incremented since the last read of the RTT_SR. AT91SAM7X256/128 Preliminary – ...
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... Block Diagram Figure 16-1. Periodic Interval Timer 0 MCK 20-bit Counter MCK/16 CPIV Prescaler CPIV 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary PIT_MR PIV = ? 0 1 PIT_PIVR PIT_PIIR set 0 PIT_SR PITS reset 0 ...
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... PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. AT91SAM7X256/128 Preliminary 76 Figure 16-2 illustrates 6120A– ...
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... Figure 16-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary MCK 1 PIV - 1 PIV 0 read PIT_PIVR APB cycle APB cycle restarts MCK Prescaler ...
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... Periodic Interval Timer (PIT) User Interface Table 16-1. Periodic Interval Timer (PIT) Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register AT91SAM7X256/128 Preliminary 78 Name Access PIT_MR Read/Write PIT_SR Read-only PIT_PIVR Read-only PIT_PIIR Read-only Reset Value ...
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... PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary – – ...
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... PICNT • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. AT91SAM7X256/128 Preliminary PICNT ...
Page 81
... Block Diagram Figure 17-1. Watchdog Timer Block Diagram write WDT_MR WDT_CR WDRSTT WDT_MR read WDT_SR or reset 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary WDT_MR WV reload 1 0 12-bit Down Counter Current WDD Value <= WDD ...
Page 82
... Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR. AT91SAM7X256/128 Preliminary 82 6120A–ATARM–01-Sep-05 ...
Page 83
... Figure 17-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Watchdog Error WDT_CR = WDRSTT Watchdog Underflow if WDRSTEN WDRSTEN ...
Page 84
... WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM7X256/128 Preliminary 84 Name WDT_CR WDT_MR WDT_SR KEY – ...
Page 85
... WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state. • WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary 29 28 WDDBGHLT 21 20 WDD ...
Page 86
... No Watchdog underflow occurred since the last read of WDT_SR least one Watchdog underflow occurred since the last read of WDT_SR. • WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR least one Watchdog error occurred since the last read of WDT_SR. AT91SAM7X256/128 Preliminary – ...
Page 87
... Mode Register. Its offset is 0x60 with respect to the System Controller offset. This register controls the Voltage Regulator Mode. Setting PSTDBY (bit 0) puts the Voltage Regulator in Standby Mode or Low-power Mode. On reset, the PSTDBY is reset wake up the Voltage Regulator in Normal Mode. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary 87 ...
Page 88
... PSTDBY: Periodic Interval Value 0 = Voltage regulator in normal mode Voltage regulator in standby mode (low-power mode). AT91SAM7X256/128 Preliminary 88 Name VREG_MR – – – – – – – ...
Page 89
... Embedded Flash Controller. 19.2 Block Diagram Figure 19-1. Memory Controller Block Diagram ARM7TDMI Processor Abort EMAC DMA Peripheral DMA Controller 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Memory Controller ASB Abort Status Misalignment Bus Detector Arbiter User Interface APB Bridge Peripheral 0 ...
Page 90
... One 256-Mbyte address space reserved for the embedded peripherals • An undefined address space of 3584M bytes representing fourteen 256-Mbyte areas that return an Abort if accessed Figure 19-2 Figure 19-2. Memory Areas AT91SAM7X256/128 Preliminary 90 shows the assignment of the 256-Mbyte memory areas. 0x0000 0000 256M Bytes ...
Page 91
... The Remap Command can be cancelled by writing the MC_RCR RCB field to one, which acts as a toggling command. This allows easy debug of the user-defined boot sequence by offering a simple way to put the chip in the same configuration as after a reset. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary 0x0000 0000 Internal Memory Area 0 0x000F FFFF ...
Page 92
... Note that the accesses of the ARM processor when it is fetching instructions are not checked. The misalignments are generally due to software bugs leading to wrong pointer handling. These bugs are particularly difficult to detect in the debug phase. AT91SAM7X256/128 Preliminary 92 19-1. 6120A–ATARM–01-Sep-05 ...
Page 93
... As the requested address is saved in the Abort Status Register and the address of the instruc- tion generating the misalignment is saved in the Abort Link Register of the processor, detection and fix of this kind of software bugs is simplified. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary 93 ...
Page 94
... Offset Register 0x00 MC Remap Control Register 0x04 MC Abort Status Register 0x08 MC Abort Address Status Register 0x10-0x5C Reserved 0x60 EFC Configuration Registers AT91SAM7X256/128 Preliminary 94 Name Access MC_RCR Write-only MC_ASR Read-only MC_AASR Read-only See Section 20. ”Embedded Flash Controller (EFC)”, on page 99 Reset State ...
Page 95
... RCB: Remap Command Bit 0: No effect. 1: This Command Bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of the page zero memory devices. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary – – – – ...
Page 96
... ABTTYP: Abort Type Status ABTTYP • MST_EMAC: EMAC Abort Source 0: The last aborted access was not due to the EMAC. 1: The last aborted access was due to the EMAC. AT91SAM7X256/128 Preliminary – – – – – ...
Page 97
... SVMST_ARM: Saved ARM Abort Source 0: No abort due to the ARM occurred since the last read of MC_ASR notified in the bit MST_ARM least one abort due to the ARM occurred since the last read of MC_ASR. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary 97 ...
Page 98
... MC Abort Address Status Register Register Name: MC_AASR Access Type: Read-only Reset Value: 0x0 Offset: 0x08 • ABTADD: Abort Address This field contains the address of the last aborted access. AT91SAM7X256/128 Preliminary ABTADD ABTADD ABTADD ABTADD 26 ...
Page 99
... GP NVM assignment. The Embedded Flash size, the page size and the lock region organization are described in the product definition section. Table 20-1. AT91SAM7X256 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Product Specific Lock and General-purpose NVM Bits AT91SAM7X128 ” ...
Page 100
... The Flash memory is accessible through 8-, 16- and 32-bit reads. As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded Flash wraps around the address space and appears to be repeated within it. AT91SAM7X256/128 Preliminary 100 Flash Memory ...
Page 101
... Flash Access Buffer (32 bits) Data To ARM Note: When FWS is equal case of sequential reads, all the accesses are performed in a single-cycle access (except for the first one). 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary @Byte 8 @Byte 4 @Byte 6 Bytes 4-7 Bytes 8-11 Bytes 4-7 Bytes 0-3 ...
Page 102
... Flash erasing. Table 20-2. Command Write page Set Lock Bit Write Page and Lock Clear Lock Bit Erase all Set General-purpose NVM Bit Clear General-purpose NVM Bit Set Security Bit AT91SAM7X256/128 Preliminary 102 3 Wait State Cycles 3 Wait State Cycles @ Bytes 4-7 Bytes 0-3 0-1 2-3 ...
Page 103
... When the current command writes or erases a page in a locked region, the command has no effect on the whole memory plane; however, the LOCKE flag is set in the MC_FSR register. This flag is automatically cleared by a read access to the MC_FSR register. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary 103 ...
Page 104
... The Flash technology requires that an erase must be done before programming. The entire memory plane can be erased at the same time page can be automatically erased by clear- ing the NEBP bit in the MC_FMR register before writing the command in the MC_FCR register. AT91SAM7X256/128 Preliminary 104 Read Status: MC_FSR ...
Page 105
... Programming Error: A bad keyword and/or an invalid command have been written in the MC_FCR register. • Lock Error: The page to be programmed belongs to a locked region. A command must be previously run to unlock the corresponding region. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Figure 20-6). 32 bits wide FF ...
Page 106
... If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. A programming error, where a bad keyword and/or an invalid command have been written in the MC_FCR register, may be detected in the MC_FSR register after a programming sequence. AT91SAM7X256/128 Preliminary 106 6120A–ATARM–01-Sep-05 ...
Page 107
... ERASE request to the chip. Refer to the product definition 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Access to the Flash in Read Mode is permitted when a Lock or Unlock command is performed. Access to the Flash in read mode is permitted when a Set, Clear or Get General-purpose NVM Bit command is performed ...
Page 108
... When the locking completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. When the security bit is active, the SECURITY bit in the MC_FSR is set. AT91SAM7X256/128 Preliminary 108 6120A–ATARM–01-Sep-05 ...
Page 109
... Embedded Flash Controller (EFC) Register Mapping Offset Register 0x60 MC Flash Mode Register 0x64 MC Flash Command Register 0x68 MC Flash Status Register 0x6C Reserved 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Name Access MC_FMR Read/Write MC_FCR Write-only MC_FSR Read-only – – Reset State 0x0 – ...
Page 110
... When writing the rest of the Flash, this field defines the number of Master Clock cycles in 1.5 microseconds. This number must be rounded up. Warning: The value 0 is only allowed for a master clock period superior to 30 microseconds. Warning: In order to guarantee valid operations on the flash memory, the field Flash Microsecond Cycle Number (FMCN) must be correctly programmed. AT91SAM7X256/128 Preliminary 110 – ...
Page 111
... FCMD: Flash Command This field defines the Flash commands: FCMD 0000 0001 0010 0011 0100 1000 1011 1101 1111 Others 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary KEY – – – PAGEN – – ...
Page 112
... KEY: Write Protection Key This field should be written with the value 0x5A to enable the command defined by the bits of the register. If the field is writ- ten with a different value, the write is not performed and no action is started. AT91SAM7X256/128 Preliminary 112 PAGEN Description PAGEN defines the page number to be written. ...
Page 113
... The corresponding lock region is locked MC_FSR, LOCKSx Product Specific Map AT91SAM7X256 AT91SAM7X128 16 8 LOCKS0 LOCKS0 LOCKS1 LOCKS1 LOCKS2 LOCKS2 LOCKS3 LOCKS3 LOCKS4 LOCKS4 LOCKS5 LOCKS5 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary 29 28 LOCKS13 LOCKS12 LOCKS11 21 20 LOCKS5 LOCKS4 LOCKS3 13 12 – – – SECURITY ...
Page 114
... LOCKS12 – LOCKS13 – LOCKS14 – LOCKS15 – AT91SAM7X256/128 Preliminary 114 Denomination Lock Region 6 Lock Status Lock Region 7 Lock Status Lock Region 8 Lock Status Lock Region 9 Lock Status Lock Region 10 Lock Status Lock Region 11 Lock Status Lock Region 12 Lock Status ...
Page 115
... Parallel Fast Flash Programming 21.2.1 Device Configuration In Fast Flash Programming Mode, the device specific test mode. Only a certain set of pins is significant. Other pins must be left unconnected. Figure 21-1. Parallel Programming Interface 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary TST VDDIO VDDIO PGMEN0 VDDIO PGMEN1 ...
Page 116
... Specifies DATA type (See PGMD[15:0] Bi-directional data bus 21.2.2 Signal Names Depending on the MODE settings, DATA is latched in different internal registers. Table 21-2. MODE[3:0] 0000 0001 0010 0011 0100 0101 Default AT91SAM7X256/128 Preliminary 116 Type Power Power Power Power Power Ground Clocks Input Test Input Input Input ...
Page 117
... An handshake is defined for read and write operations. When the device is ready to start a new operation (RDY signal set), the programmer starts the handshake by clearing the NCMD signal. The handshaking is achieved once NCMD signal is high and RDY is high. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Command Bit Coding Symbol READ ...
Page 118
... Clears NCMD signal 3 Waits for RDY low 4 Releases MODE and DATA signals 5 Sets NCMD signal 6 Waits for RDY high 21.2.4.2 Read Handshaking For details on the read handshaking sequence, refer to AT91SAM7X256/128 Preliminary 118 NCMD 2 3 RDY NOE NVALID DATA[15:0] 1 MODE[3:0] Device Action Waits for NCMD low ...
Page 119
... Table 21-3 on page face running several read/write handshaking sequences. When a new command is executed, the previous one is automatically achieved. Thus, chaining a read command after a write automatically flushes the load buffer in the Flash. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Parallel Programming Timing, Read Sequence NCMD 2 3 ...
Page 120
... CMDE) The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. Table 21-7. Step AT91SAM7X256/128 Preliminary 120 Read Command Handshake Sequence MODE[3:0] Write handshaking CMDE Write handshaking ADDR0 Write handshaking ADDR1 ...
Page 121
... When bit 0 of the bit mask is set, then the first lock bit is activated. In the same way, the Clear Lock command (CLB) is used to clear lock bits. All the lock bits are also cleared by the EA command. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Write Command (Continued) Handshake Sequence MODE[3:0] Write handshaking DATA ...
Page 122
... General-purpose NVM bits can be read using the Get Fuse Bit command (GFB). The n NVM bit is active when bit n of the bit mask is set.. Table 21-12. Get GP NVM Bit Command Step 1 2 AT91SAM7X256/128 Preliminary 122 Set and Clear Lock Bit Command Handshake Sequence Write handshaking Write handshaking ...
Page 123
... This command is used to perform a write access to any memory location. The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Handshake Sequence Write handshaking Write handshaking Handshake Sequence ...
Page 124
... Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 21-16. Get Version Command Step 1 2 AT91SAM7X256/128 Preliminary 124 Handshake Sequence MODE[3:0] Write handshaking CMDE Write handshaking ADDR0 Write handshaking ADDR1 Write handshaking ADDR2 Write handshaking ...
Page 125
... Core Power Supply VDDPLL PLL Power Power Supply GND Ground Main Clock Input. This input can be tied to GND. In this XIN case, the device is clocked by the internal RC oscillator. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary TST VDDIO VDDIO PGMEN0 VDDIO PGMEN1 GND PGMEN2 TDI TDO ...
Page 126
... Shift 0x2 into the DR register ( bits long, LSB first) without going through the Run- Test-Idle state. • Shift 0xC into the IR register ( bits long, LSB first) without going through the Run-Test- Idle state. Note: Table 21-18. Reset TAP controller and go to Select-DR-Scan AT91SAM7X256/128 Preliminary 126 Type Test Input Input ...
Page 127
... Debug Comms Registers. 21.3.4.1 Flash Read Command This command is used to read the Flash contents. The memory map is accessible through this command. Memory is seen as an array of words (32-bit wide). The read command can start at 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary r/w Address ...
Page 128
... Flash Erase Page and Write command (EWP) is equivalent to the Flash Write Command. How- ever, before programming the load buffer, the page is erased. Flash Erase Page and Write the Lock command (EWPL) combines EWP and WPL commands. AT91SAM7X256/128 Preliminary 128 DR Data (Number of Words to Read) << READ ...
Page 129
... In the same way, the Clear Fuse command (CFB) is used to clear GP NVM bits. All the general- purpose NVM bits are also cleared by the EA command. Table 21-24. Set and Clear General-purpose NVM Bit Command Read/Write Write Write 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary DR Data EA DR Data SLB or CLB Bit Mask DR Data ...
Page 130
... This command is used to perform a write access to any memory location. The Memory Wrire command (WRAM) is optimized for consecutive writes. An internal address buffer is automatically increased. Table 21-28. Write Command Read/Write Write Write Write AT91SAM7X256/128 Preliminary 130 DR Data GFB Bit Mask DR Data SSE DR Data (Number of Words to Read) << RRAM ...
Page 131
... Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 21-29. Get Version Command Read/Write Write Read 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary DR Data Memory [address+4] Memory [address+8] Memory [address+(Number of Words to Write - 1 Data GVE Version ...
Page 132
... AT91SAM7X256/128 Preliminary 132 6120A–ATARM–01-Sep-05 ...
Page 133
... Disable of the Watchdog and enable of the user reset 10. Initialization of the USB Device Port 11. Jump to SAM-BA Boot sequence (see 22.4 SAM-BA Boot The SAM-BA boot principle is to: 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary ™ Boot is then executed. It waits for transactions either on the USB device the AutoBaudrate Sequence OR USB Enumeration ...
Page 134
... Figure 22-2. AutoBaudrate Flow Diagram Table 22-1. Command • Write commands: Write a byte (O), a halfword ( word (W) to the target. AT91SAM7X256/128 Preliminary 134 Device Setup No Character '0x80' received ? Yes No Character '0x80' received ? Yes No Character '#' received ? Yes Send Character '>' Run SAM-BA Boot – ...
Page 135
... Each block of the transfer looks like: <SOH><blk #><255-blk #><--128 data bytes--><checksum> in which: Figure 22-3 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary – Address: Address in hexadecimal – Output: The byte, halfword or word read in hexadecimal following by ‘>’ – Address: Address in hexadecimal – ...
Page 136
... The device handles standard requests as defined in the USB Specification. Table 22-2. Request GET_DESCRIPTOR SET_ADDRESS SET_CONFIGURATION GET_CONFIGURATION 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Host C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK ...
Page 137
... Hardware and Software Constraints • SAM-BA boot copies itself in the SRAM and uses a block of internal SRAM for variables and stacks. The remaining available size for the user code is 57344 bytes for AT91SAM7X256 and 24576 bytes for AT91SAM7X128. • USB requirements: Table 22-4. ...
Page 138
... AT91SAM7X256/128 Preliminary 138 6120A–ATARM–01-Sep-05 ...
Page 139
... The peripheral triggers PDC transfers using transmit and receive signals. When the pro- grammed data is transferred, an end of transfer interrupt is generated by the corresponding peripheral. 23.2 Block Diagram Figure 23-1. Block Diagram 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Peripheral DMA Controller Peripheral THR PDC Channel 0 PDC Channel 1 RHR Status & ...
Page 140
... When the counter reaches zero, the transfer is complete and the PDC stops transfer- ring data. If the Next Counter Register is equal to zero, the PDC disables the trigger while activating the related peripheral end flag. AT91SAM7X256/128 Preliminary 140 6120A–ATARM–01-Sep-05 ...
Page 141
... If simultaneous requests of the same type (receiver or transmitter) occur on identical peripher- als, the priority is determined by the numbering of the peripherals. If transfer requests are not simultaneous, they are treated in the order they occurred. Requests from the receivers are handled first and then followed by transmitter requests. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary 141 ...
Page 142
... PDC Transfer Status Register Note: 1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user according to the function and the peripheral desired (DBGU, USART, SSC, SPI, MCI etc). AT91SAM7X256/128 Preliminary 142 Register Name Read/Write ...
Page 143
... Address of the next receive transfer. 23.4.2 PDC Receive Counter Register Register Name: PERIPH_RCR Access Type: Read/Write • RXCTR: Receive Counter Value Number of receive transfers to be performed. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary RXPTR RXPTR RXPTR RXPTR 29 ...
Page 144
... PDC Transmit Counter Register Register Name: PERIPH_TCR Access Type: Read/Write • TXCTR: Transmit Counter Value TXCTR is the size of the transmit transfer to be performed. At zero, the peripheral DMA transfer is stopped. AT91SAM7X256/128 Preliminary 144 TXPTR TXPTR TXPTR 5 ...
Page 145
... PDC Receive Next Counter Register Register Name: PERIPH_RNCR Access Type: Read/Write • RXNCR: Receive Next Counter Value RXNCR is the size of the next buffer to receive. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary RXNPTR RXNPTR RXNPTR ...
Page 146
... TXNPTR is the address of the next buffer to transmit when the current buffer is empty. 23.4.8 PDC Transmit Next Counter Register Register Name: PERIPH_TNCR Access Type: Read/Write • TXNCR: Transmit Next Counter Value TXNCR is the size of the next buffer to transmit. AT91SAM7X256/128 Preliminary 146 TXNPTR TXNPTR TXNPTR ...
Page 147
... Disables the receiver PDC transfer requests. • TXTEN: Transmitter Transfer Enable effect Enables the transmitter PDC transfer requests. • TXTDIS: Transmitter Transfer Disable effect Disables the transmitter PDC transfer requests 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary – – – 21 ...
Page 148
... RXTEN: Receiver Transfer Enable 0 = Receiver PDC transfer requests are disabled Receiver PDC transfer requests are enabled. • TXTEN: Transmitter Transfer Enable 0 = Transmitter PDC transfer requests are disabled Transmitter PDC transfer requests are enabled. AT91SAM7X256/128 Preliminary 148 – – ...
Page 149
... The fast forcing feature redirects any internal or external interrupt source to provide a fast inter- rupt rather than a normal interrupt. 24.2 Block Diagram Figure 24-1. Block Diagram 24.3 Application Block Diagram Figure 24-2. Description of the Application Block 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary FIQ AIC IRQ0-IRQn Up to Thirty-two Sources Embedded PeripheralEE ...
Page 150
... Interrupt Sources The Interrupt Source 0 is always located at FIQ. If the product does not feature an FIQ pin, the Interrupt Source 0 cannot be used. AT91SAM7X256/128 Preliminary 150 Advanced Interrupt Controller FIQ PIO External ...
Page 151
... The peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peripheral). Consequently, to sim- plify the description of the functional operations and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary 151 ...
Page 152
... The AIC_ISR register reads the number of the current interrupt (see 155) and the register AIC_CISR gives an image of the signals nIRQ and nFIQ driven on the processor. Each status referred to above can be used to optimize the interrupt handling of the systems. AT91SAM7X256/128 Preliminary 152 (See “Priority Controller” on page (See “Fast Forcing” on page 155 ...
Page 153
... Internal Interrupt Source Input Stage Figure 24-4. 24.7.1.6 External Interrupt Source Input Stage Figure 24-5. External Interrupt Source Input Stage Source i 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Internal Interrupt Source Input Stage AIC_SMRI (SRCTYPE) Source i Edge Detector Set Clear AIC_ISCR AIC_ICCR AIC_SMRi SRCTYPE High/Low Pos ...
Page 154
... The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources. 24.7.2.1 External Interrupt Edge Triggered Source Figure 24-6. 24.7.2.2 External Interrupt Level Sensitive Source Figure 24-7. AT91SAM7X256/128 Preliminary 154 External Interrupt Edge Triggered Source MCK IRQ or FIQ (Positive Edge) IRQ or FIQ (Negative Edge) ...
Page 155
... The nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority interrupt condition happens (or is pending) during the interrupt treatment in 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Internal Interrupt Edge Triggered Source MCK nIRQ Maximum IRQ Latency = 4 ...
Page 156
... This section gives an overview of the fast interrupt handling sequence when using the AIC assumed that the programmer understands the architecture of the ARM processor, and espe- cially the processor interrupt modes and the associated status bits assumed that: AT91SAM7X256/128 Preliminary 156 PC,[PC,# -&F20] 6120A–ATARM–01-Sep-05 ...
Page 157
... SPSR_irq. Note: 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary priority. The current level is the priority level of the current interrupt. must be read in order to de-assert nIRQ. If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared dur- ing this phase. The “ ...
Page 158
... FIQ link register (R14_FIQ) and the program counter (R15) is loaded with 0x1C. In the following cycle, during fetch at address 0x20, the ARM core adjusts R14_fiq, decre- menting it by four. 2. The ARM core enters FIQ mode. AT91SAM7X256/128 Preliminary 158 PC,[PC,# -&F20] 6120A–ATARM–01-Sep-05 ...
Page 159
... The read of the FVR does not 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary The "F" bit in SPSR is significant set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ is masked) ...
Page 160
... Interrupt Status Register (AIC_ISR), is updated with the current interrupt only when AIC_IVR is written. An AIC_IVR read on its own (e.g debugger), modifies neither the AIC context nor the AIC_ISR. Extra AIC_IVR reads perform the same operations. However recommended to AT91SAM7X256/128 Preliminary 160 Input Stage Automatic Clear Read FVR if Fast Forcing is disabled on Sources ...
Page 161
... Control Register) is set. However, this mask does not prevent waking up the processor if it has entered Idle Mode. This function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt strongly recommended to use this mask with caution. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary 161 ...
Page 162
... Fast Forcing Disable Register 0x148 Fast Forcing Status Register Note: 1. The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset, thus not pending. AT91SAM7X256/128 Preliminary 162 Name Access AIC_SMR0 Read/Write AIC_SMR1 Read/Write ...
Page 163
... The priority level is not used for the FIQ in the related SMR register AIC_SMRx. • SRCTYPE: Interrupt Source Type The active level or edge is not programmable for the internal interrupt sources. SRCTYPE 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary – – – – – – ...
Page 164
... The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU. AT91SAM7X256/128 Preliminary 164 29 28 ...
Page 165
... IRQID: Current Interrupt Identifier The Interrupt Status Register returns the current interrupt source number. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary FIQV FIQV FIQV FIQV – ...
Page 166
... Reset Value PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Mask 0 = Corresponding interrupt is disabled Corresponding interrupt is enabled. AT91SAM7X256/128 Preliminary 166 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 5 ...
Page 167
... PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID3: Interrupt Enable effect Enables corresponding interrupt. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary – – – – – – – – ...
Page 168
... Access Type: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Clear effect Clears corresponding interrupt. AT91SAM7X256/128 Preliminary 168 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 5 ...
Page 169
... The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete. Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary PID29 ...
Page 170
... PROT: Protection Mode 0 = The Protection Mode is disabled The Protection Mode is enabled. • GMSK: General Mask 0 = The nIRQ and nFIQ lines are normally controlled by the AIC The nIRQ and nFIQ lines are tied to their inactive state. AT91SAM7X256/128 Preliminary 170 SIQV ...
Page 171
... PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • SYS, PID2-PID31: Fast Forcing Disable effect Disables the Fast Forcing feature on the corresponding interrupt. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary PID29 PID28 PID27 PID21 PID20 PID19 PID13 ...
Page 172
... PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • SYS, PID2-PID31: Fast Forcing Status 0 = The Fast Forcing feature is disabled on the corresponding interrupt The Fast Forcing feature is enabled on the corresponding interrupt. AT91SAM7X256/128 Preliminary 172 PID29 PID28 PID27 PID21 PID20 PID19 ...
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... MHz. The oscillator contains 25 pF capacitors on each XIN and XOUT pin. Consequently, CL1 and CL2 can be removed when a 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Section 26.9. However, the Clock Generator registers are named shows the Main Oscillator block diagram. ...
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... MOSCS bit is set. Then, at the 16th falling edge of Slow Clock, the MAINRDY bit in CKGR_MCFR (Main Clock Frequency Register) is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock AT91SAM7X256/128 Preliminary 174 XIN ...
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... Values and connected to the PLLRC pin must be calculated as a function of the PLL input frequency, the PLL output frequency and the phase margin. A trade-off has to be found between output signal overshoot and startup time. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary shows the block diagram of the divider and PLL block. DIV MUL ...
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... The user has to load the number of Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field. The transient time depends on the PLL filter. The initial state of the PLL and its target frequency can be calculated using a specific tool pro- vided by Atmel. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary 176 ...
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... This feature is useful when switching from a high- speed clock to a lower one to inform the software when the change is actually done. Figure 26-1. Master Clock Controller PMC_MCKR SLCK MAINCK PLLCK 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary PMC_MCKR CSS PRES Master Clock Prescaler MCK To the Processor ...
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... In order to stop a peripheral recommended that the system software wait until the periph- eral has executed its last programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the system. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary USBDIV Divider UDP Clock (UDPCK) ...
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... This measure can be accomplished via the CKGR_MCFR register. Once the MAINRDY field is set in CKGR_MCFR register, the user may read the MAINF field in CKGR_MCFR register. This provides the number of main clock cycles within six- teen slow clock cycles. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary write_register(CKGR_MOR,0x00000701) 179 ...
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... Once PMC_MCKR register has been written, the user must wait for the MCKRDY bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting for the interrupt line to be raised if the associated interrupt to MCKRDY has been enabled in the PMC_IER register. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary write_register(CKGR_PLLR,0x00040805) 180 ...
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... Code Example: 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary IF PLLx clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLR, the MCKRDY flag will go low while PLL is unlocked. Once PLL is locked again, LOCK goes high and MCKRDY is set. ...
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... Depending on the system used, 15 peripheral clocks can be enabled or disabled. The PMC_PCSR provides a clear view as to which peripheral clock is enabled. Note: Code Examples: Peripheral clocks 4 and 8 are enabled. Peripheral clock 4 is disabled. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary write_register(PMC_PCK0,0x00000015) Each enabled peripheral clock corresponds to Master Clock. write_register(PMC_PCER,0x00000110) write_register(PMC_PCDR,0x00000010) 182 ...
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... Slow Clock PLL Clock LOCK MCKRDY Master Clock Write PMC_MCKR 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary gives the worst case timings required for the Master Clock to switch from one Clock Switching Timings (Worst Case) From Main Clock – 0.5 x Main Clock + 4.5 x SLCK ...
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... Figure 26-4. Switch Master Clock from Main Clock to Slow Clock Slow Clock Main Clock MCKRDY Master Clock Write PMC_MCKR Figure 26-5. Change PLL Programming Main Clock PLL Clock LOCK MCKRDY Master Clock Write CKGR_PLLR 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Main Clock 184 ...
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... Figure 26-6. Programmable Clock Output Programming PLL Clock PCKRDY PCKx Output Write PMC_PCKx Write PMC_SCER Write PMC_SCDR 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary PLL Clock is selected PCKx is enabled PCKx is disabled 185 ...
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... Interrupt Enable Register 0x0064 Interrupt Disable Register 0x0068 Status Register 0x006C Interrupt Mask Register 0x0070 - 0x00FC Reserved 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary Name Access PMC_SCER Write-only PMC_SCDR Write-only PMC _SCSR Read-only – – PMC _PCER Write-only PMC_PCDR ...
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... UDP: USB Device Port Clock Enable effect Enables the 48 MHz clock of the USB Device Port. • PCKx: Programmable Clock x Output Enable effect Enables the corresponding Programmable Clock output. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary – – – ...
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... UDP: USB Device Port Clock Disable effect Disables the 48 MHz clock of the USB Device Port. • PCKx: Programmable Clock x Output Disable effect Disables the corresponding Programmable Clock output. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary – – – ...
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... The 48 MHz clock (UDPCK) of the USB Device Port is disabled The 48 MHz clock (UDPCK) of the USB Device Port is enabled. • PCKx: Programmable Clock x Output Status 0 = The corresponding Programmable Clock output is disabled The corresponding Programmable Clock output is enabled. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary – – ...
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... PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • PIDx: Peripheral Clock x Disable effect Disables the corresponding peripheral clock. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 ...
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... PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • PIDx: Peripheral Clock x Status 0 = The corresponding peripheral clock is disabled The corresponding peripheral clock is enabled. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary PID29 PID28 PID27 PID21 PID20 PID19 PID13 ...
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... When OSCBYPASS is set, the MOSCS flag in PMC_SR is automatically set. Clearing MOSCEN and OSCBYPASS bits allows resetting the MOSCS flag. • OSCOUNT: Main Oscillator Start-up Time Specifies the number of Slow Clock cycles multiplied by 8 for the Main Oscillator start-up time. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary – ...
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... Gives the number of Main Clock cycles within 16 Slow Clock periods. • MAINRDY: Main Clock Ready 0 = MAINF value is not valid or the Main Oscillator is disabled The Main Oscillator has been enabled previously and MAINF value is available. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary – ...
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... MUL: PLL Multiplier 0 = The PLL is deactivated 2047 = The PLL Clock frequency is the PLL input frequency multiplied by MUL+ 1. • USBDIV: Divider for USB Clock USBDIV 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary USBDIV – MUL ...
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... CSS: Master Clock Selection • PRES: Master Clock Prescaler 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary – – – – – – – – – – ...
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... CSS: Master Clock Selection CSS • PRES: Programmable Clock Prescaler 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary – – – – – – – – – – ...
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... MOSCS: Main Oscillator Status Interrupt Enable • LOCK: PLL Lock Interrupt Enable • MCKRDY: Master Clock Ready Interrupt Enable • PCKRDYx: Programmable Clock Ready x Interrupt Enable effect Enables the corresponding interrupt. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary – – – ...
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... MOSCS: Main Oscillator Status Interrupt Disable • LOCK: PLL Lock Interrupt Disable • MCKRDY: Master Clock Ready Interrupt Disable • PCKRDYx: Programmable Clock Ready x Interrupt Disable effect Disables the corresponding interrupt. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary – – – ...
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... PLL is not locked 1 = PLL is locked. • MCKRDY: Master Clock Status 0 = Master Clock is not ready Master Clock is ready. • PCKRDYx: Programmable Clock Ready Status 0 = Programmable Clock x is not ready Programmable Clock x is ready. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary – – – – ...
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... MOSCS: Main Oscillator Status Interrupt Mask • LOCK: PLL Lock Interrupt Mask • MCKRDY: Master Clock Ready Interrupt Mask • PCKRDYx: Programmable Clock Ready x Interrupt Mask 0 = The corresponding interrupt is enabled The corresponding interrupt is disabled. 6120A–ATARM–01-Sep-05 AT91SAM7X256/128 Preliminary – – – ...