AT91SAM9261 ATMEL Corporation, AT91SAM9261 Datasheet

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AT91SAM9261

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AT91SAM9261
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ATMEL Corporation
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ARM926EJ-S
(r0p4/r0p5)
Technical Reference Manual
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D

Related parts for AT91SAM9261

AT91SAM9261 Summary of contents

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Technical Reference Manual Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D ARM926EJ-S (r0p4/r0p5) ...

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ARM926EJ-S Technical Reference Manual Copyright © 2001-2003 ARM Limited. All rights reserved. Release Information Date 26 September 2001 29 January 2002 5 December 2003 26 January 2004 Proprietary Notice Words and logos marked with as otherwise stated below in this ...

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Contents ARM926EJ-S Technical Reference Manual Preface Chapter 1 Introduction 1.1 Chapter 2 Programmer’s Model 2.1 2.2 2.3 Chapter 3 Memory Management Unit 3.1 3.2 3.3 3.4 3.5 3.6 3.7 ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. About ...

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Contents Chapter 4 Caches and Write Buffer 4.1 4.2 4.3 4.4 4.5 Chapter 5 Tightly-Coupled Memory Interface 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Chapter 6 Bus Interface Unit 6.1 6.2 Chapter 7 Noncachable Instruction Fetches 7.1 Chapter ...

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Chapter 11 Debug Support 11.1 Chapter 12 Power Management 12.1 Appendix A Signal Descriptions A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 Appendix B CP15 Test and Debug Registers B.1 Glossary ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights ...

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Contents vi Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D ...

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List of Tables ARM926EJ-S Technical Reference Manual Change history .............................................................................................................. ii Table 2-1 CP15 register summary ............................................................................................ 2-3 Table 2-2 Address types in ARM926EJ-S ................................................................................. 2-4 Table 2-3 CP15 abbreviations ................................................................................................... 2-5 Table 2-4 Reading from register c0 ........................................................................................... 2-7 ...

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List of Tables Table 2-23 TCM Region Register c9 ........................................................................................ 2-30 Table 2-24 TCM Size field encoding ......................................................................................... 2-30 Table 2-25 Programming the TLB Lockdown Register ............................................................. 2-32 Table 2-26 FCSE PID Register operations ............................................................................... 2-34 Table 2-27 Context ID ...

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Table B-10 MMU Debug Control Register bit assignments ....................................................... B-14 Table B-11 Memory Region Remap Register instructions ......................................................... B-15 Table B-12 Encoding of the Memory Region Remap Register .................................................. B-16 Table B-13 Encoding of the remap fields ................................................................................... B-16 ARM ...

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List of Tables x Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D ...

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List of Figures ARM926EJ-S Technical Reference Manual Key to timing diagram conventions ............................................................................ xix Figure 1-1 ARM926EJ-S block diagram ..................................................................................... 1-3 Figure 1-2 ARM926EJ-S interface diagram (part one) ............................................................... 1-4 Figure 1-3 ARM926EJ-S interface diagram (part two) ............................................................... 1-5 Figure ...

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List of Figures Figure 3-4 First-level descriptor ................................................................................................. 3-9 Figure 3-5 Section descriptor ................................................................................................... 3-10 Figure 3-6 Coarse page table descriptor .................................................................................. 3-11 Figure 3-7 Fine page table descriptor ...................................................................................... 3-12 Figure 3-8 Section translation .................................................................................................. 3-14 Figure 3-9 Second-level ...

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Figure 12-2 Logic for stopping ARM926EJ-S clock during wait for interrupt .............................. 12-3 Figure B-1 CP15 MRC and MCR bit pattern ............................................................................... B-2 Figure B-2 Rd format for selecting main TLB entry ..................................................................... B-6 Figure B-3 Rd format for accessing ...

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List of Figures xiv Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D ...

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Preface This preface introduces the ARM926EJ-S Revision r0p4/r0p5 Technical Reference Manual (TRM). It contains the following sections: • About this manual on page xvi • Feedback on page xxi. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. xv ...

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Preface About this manual This is the Technical Reference Manual for the ARM926EJ-S processor. Product revision status The rnpn identifier indicates the revision status of the product described in this manual, where Intended audience This document has been ...

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Chapter 6 Bus Interface Unit Chapter 7 Noncachable Instruction Fetches Chapter 8 Coprocessor Interface Chapter 9 Instruction Memory Barrier Chapter 10 Embedded Trace Macrocell Support Chapter 11 Debug Support Chapter 12 Power Management Appendix A Signal Descriptions Appendix B CP15 ...

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Preface Conventions This section describes the conventions that this manual uses: • Typographical • Timing diagrams • Signal naming on page xix • Numbering on page xx. Typographical This manual uses the following typographical conventions: italic bold monospace italic monospace ...

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Signal naming The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means HIGH for active-HIGH signals and LOW for active-LOW signals: Prefix H Prefix n Prefix DH Prefix IH Prefix DR Prefix IR ...

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Preface Numbering <size in bits>’<base><number> Further reading This section lists publications by ARM Limited, and by third parties. ARM Limited periodically provides updates and corrections to its documentation. See Frequently Asked Questions list. ARM publications This manual contains information that ...

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Feedback ARM Limited welcomes feedback on the ARM926EJ-S processor and its documentation. Feedback on the product If you have any comments or suggestions about this product, contact your supplier giving: • the product name • a concise explanation of your ...

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Preface xxii Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D ...

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Chapter 1 Introduction This chapter introduces the ARM926EJ-S processor and its features. It contains the following section: • About the ARM926EJ-S processor on page 1-2. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 1-1 ...

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Introduction 1.1 About the ARM926EJ-S processor The ARM926EJ-S processor is a member of the ARM9 family of general-purpose microprocessors. The ARM926EJ-S processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are ...

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External coprocessor interface CPDOUT CPDIN Coprocessor ETM interface interface WDATA RDATA DA ARM9EJ-S IA INSTR Figure 1-2 on page 1-4 and Figure 1-3 on page 1-5 show the ARM926EJ-S interfaces. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. ...

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Introduction Clock nFIQ Interrupts nIRQ STANDBYWFI BIGENDINIT Miscellaneous VINITHI configuration CFGBIGEND TAPID[31:0] COMMRX COMMTX DBGACK DBGEN DBGRQI JTAG debug EDBGRQ DBGEXT[1:0] DBGINSTREXEC DBGRNG[1:0] DBGIEBRKPT DBGDEWPT DBGnTRST DBGTCKEN DBGTDI DBGTMS DBGTDO Debug DBGIR[3:0] DBGSCREG[4:0] DBGTAPSM[3:0] DBGnTDOEN DBGSDIN DBGSDOUT 1-4 Copyright © ...

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ETMDMAS[1:0] ETMRDATA[31:0] ETM interface ETMWDATA[31:0] ETMINSTREXEC ETMID31TO25[6:0] ETMID15TO11[4:0] ETMCHSD[1:0] ETMCHSE[1:0] ETMLATECANCEL ETMPROCID[31:0] ETMPROCIDWR ETMINSTRVALID ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. ETMEN FIFOFULL ETMBIGEND ETMHIVECS ETMIA[31:0] ETMInNREQ ETMISEQ ETMITBIT ETMIABORT ETMDA[31:0] ETMDMORE ETMDnMREQ ETMDnRW ETMDSEQ ARM926EJ-S ETMDABORT ...

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Introduction 1-6 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D ...

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Chapter 2 Programmer’s Model This chapter describes the ARM926EJ-S registers in CP15, the system control coprocessor, and provides information for programming the microprocessor. It contains the following sections: • About the programmer’s model on page 2-2 • Summary of ARM926EJ-S ...

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Programmer’s Model 2.1 About the programmer’s model The system control coprocessor (CP15) is used to configure and control the ARM926EJ-S processor. The caches, Tightly-Coupled Memories (TCMs), Memory Management Unit (MMU), and most other system options are controlled using CP15 registers. ...

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Summary of ARM926EJ-S system control coprocessor (CP15) registers CP15 defines 16 registers. Table 2-1 shows the read and write functions of the registers. Register ...

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Programmer’s Model All CP15 register bits that are defined and contain state are set Reset except: • The V bit is set reset if the VINITHI signal is LOW the VINITHI ...

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Cond The mnemonics for these instructions are: Attempting to read from a write-only register, or writing to a read-only register causes Unpredictable results. In all instructions that access CP15: ...

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Programmer’s Model Term Should Be One Should Be Zero or Preserved In all cases, reading from, or writing any data values to any CP15 registers, including those fields specified as Unpredictable, Should Be One, or Should Be Zero does not ...

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Register descriptions The following registers are described in this section: • ID Code, Cache Type, and TCM Status Registers, c0 • Control Register c1 on page 2-12 • Translation Table Base Register c2 on page 2-17 • Domain Access ...

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Programmer’s Model ID Code Register c0 This is a read-only register that returns the 32-bit device ID code. You can access the ID Code Register by reading CP15 register c0 with the Opcode_2 field set to any value other than ...

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Ctype Ctype S bit Dsize Isize The Ctype field specifies if the cache supports lockdown or not, and how it is cleaned. The encoding is shown in Table 2-6. All unused values are ...

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Programmer’s Model Assoc M bit Len The size of the cache is determined by the Size field and the M bit. The M bit is 0 for the DCache and ICache. The Size field is bits [21:18] for the DCache ...

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The line length of the cache is determined by the Len field. The Len field is bits [13:12] for the DCache and bits [1:0] for the ICache. Table 2-9 shows the line length encoding. The cache type register values for ...

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Programmer’s Model Function Isize TCM Status Register c0 This is a read-only register that enables operating systems to establish if TCM memories are present. See also TCM Region Register c9 on page 2-29. You can access the TCM Status Register ...

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All defined control bits are set to zero on reset except the V bit and the B bit. The V bit is set to zero at reset if the VINITHI signal is LOW, or one if the VINITHI signal is ...

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Programmer’s Model Bit [13] [12] [11:10] [9] [8] [7] [6:3] [2] [1] [0] Effects of Control Register on caches The bits of the Control Register that directly affect the ICache and DCache behavior are: • the M bit • the ...

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RR bit. Assuming that TCM regions are disabled, the caches behave as shown in Table 2-12. Cache MMU ICache disabled Enabled or disabled ICache enabled Disabled ICache enabled Enabled DCache disabled Enabled or disabled DCache enabled Disabled DCache ...

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Programmer’s Model Effects of the Control Register on TCM interface The M bit of the Control Register, when combined with the En bit in the respective TCM region register c9, directly affects the TCM interface behavior, as shown in Table ...

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Read accesses on the TCM interface are not prevented when an ARM9EJ-S core memory access is aborted. All reads on the TCM interface must be treated as speculative. ARM92EJ-S processor write accesses that are aborted do not take place on ...

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Programmer’s Model D15 D14 D13 D12 D11 D10 ...

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The FSR accessed is determined by the value of the Opcode_2 field: Opcode_2 = 0 Opcode_2 = 1 The fault type encoding is listed in Table 3-9 on page 3-22. You can access the FSRs using the following instructions: The ...

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Programmer’s Model Table 2-16 shows the encodings used for the status field in the FSR, and if the Domain field contains valid information. See Fault address and fault status registers on page 3-21 for details of MMU aborts. 2.3.7 Fault ...

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Reading from CP15 c7 is Unpredictable, with the exception of the two test and clean operations (see Table 2-18 on page 2-22 and Test and clean operations on page 2-24). You can use the following instruction to write to c7: ...

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Programmer’s Model Function Prefetch ICache line Drain write buffer Wait for interrupt Table 2-18 lists the cache operation functions and the associated data and instruction formats for c7. Function/operation Invalidate ICache and DCache Invalidate ICache Invalidate ICache single entry (MVA) ...

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Function/operation Invalidate DCache single entry (Set/Way) Clean DCache single entry (MVA) Clean DCache single entry (Set/Way) Test and clean DCache Clean and invalidate DCache entry (MVA) Clean and invalidate DCache entry (Set/Way) Test, clean, and invalidate DCache Drain write buffer ...

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Programmer’s Model 31 32-A 31-A Way Test and clean operations The test and clean DCache instruction provides an efficient way to clean the entire DCache using a simple loop. The test and clean DCache instruction tests a number of lines ...

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The fully-associative part (also referred to as the lockdown part of the TLB) is used to store entries to be locked down. Entries held in the lockdown part of the TLB are preserved during an invalidate TLB operation. Entries can ...

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Programmer’s Model 31 If either small or large pages are used, and these pages contain subpage access permissions that are different, then you must use four invalidate TLB single entry operations, with the MVA set to each subpage, to invalidate ...

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The first four bits of this register determine the L bit for the associated cache way. The Opcode_2 field of the MRC or MCR instruction determines whether the instruction or data lockdown register is accessed: Opcode_2 = 0 Opcode_2 = ...

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Programmer’s Model The format of the Cache Lockdown Register L bits is shown in Table 2-21. All cache ways are available for allocation from reset. Bits [31:16] [15: You can use the cache lockdown and cache ...

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For each of the cache lines to be locked down in cache way i: • • 8. Write to register c9, CRm == 0 setting for bit i and restoring all the other bits to the ...

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Programmer’s Model The TCM Region Register format is shown in Figure 2-13. 31 Base address (physical address) Table 2-23 shows the bit assignments for the TCM Region Register. 2-30 Copyright © 2001-2003 ARM Limited. All rights reserved ...

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If either the data or instruction TCM is disabled, then the contents of the respective TCM are not accessed. If the TCM is subsequently re-enabled, the contents will not have been changed by the ARM926EJ-S processor. For a Harvard arrangement, ...

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Programmer’s Model 2.3.11 TLB Lockdown Register c10 The TLB Lockdown Register controls where hardware page table walks place the TLB entry, in the set associative region or the lockdown region of the TLB, and if in the lockdown region, which ...

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It is not possible for a lockdown entry to entirely map either small or large pages, unless all the subpage access permissions are identical. Entries can still be written into the lockdown region, but the address range that is mapped ...

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Programmer’s Model FCSE PID Register Addresses issued by the ARM9EJ-S core in the range 0 to 32MB are translated in accordance with the value contained in this register. Address A becomes A + (FCSE PID x 32MB this ...

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Where A1, A2, and A3 are the three instructions following the fast context switch. Context ID Register The Context ID Register provides a mechanism to allow real-time trace tools to identify the currently executing process in multi-tasking environments. The contents ...

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Programmer’s Model 2.3.15 Test and Debug Register c15 You can use register c15 to provide device-specific test and debug operations in ARM926EJ-S processors. Appendix B CP15 Test and Debug Registers describes the registers and functions available using CP15 c15.This register ...

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Chapter 3 Memory Management Unit This chapter describes the Memory Management Unit (MMU). It contains the following sections: • About the MMU on page 3-2 • Address translation on page 3-5 • MMU faults and CPU aborts on page 3-21 ...

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Memory Management Unit 3.1 About the MMU The ARM926EJ-S MMU is an ARM architecture v5 MMU. It provides virtual memory features required by systems operating on platforms such as Symbian OS, WindowsCE, and Linux. A single set of two-level page ...

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Access permissions and domains For large and small pages, access permissions are defined for each subpage (1KB for small pages, 16KB for large pages). Sections and tiny pages have a single set of access permissions. All regions of memory ...

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Memory Management Unit 3.1.3 MMU program accessible registers Table 3-1 shows the CP15 registers that are used in conjunction with page table descriptors stored in memory to determine the operation of the MMU. Register Bits Control register ...

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Address translation The VA generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE using the value held in CP15 c13. The MMU translates MVAs into physical addresses to access external memory, and ...

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Memory Management Unit 3.2.1 Translation table base The hardware translation process is initiated when the TLB does not contain a translation for the requested MVA. The Translation Table Base Register (TTBR), CP15 register c2, points to the base address of ...

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Translation table TTB base Indexed by modified virtual address bits [31:20] 4096 entries ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. Section Section base Indexed by modified virtual address bits [19:0] 1MB Coarse page Coarse page table table ...

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Memory Management Unit 3.2.2 First-level fetch Bits [31:14] of the TTBR are concatenated with bits [31:20] of the MVA to produce a 30-bit address as shown in Figure 3-3. Translation table base 31 Translation base 31 Translation base 31 First-level ...

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Coarse page table base address Section base address Fine page table base address A section descriptor provides the base address of a 1MB block of memory. The page table descriptors provide the base address of a page table that ...

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Memory Management Unit Bits Section [3:2] - [1:0] The two least significant bits of the first-level descriptor indicate the descriptor type as shown in Table 3-3. Value 3.2.4 Section descriptor A section ...

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Section descriptor bit assignments are described in Table 3-4. Bits [31:20] [19:12] [11:10] [9] [8:5] [4] [3:2] [1:0] 3.2.5 Coarse page table descriptor A coarse page table descriptor provides the base address of a page table that contains second-level descriptors ...

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Memory Management Unit Coarse page table descriptor bit assignments are described in Table 3-5. Bits [31:10] [9] [8:5] [4] [3:2] [1:0] 3.2.6 Fine page table descriptor A fine page table descriptor provides the base address of a page table that ...

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Table 3-6 shows the fine page table descriptor bit assignments. Bits [31:12] [11:9] [8:5] [4] [3:2] [1:0] 3.2.7 Translating section references Figure 3-8 on page 3-14 shows the complete section translation sequence. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All ...

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Memory Management Unit Translation table base 31 Translation base 31 Translation base Section first-level descriptor Section base address Physical address Section base address 3.2.8 Second-level descriptor If the first-level fetch returns either a coarse ...

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Large page base address Small page base address Tiny page base address A second-level descriptor defines a tiny, a small large page descriptor invalid: • a large page descriptor provides the base address of a ...

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Memory Management Unit Bits Large [11:4] [3:2] [1:0] The two least significant bits of the second-level descriptor indicate the descriptor type as shown in Table 3-8. Value Tiny pages do not support ...

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Translation table base 31 Translation base 31 Translation base First-level descriptor 31 Coarse page table base address 31 Coarse page table base address Second-level descriptor 31 Page base address Physical address 31 Page base address Because the upper four bits ...

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Memory Management Unit 3.2.10 Translating small page references Figure 3-11 shows the complete translation sequence for a 4KB small page. Translation table base 31 Translation base 31 Translation base First-level descriptor 31 Coarse page table base address 31 Coarse page ...

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Translating tiny page references Figure 3-12 shows the complete translation sequence for a 1KB tiny page. Translation table base 31 Translation base 31 Translation base First-level descriptor 31 Fine page table base address 31 Fine page table base address ...

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Memory Management Unit The domain specified in the first-level description and access permissions specified in the first-level description together determine whether the access has permissions to proceed. See section Domain access control on page 3-24 for details. Subpages You can ...

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MMU faults and CPU aborts The MMU generates an abort on the following types of faults: • alignment faults (data accesses only) • translation faults • domain faults • permission faults. In addition, an external abort can be raised ...

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Memory Management Unit Fault status register (FSR) Table 3-9 shows the various access permissions and controls supported by the data MMU, and how these are interpreted to generate faults. Alignment faults can write either b0001 or b0011 into FSR[3:0]. Invalid ...

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Fault address register (FAR) For load and store instructions that can involve the transfer of more than one word (LDM/STM, LDRD, STRD, and STC/LDC), the value written into the FAR register depends on the type of access, and for external ...

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Memory Management Unit 3.4 Domain access control MMU accesses are primarily controlled through the use of domains. There are 16 domains and each has a two-bit field to define access to it. Two types of user are supported: • clients ...

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ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. Table 3-12 Interpreting access permission (AP) bits (continued Privileged permissions Read/write Read/write Read/write Memory Management ...

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Memory Management Unit 3.5 Fault checking sequence The sequence the MMU uses to check for access faults is different for sections and pages. The sequence for both types of access is shown in Figure 3-13. Section translation Invalid fault Section ...

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Translation faults • Domain faults • Permission faults on page 3-28. 3.5.1 Alignment faults If alignment fault checking is enabled (the A bit in CP15 c1 is set), the MMU generates an alignment fault on any data word access ...

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Memory Management Unit 3.5.4 Permission faults If the two-bit domain field returns 01 (client), then access permissions are checked as follows: Section Large page or small page Tiny page 3-28 Copyright © 2001-2003 ARM Limited. All rights reserved. If the ...

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External aborts In addition to the MMU generated aborts, external aborts can be generated for certain types of access that involve transfers over the AHB bus. These can be used to flag errors on external memory accesses. However, not ...

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Memory Management Unit Because the same register, CP15 c1, controls the enabling of the ICache, DCache, and the MMU, all three can be enabled using a single MCR instruction. 3.6.2 Disabling the MMU To disable the MMU, clear bit 0 ...

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TLB structure The MMU contains a single unified TLB used for both data accesses and instruction fetches. The TLB is divided into two parts: • an eight-entry fully-associative part used exclusively for holding locked down TLB entries • a ...

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Memory Management Unit 3-32 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D ...

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Chapter 4 Caches and Write Buffer This chapter describes the Instruction Cache (ICache), the Data Cache (DCache), and the write buffer. It contains the following sections: • About the caches and write buffer on page 4-2 • Write buffer on ...

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Caches and Write Buffer 4.1 About the caches and write buffer The ARM926EJ-S processor includes: • an Instruction Cache (ICache) • a Data Cache (DCache) • a write buffer. The size of the caches can be from 4KB to 128KB, ...

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The latter allows DCache coherency to be efficiently maintained when small code changes occur, for example for self-modifying code and changes to exception vectors. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. Caches and Write Buffer 4-3 ...

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Caches and Write Buffer 4.2 Write buffer The write buffer is used for all writes to a noncachable, bufferable region, write-through region, and write misses to a write-back region. A separate buffer is incorporated in the DCache for holding write-back ...

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Enabling the caches On reset, the ICache and DCache entries are all invalidated and the caches are disabled. The caches are not accessed for reads or writes. The caches are enabled using the I, C, and M bits from ...

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Caches and Write Buffer Table 4-3 gives the CP15 c1 C and M bit settings for DCache, and the associated behavior. CP15 c1 C bit Table 4-4 gives the page table C and B bit settings for ...

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Page table C bit 1 ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. Table 4-4 Page table C and B bit settings for the DCache (continued) Page table Description ARM926EJ-S behavior B bit 1 Write-back DCache enabled: Read ...

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Caches and Write Buffer 4.4 TCM and cache access priorities The priorities that apply to the ARM926EJ-S processor for instruction accesses are shown in Table 4-5. The ARM926EJ-S processor gives highest priority to an address that is in the instruction ...

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Cache MVA and Set/Way formats This section shows how the MVA and Set/Way formats of ARM926EJ-S caches map to a generic virtually indexed, virtually addressed cache. Figure 4-1 shows a generic, virtually indexed, virtually addressed cache. Vitual index, virtual ...

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Caches and Write Buffer 31 Table 4-7 shows values of S and NSETS for an ARM926EJ-S cache. Figure 4-2 shows the ARM926EJ-S cache associativity. In Figure 4-2, the following points apply: • the group of tags of the same Index ...

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ARM926EJ-S caches are four-way Associative • the range of tags addressed by the Index define a Way • the number of tags in a Way is the number of Sets, NSETS. The Set/Way/Word format for ARM926EJ-S caches is ...

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Caches and Write Buffer 4-12 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D ...

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Chapter 5 Tightly-Coupled Memory Interface This chapter describes the ARM926EJ-S Tightly-Coupled Memory (TCM) interface. It contains the following sections: • About the tightly-coupled memory interface on page 5-2 • TCM interface signals on page 5-4 • TCM interface bus cycle ...

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Tightly-Coupled Memory Interface 5.1 About the tightly-coupled memory interface The ARM926EJ-S processor enables low latency access to external memories using the Tightly Coupled Memory (TCM) interface. The term tightly coupled memory refers to the relationship between the ARM9EJ-S CPU core, ...

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The TCM interface contains a two entry write buffer, which avoids the need for stall cycles because of the mismatch between the ARM9EJ-S native memory interface, and the requirements for standard SRAM. TCM accesses can be extended by using ...

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Tightly-Coupled Memory Interface 5.2 TCM interface signals The TCM interface is designed to be compatible the timings of standard ASIC SRAM components, allowing connection to single cycle SRAM with minimal interfacing logic required. For standard SRAM the chip-select, address, and ...

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DRWAIT DRWAIT is used to extend a TCM transfer by inserting wait states. The timing of the DRWAIT signal is a cycle ahead of the cycle in which the data transfer takes place, which means that if an access is ...

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Tightly-Coupled Memory Interface DRWD[31:0] DRWD is the write data written into the TCM valid in the same cycle as DRCS and held stable until the penultimate cycle of the access. DMA signals The DMA interface allows the values ...

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Instruction TCM signals The instruction side TCM signals are almost identical to the DTCM signals. All the signals on the DTCM have an equivalent on the instruction side. • Control signals — — — • Address and attribute signals ...

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Tightly-Coupled Memory Interface 5.3 TCM interface bus cycle types and timing The TCM bus interface is pipelined to enable back-to-back accesses to TCM memory with zero wait states. For each TCM access there is one request cycle and one or ...

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Zero wait state timing For zero wait state accesses the timing of the TCM interface corresponds to the timing of a standard SRAM component, with minimal interfacing logic required. Figure 5-2 shows examples of zero wait state accesses on ...

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Tightly-Coupled Memory Interface CLK DRCS DRSEQ DnRW DRADDR DRRD DRWD DRWBL In cycle T1, a nonsequential read request is made to address A. In cycle T2, a nonsequential word write request is made to address B and data is returned ...

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Figure 5-4 Relationship between DRDMAEN, DRDMACS, DRDMAADDR, DRADDR and DRCS Internal to the ARM926EJ-S processor there are multiple sources for both the address and chip-select outputs. The address and chip-select outputs of the TCM interface are timing critical, however not ...

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Tightly-Coupled Memory Interface DRDMAEN DRDMACS DRADDR DRDMAADDR In cycle T1, the ARM926EJ-S internal TCM controller is idle and DRIDLE is asserted. DRDMAEN is asserted, and consequently the value of DRDMAADDR is propagated onto DRADDR, and DRCS is asserted (DRDMACS = ...

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Multi-cycle access timing If non zero wait state memory is used for TCM, then the DRWAIT/IRWAIT signals are used to wait the ARM926EJ-S. The wait information for a data cycle is pipelined so that the value of DRWAIT/IRWAIT pertains ...

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Tightly-Coupled Memory Interface In the WAIT state IRWAIT is asserted. In the COMPLETE state IRWAIT is deasserted. Certain types of memories can have different access penalties depending on whether an access is sequential or nonsequential. The IRSEQ/DRSEQ signals indicate if ...

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CLK IRCS IRSEQ IRWAIT IRADDR IRRD In cycle T1, a nonsequential request is made to address A and IRWAIT is asserted. In cycle T2, IRSEQ is asserted because of the wait-state. IRWAIT is deasserted. IRCS is unknown. In cycle T3, ...

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Tightly-Coupled Memory Interface The logic used to generate DRWAIT uses both the loopback scheme using DRSEQ for inserting a wait state for a nonsequential request, and an additional signal DMAWAIT, for stalling during DMA accesses. The FORCE_NSEQ signal is an ...

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T1 T2 CLK DRCS DRSEQ DRADDR A DRWAIT DMAWAIT FORCE_NSEQ REQCLK SEQ RD DRRD Figure 5-11 Cycle timing of circuit with DMA and single wait state for nonsequential accesses In cycle T1, the ARM926EJ-S initiates a sequential ...

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Tightly-Coupled Memory Interface In cycle T5, the access to A completes. A sequential request is made to A+1. There is no DMA activity. In cycle T6, the access to A+1 completes. A sequential request is made to A+2. There is ...

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TCM programmer’s model After reset, the behavior of the TCMs is controlled by the state of the TCM Region Register, CP15 c9. 5.4.1 Enabling the ITCM The ITCM can automatically be enabled at reset using the INITRAM pin. If ...

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Tightly-Coupled Memory Interface 5.5 TCM interface examples This section contains the following examples: • Zero-wait-state RAM example • Producing byte writable memory using word writable RAM • Multiple banks of RAM example on page 5-21. Most of the examples in ...

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The rules for connecting four RAM blocks are: • • ARM926EJ-S DRWD[31:0] DRWR[7:0] DRADDR[17:0] DRWBL[3:0] b0110 DIN[7:0] A[14:0] DRSIZE[3:0] CLK CLK 32K RAM DRWAIT Byte 0 CS DRnRW DRCS DRRD[31:0] In little-endian mode, DRWBL[0] indicates the LSB of the word ...

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Tightly-Coupled Memory Interface • fast design is more important than minimizing power consumption, you must follow the example in Optimizing for speed on page 5-23. The rules for producing memory out of smaller RAM blocks are: • There ...

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ARM926EJ-S DRWD[31:0] DRADDR[17:0] DRWBL[3:0] DRSIZE[3:0] DRWAIT DRRD[31:0] Optimizing for speed Figure 5-15 on page 5-24 shows how to produce a large memory from two smaller RAM blocks if you are optimizing for speed. Separate write enable control is required for ...

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Tightly-Coupled Memory Interface ARM926EJ-S DRWD[31:0] DRADDR[17:0] DRWBL[3:0] DRSIZE[3:0] DRRD[31:0] 5.5.4 Sequential ROM example The diagram in Figure 5-16 on page 5-25 shows an example of a TCM sub-system that uses wait states for nonsequential accesses. The ROM used to hold ...

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Figure 5-16 TCM subsystem that uses wait states for nonsequential accesses The address and chip-select inputs to the ROM are pipelined with respect to the ARM926EJ-S TCM interface outputs. An address incrementer is used to generate sequential addresses. The output ...

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Tightly-Coupled Memory Interface CLK IRCS IRSEQ IRWAIT IRADDR IRRD Figure 5-17 Cycle timing of circuit that uses wait states for non sequential accesses 5.5.5 DMA interface example Figure 5-18 on page 5-27 shows an example TCM subsystem ...

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Integrating RAM test logic The memory used to implement TCM might require some form of test access, typically by a BIST controller. Generally this is done by adding a collar of multiplexors around the memory inputs. However, this method ...

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Tightly-Coupled Memory Interface This is similar to the previous DMA example. However, for BIST testing it is necessary for the BIST controller to be able to force the memory chip select to both HIGH and LOW values. This requirement means ...

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TCM access penalties The data side of the ARM926EJ-S core can access the ITCM. To maximize the performance of the ITCM, data read accesses to the ITCM are pipelined. The ARM926EJ-S core is stalled for two cycles to enable ...

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Tightly-Coupled Memory Interface 5.7 TCM write buffer Each TCM interface has a two word entry write buffer. This is required to de-pipeline the address and data values produced by the ARM9EJ-S core so that non-speculative writes can be made to ...

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Using synchronous SRAM as TCM memory If you use SRAM to implement TCM memory, then your library RAM must meet the following requirements: • It must be synchronous. All timings must be relative to the rising clock edge. • ...

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Tightly-Coupled Memory Interface 5.9 TCM clock gating If the ARM926EJ-S processor is not currently running code from a TCM region, the idle signal for that TCM (DRIDLE for DTCM, IRIDLE for ITCM) is asserted. This indicates that a TCM access ...

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Chapter 6 Bus Interface Unit This chapter describes the ARM926EJ-S Bus Interface Unit (BIU). It contains the following sections: • About the bus interface unit on page 6-2 • Supported AHB transfers on page 6-3. ARM DDI0198D Copyright © 2001-2003 ...

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Bus Interface Unit 6.1 About the bus interface unit The ARM926EJ-S Bus Interface Unit (BIU) arbitrates and schedules AHB requests. The BIU contains separate masters for both instruction and data access enabling complete AHB system flexibility. Separate masters enable multi-layer ...

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Supported AHB transfers The ARM926EJ-S processor supports a subset of AHB transfers. The permitted AHB transfers are described in: • Memory map • Transfer size • Mapping of level one and level two (AHB) attributes on page 6-5 • ...

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Bus Interface Unit Table 6-1 shows the HBURST encodings that the ARM926EJ-S processor uses, and the operations that perform each burst size. HBURST[2:0] Description Single Single transfer Incr4 Four-word incrementing burst Incr8 Eight-word incrementing burst Wrap8 Eight-word wrapping burst Incr4 ...

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Mapping of level one and level two (AHB) attributes Table 6-2 shows the IHPROT[3:0] and DHPROT[3:0] mappings for memory operations. Operation DCache linefill ICache linefill Page table walk (data) Page table walk (instruction) Instruction fetch Data access DCache write-back ...

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Bus Interface Unit 6.2.4 Byte and halfword accesses This section describes byte and halfword accesses for: • Address alignment • Thumb instruction fetches • Endianness and byte lane indication. Address alignment The ARM926EJ-S BIU performs address alignment checking and aligns ...

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Memory coherency on page 6-9. Single-layer AHB systems If the ARM926EJ-S processor used in a single-layer AHB system, each of the two BIU masters must be treated as being unique. The simplest way of integrating the ...

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Bus Interface Unit ARM926EJ-S processor Multi-layer AHB is described in more detail in the Multi-layer AHB Overview. Multi-AHB systems It is possible that the ARM926EJ-S instruction and data AHB interfaces can be connected to separate AHB systems, although there must ...

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If both AHB systems operate at the same frequency, DHCLKEN and IHCLKEN must be tied together. See AHB clocking on page 6-10 for more details. The AHB clock for each system, HCLK1 and HCLK2, must be synchronized to the ARM926EJ-S ...

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Bus Interface Unit 6.2.6 AHB clocking The ARM926EJ-S design uses a single clock, CLK. To run the ARM926EJ-S processor at a higher frequency than the AHB system bus, a separate AHB clock enable for each of the two bus masters ...

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For all other types of access (cache linefills, writeback evictions, buffered writes), an Error response is ignored. If the ARM926EJ-S processor used in a system which has to be tolerant to soft errors in external memory, then ...

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Bus Interface Unit 6-12 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D ...

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Chapter 7 Noncachable Instruction Fetches This chapter describes noncachable instruction fetches in the ARM926EJ-S processor. It contains the following section: • About noncachable instruction fetches on page 7-2. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 7-1 ...

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Noncachable Instruction Fetches 7.1 About noncachable instruction fetches The ARM926EJ-S processor performs speculative noncachable instruction fetches to increase performance. Speculative instruction fetching is enabled at reset. This can be disabled using bit 16 in the debug state register CP15 c15 ...

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This IMB implementation only applies to the ARM926EJ-S processor running code from a noncachable region of memory. If code is run from a cachable region of memory different device is used then a different IMB implementation is required. ...

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Noncachable Instruction Fetches 7-4 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D ...

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Chapter 8 Coprocessor Interface This chapter describes the ARM926EJ-S coprocessor interface. It contains the following sections: • About the ARM926EJ-S external coprocessor interface on page 8-2 • LDC/STC on page 8-4 • MCR/MRC on page 8-6 • CDP on page ...

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Coprocessor Interface 8.1 About the ARM926EJ-S external coprocessor interface The ARM926EJ-S supports the connection of on-chip coprocessors to the ARM9EJ-S core through an external coprocessor interface. All types of coprocessor instructions are supported. 8.1.1 Overview Coprocessors determine the instructions that ...

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This is one technique for generating a clock that reflects the ARM9EJ-S core pipeline advancing. If CPCLKEN is LOW on the rising edge of CPCLK then the ARM9EJ-S core pipeline is stalled and the coprocessor pipeline should not advance. Coprocessor ...

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Coprocessor Interface 8.2 LDC/STC The cycle timing for this operation is shown in Figure 8-3. Fetch Decode Coprocessor pipeline CLK CPINSTR[31:0] LDC nCPMREQ CPPASS CPLATECANCEL CHSDE[1:0] CHSEX[1:0] CPDOUT[31:0] LDC CPDIN[31:0] STC In Figure 8-3 four words of data are transferred. ...

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If a coprocessor instruction busy-waits then CPPASS is asserted on every cycle until the coprocessor instruction is executed interrupt occurs during busy-waiting then CPPASS is driven LOW and the coprocessor should stop the coprocessor instruction execution. Another output, ...

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Coprocessor Interface 8.3 MCR/MRC These cycles look very similar to STC/LDC. An example with a busy-wait state is shown in Figure 8-4. Fetch Coprocessor pipeline CLK MCR/MRC CPINSTR[31:0] nCPMREQ CPPASS CPLATECANCEL CHSDE[1:0] CHSEX[1:0] CPDOUT[31:0] MCR CPDIN[31:0] MRC First, nCPMREQ is ...

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Interlocked MCR If the data for an MCR operation is not available inside the ARM9EJ-S core pipeline during its first Decode cycle, then the ARM9EJ-S core pipeline interlocks for one or more cycles until the data is available. An ...

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Coprocessor Interface 8.4 CDP instructions usually execute in a single cycle. Like all the previous cycles, nCPMREQ is driven LOW to signal when an instruction is entering the Decode and then the Execute stage of the pipeline. If the instruction ...

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Privileged instructions The coprocessor might restrict certain instructions for use in privileged modes only this, the coprocessor has to track the nCPTRANS output. Figure 8-7 shows how nCPTRANS changes after a mode change. Fetch Coprocessor pipeline CLK ...

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Coprocessor Interface 8.6 Busy-waiting and interrupts The coprocessor is permitted to stall (busy-wait) the processor during the execution of a coprocessor instruction if, for example still busy with an earlier coprocessor instruction so, the coprocessor associated ...

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CPBURST The CPBURST signal is used by the external coprocessor to indicate the number of words to be transferred in an LDC or STC operation. CPBURST is used by the ARM926EJ-S memory system to optimize LDC/STC instructions that access ...

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Coprocessor Interface 8.8 CPABORT The CPABORT signal being asserted HIGH indicates that an aborted. CPABORT is asserted in the cycle after the Memory stage of the aborting LDC/STC instruction. This is shown in Figure 8-9. Coprocessor pipeline CLK CPINSTR[31:0] nCPMREQ ...

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The nCPINSTRVALID signal indicates if the instruction currently on the CPINSTR bus is valid, and should be decoded by the coprocessor. If nCPINSTRVALID is 1, then the instruction should not be decoded by the coprocessor and an ABSENT ...

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Coprocessor Interface 8.10 Connecting multiple external coprocessors If multiple coprocessors are connected to the ARM926EJ-S processor, then outputs of the various coprocessors must be combined to form a single set of coprocessor inputs. The coprocessor handshake signals are combined together ...

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Chapter 9 Instruction Memory Barrier This chapter describes the ARM926EJ-S Instruction Memory Barrier (IMB) operation. It contains the following sections: • About the instruction memory barrier operation on page 9-2 • IMB operation on page 9-3 • Example IMB sequences ...

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Instruction Memory Barrier 9.1 About the instruction memory barrier operation Whenever code is treated as data, for example self-modifying code, or loading code into memory, then a sequence of instructions called an Instruction Memory Barrier (IMB) operation must be used ...

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IMB operation To ensure consistency between data and instruction sides, you must take the following steps: 1. Clean the DCache 2. Drain the write buffer 3. Synchronize data and instruction streams in level two AHB subsystems 4. Invalidate the ...

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Instruction Memory Barrier 9.2.4 Invalidate the ICache The ICache must be invalidated to remove any stale copies of instructions that are no longer valid. If the ICache is not being used, or the modified regions are not in cachable areas ...

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Example IMB sequences The following sequence corresponds to steps 1-4 in IMB operation on page 9-3: The following sequence illustrates an IMB sequence used after modifying a single instruction (for example, setting a software breakpoint), with no external synchronization ...

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Instruction Memory Barrier 9-6 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D ...

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Chapter 10 Embedded Trace Macrocell Support This chapter describes the Embedded Trace Macrocell (ETM) support for the ARM926EJ-S processor. It contains the following section: • About Embedded Trace Macrocell support on page 10-2. ARM DDI0198D Copyright © 2001-2003 ARM Limited. ...

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Embedded Trace Macrocell Support 10.1 About Embedded Trace Macrocell support To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an Embedded Trace Macrocell (ETM). For more information on the ETM, see the ETM9 Technical Reference ...

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Stalling the core with FIFOFULL affects real-time operating performance. If connected, an ETM must be disabled during normal ARM926EJ-S processor operation to prevent FIFOFULL adversely affecting the ARM926EJ-S processor performance. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. ...

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Embedded Trace Macrocell Support 10-4 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D ...

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Chapter 11 Debug Support This chapter describes the debug support for the ARM926EJ-S processor. It contains the following section: • About debug support on page 11-2. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 11-1 ...

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Debug Support 11.1 About debug support Debug support is implemented by using the ARM9EJ-S core embedded within the ARM926EJ-S processor. Full details of the debug support provided by the ARM9EJ-S core are described in the ARM9EJ-S Technical Reference Manual. Debug ...

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To perform an access using scan chain 15, you must: 1. During the SHIFT-DR state of the TAP state machine, shift in the read/write bit, register address, and register data value for writing, with bit 32 set to 1. For ...

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Debug Support The mapping of the register address field to the CP15 registers is shown in Table 11-2. Writes to either the cache operations register (CRn = c7) or the TLB operations register (CRn = c8), which require a form ...

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Chapter 12 Power Management This chapter describes the power management facilities provided by the ARM926EJ-S processor. It contains the following section: • About power management on page 12-2. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 12-1 ...

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Power Management 12.1 About power management The power management facilities provided by the ARM926EJ-S processor are: • Dynamic power management (wait for interrupt mode) • Static power management (leakage control) on page 12-3. 12.1.1 Dynamic power management (wait for interrupt ...

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When the ARM926EJ-S has entered a low-power state, all of the main internal clocks are stopped, including the clock for the ARM9EJ-S core. However, the ARM9EJ-S is active if DBGTCKEN is asserted. This enables values to be written in the ...

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Power Management MMU RAMs The RAM used to implement the MMU can be safely powered down if the MMU has been disabled (using CP15 control register c1) and it contains no valid entries.While the MMU is disabled, only explicit CP15 ...

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Appendix A Signal Descriptions This appendix describes the ARM926EJ-S processor input and output signals. It contains the following sections: • Signal properties and requirements on page A-2 • AHB related signals on page A-3 • Coprocessor interface signals on page ...

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Signal Descriptions A.1 Signal properties and requirements To ensure ease of integration of the ARM926EJ-S processor into embedded applications, and to simplify synthesis flow, the following design techniques have been used: • a single rising edge clock times all activity ...

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A.2 AHB related signals Table A-1 describes the ARM926EJ-S processor AHB related signals. Signal name DHADDR[31:0] DHBL[3:0] DHBURST[2:0] DHBUSREQ DHCLKEN DHGRANT DHLOCK DHPROT[3:0] DHRDATA[31:0] DHREADY DHRESP[1:0] DHSIZE[2:0] DHTRANS[1:0] DHWDATA[31:0] DHWRITE HRESETn IHADDR[31:0] IHBURST[2:0] IHBUSREQ IHCLKEN ARM DDI0198D Copyright © 2001-2003 ...

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Signal Descriptions Signal name IHGRANT IHLOCK IHPROT[3:0] IHREADY IHRDATA[31:0] IHRESP[1:0] IHSIZE[2:0] IHTRANS[1:0] IHWRITE A-4 Copyright © 2001-2003 ARM Limited. All rights reserved. Table A-1 AHB related signals (continued) Direction Description Input AHB bus grant signal (instruction). Output AHB bus lock ...

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A.3 Coprocessor interface signals Table A-2 describes the ARM926EJ-S processor coprocessor interface signals. Name CPABORT CPBURST[3:0] CPCLKEN Coprocessor clock enable CPDIN[31:0] Coprocessor write data CPDOUT[31:0] Coprocessor read data CPEN Coprocessor enable CPINSTR[31:0] Coprocessor instruction data CPPASS CPLATECANCEL CHSDE[1:0] Coprocessor handshake ...

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Signal Descriptions Name CHSEX[1:0] Coprocessor handshake execute nCPINSTRVALID Coprocessor valid instruction nCPMREQ Not coprocessor instruction request nCPTRANS Not coprocessor memory translate A-6 Copyright © 2001-2003 ARM Limited. All rights reserved. Table A-2 Coprocessor interface signals (continued) Direction Description Input The ...

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A.4 Debug signals Table A-3 describes the ARM926EJ-S processor debug signals. Name COMMRX Communications channel receive COMMTX Communications channel transmit DBGACK Debug acknowledge DBGDEWPT Data watchpoint DBGEN Debug enable DBGEXT[1:0] EmbeddedICE-RT external input DBGIEBKPT Instruction breakpoint DBGINSTREXEC Instruction executed ARM ...

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Signal Descriptions Name DBGRNG[1:0] EmbeddedICE-RT range out DBGRQI Internal debug request EDBGRQ External debug request A-8 Copyright © 2001-2003 ARM Limited. All rights reserved. Table A-3 Debug signals (continued) Direction Description Output Indicates that the corresponding EmbeddedICE-RT watchpoint register has ...

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A.5 JTAG signals Table A-4 describes the ARM926EJ-S processor JTAG signals. Name DBGIR[3:0] TAP controller instruction register DBGnTRST Not test reset DBGnTDOEN Not DBGTDO enable DBGSCREG[4:0] DBGSDIN External scan chain serial input data DBGSDOUT External scan chain serial data output ...

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Signal Descriptions A.6 Miscellaneous signals Table A-5 describes the miscellaneous signals on the ARM926EJ-S processor. Name BIGENDINIT CLK CFGBIGEND ARM9EJ-S core endianness configuration EXTEST INTEST nFIQ Not fast interrupt request nIRQ Not interrupt request SCANENABLE STANDBYWFI A-10 Copyright © 2001-2003 ...

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Name TAPID[31:0] TESTMODE VINITHI Exception vector location at reset ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. Table A-5 Miscellaneous signals (continued) Direction Description Input This is the ARM926EJ-S device identification (ID) code test data register, accessible from ...

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Signal Descriptions A.7 ETM interface signals Table A-6 describes the ARM926EJ-S processor ETM interface signals. Name ETMBIGEND ETMCHSD[1:0] ETMCHSE[1:0] ETMDA[31:0] ETMDABORT ETMDBGACK ETMDMAS[1:0] ETMDMORE ETMDnMREQ ETMDnRW ETMDSEQ ETMEN ETMHIVECS ETMIA[31:0] ETMIABORT ETMID15TO11[15:11] ETMID31TO25[31:25] ETMIJBIT ETMInMREQ ETMINSTREXEC ETMINSTRVALID ETMISEQ A-12 Copyright ...

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