ATMEGA324-20AU ATMEL Corporation, ATMEGA324-20AU Datasheet

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ATMEGA324-20AU

Manufacturer Part Number
ATMEGA324-20AU
Description
Manufacturer
ATMEL Corporation
Datasheet
Features
High-performance, Low-power AVR
Advanced RISC Architecture
Nonvolatile Program and Data Memories
JTAG (IEEE std. 1149.1 Compliant) Interface
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltages
Speed Grades
Power Consumption at 1 MHz, 3V, 25C for ATmega644
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-chip 2-cycle Multiplier
– 16/32/64K Bytes of In-System Self-Programmable Flash
– Optional Boot Code Section with Independent Lock Bits
– 512B/1K/2K Bytes EEPROM
– 1/2/4K Bytes Internal SRAM
– Programming Lock for Software Security
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel, 10-bit ADC
– Byte-oriented Two-wire Serial Interface
– One/Two Programmable Serial USART (ATmega644, ATmega164/324)
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
– 1.8 - 5.5V for ATmega164/324/644V
– 2.7 - 5.5V for ATmega164/324/644
– ATmega164/324/644V: 0 - 4MHz @ 1.8 - 5.5V, 0 - 10MHz @ 2.7 - 5.5V
– ATmega164/324/644: 0 - 10MHz @ 2.7 - 5.5V, 0 - 20MHz @ 4.5 - 5.5V
– Active: 240 µA @ 1.8V, 1MHz
– Power-down Mode: 0.1 µA @ 1.8V
Mode
and Extended Standby
Endurance: 10,000 Write/Erase Cycles
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
Endurance: 100,000 Write/Erase Cycles
Differential mode with selectable gain at 1x, 10x or 200x
®
8-bit Microcontroller
Note: This is a summary document. A complete document
is available on our Web site at www.atmel.com.
8-bit
Microcontroller
with 16/32/64K
Bytes In-System
Programmable
Flash
ATmega164/V
ATmega324/V
ATmega644/V
Advance
Information
Summary
2593AS–AVR–06/05

Related parts for ATMEGA324-20AU

ATMEGA324-20AU Summary of contents

Page 1

... Active: 240 µA @ 1.8V, 1MHz – Power-down Mode: 0.1 µA @ 1.8V ® 8-bit Microcontroller Note: This is a summary document. A complete document is available on our Web site at www.atmel.com. 8-bit Microcontroller with 16/32/64K Bytes In-System Programmable Flash ATmega164/V ATmega324/V ATmega644/V Advance Information Summary 2593AS–AVR–06/05 ...

Page 2

Pin Configurations ATmega164/324/644 2 Figure 1. Pinout ATmega164/324 (PCINT8/XCK0/T0) PB0 (PCINT9/CLKO/T1) PB1 (PCINT10/INT2/AIN0) PB2 (PCINT11/OC0A/AIN1) PB3 (PCINT12/OC0B/SS) PB4 (PCINT13/MOSI) PB5 (PCINT14/MISO) PB6 (PCINT15/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0) PD0 (PCINT25/TXD0) PD1 (PCINT26/RXD1/INT0) PD2 (PCINT27/TXD1/INT1) PD3 (PCINT28/XCK1/OC1B) PD4 (PCINT29/OC1A) ...

Page 3

Figure 2. Pinout ATmega644 (PCINT8/XCK0/T0) PB0 (PCINT9/CLKO/T1) PB1 (PCINT10/INT2/AIN0) PB2 (PCINT11/OC0A/AIN1) PB3 (PCINT12/OC0B/SS) PB4 (PCINT13/MOSI) PB5 (PCINT14/MISO) PB6 (PCINT15/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0) PD0 (PCINT25/TXD0) PD1 (PCINT26/INT0) PD2 (PCINT27/INT1) PD3 (PCINT28/OC1B) PD4 (PCINT29/OC1A) PD5 (PCINT30/OC2B/ICP) PD6 ...

Page 4

Disclaimer Overview Block Diagram Figure 3. Block Diagram VCC Power Supervision RESET POR / BOD & RESET Watchdog GND Timer Watchdog Oscillator XTAL1 Oscillator Circuits / Clock Generation XTAL2 NOTE: The USART 1 is only available for ATmega164/324 ATmega164/324/644 4 ...

Page 5

... Comparison Between ATmega164, ATmega324 and ATmega644 2593AS–AVR–06/05 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle ...

Page 6

Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) RESET XTAL1 XTAL2 AVCC ATmega164/324/644 6 Digital supply voltage. Ground. Port A serves as analog inputs to the Analog-to-digital Converter. Port A also serves ...

Page 7

AREF 2593AS–AVR–06/05 This is the analog reference pin for the Analog-to-digital Converter. 7 ...

Page 8

Register Summary Address Name Bit 7 (0xFF) Reserved - (0xFE) Reserved - (0xFD) Reserved - (0xFC) Reserved - (0xFB) Reserved - (0xFA) Reserved - (0xF9) Reserved - (0xF8) Reserved - (0xF7) Reserved - (0xF6) Reserved - (0xF5) Reserved - (0xF4) ...

Page 9

Address Name Bit 7 (0xBF) Reserved - (0xBE) Reserved - (0xBD) TWAM TWAM6 (0xBC) TWCR TWINT (0xBB) TWDR (0xBA) TWAR TWA6 (0xB9) TWSR TWS7 (0xB8) TWBR (0xB7) Reserved - (0xB6) ASSR - (0xB5) Reserved - (0xB4) OCR2B (0xB3) OCR2A (0xB2) ...

Page 10

Address Name Bit 7 (0x7D) Reserved - (0x7C) ADMUX REFS1 (0x7B) ADCSRB - (0x7A) ADCSRA ADEN (0x79) ADCH (0x78) ADCL (0x77) Reserved - (0x76) Reserved - (0x75) Reserved - (0x74) Reserved - (0x73) PCMSK3 PCINT31 (0x72) Reserved - (0x71) Reserved ...

Page 11

Address Name Bit 7 0x1B (0x3B) PCIFR - 0x1A (0x3A) Reserved - 0x19 (0x39) Reserved - 0x18 (0x38) Reserved - 0x17 (0x37) TIFR2 - 0x16 (0x36) TIFR1 - 0x15 (0x35) TIFR0 - 0x14 (0x34) Reserved - 0x13 (0x33) Reserved - ...

Page 12

Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract Constant ...

Page 13

Mnemonics Operands BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register CBI P,b Clear Bit in I/O Register LSL Rd Logical Shift Left LSR Rd Logical ...

Page 14

Mnemonics Operands IN Rd Port OUT P, Rr Out Port PUSH Rr Push Register on Stack POP Rd Pop Register from Stack MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break ATmega164/324/644 14 Description ...

Page 15

Ordering Information ATmega164 (3) Speed (MHz) Power Supply 10 1.8 - 5.5V 20 2.7 - 5.5V Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum ...

Page 16

... Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 44M1 ATmega164/324/644 16 Ordering Code Package (2) ATmega324V-10AU 44A (2) ATmega324V-10PU 40P6 (2) ATmega324V-10MU 44M1 (2) ATmega324-20AU 44A (2) ATmega324-20PU 40P6 (2) ATmega324-20MU 44M1 ” on page 310. CC Package Type (1) Operational Range Industrial ...

Page 17

ATmega644 (3) Speed (MHz) Power Supply 10 1.8 - 5.5V 20 2.7 - 5.5V Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. ...

Page 18

Packaging Information 44A PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and ...

Page 19

A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). ...

Page 20

D Marked Pin TOP VIEW BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3. 2325 Orchard Parkway San Jose, CA 95131 R ATmega164/324/644 20 E Pin #1 Corner Pin ...

Page 21

... Errata ATmega164 Rev. A ATmega324 Rev. A ATmega644 Rev. A 2593AS–AVR–06/05 Not sampled. Not sampled. • EEPROM read from application code does not work in Lock Bit Mode 3. 1. EEPROM read from application code does not work in Lock Bit Mode 3 When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the application code ...

Page 22

Datasheet Revision History Rev. 2593A-06/05 ATmega164/324/644 22 Please note that the referring page numbers in this section are referred to this docu- ment. The referring revision in this section are referring to the document revision. 1.Initial revision. 2593AS–AVR–06/05 ...

Page 23

... Atmel does not make any commitment to update the information contained herein. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © Atmel Corporation 2005. All rights reserved. Atmel are the registered trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...

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