CS8414 Cirrus Logic, Inc., CS8414 Datasheet
CS8414
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CS8414 Summary of contents
Page 1
... The CS8413 has a configurable internal buffer memory, read through a parallel port, which may be used to buffer channel status, auxiliary data, and/or user data. The CS8414 de-multiplexes the channel, user, and va- lidity data directly to serial output pins with dedicated output pins for the most important channel status bits. ...
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... TTL/CMOS Levels .................................................................................... 35 Transformers ............................................................................................ 35 APPENDIX B: SUGGESTED RESET CIRCUIT FOR CS8414 ........................ 36 Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “ ...
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... VD+, VA ± 5%) A Symbol except RXP, RXN V IH except RXP, RXN 200 µA) V (VD -3.2 mA (Note (Note 3) MCK t j CS8413 CS8414 Min Max Units - 6 ±10 mA -0.3 (VD+) + 0 -55 125 °C -65 150 °C Min Typ Max Units 4.75 5.0 5.25 ...
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... RD/WR low (writing) t dcssw RD/WR low (writing) t csdhw RD/WR high (reading) t csddr RD/WR high (reading) t csdhr t adcss t csl t t rwcss csrwi t dcssw t csddr CS8413 Parallel Port timing CS8413 CS8414 Min Typ Max 200 - - HYST = 20 pF) L Min Typ Max 13 ...
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... CS8413 the edge is selectable. The table is defined for the CS8413 with control reg. 2 bit 0, SCED, set to one, and for the CS8414 in formats and 7. For the other formats, the table and figure edges must be reversed (i.e. “rising” to “falling” and vice versa.) ...
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... Figure 1. CS8413 Typical Connection Diagram +5V Analog +5V Digital 22 7 VA+ VD+ 21 AGND 9 RXP SDATA FSYNC 10 RXN CS8414 13 CS12/FCK 16 SEL 25 ERF 6 C/E-F bits 20 FILT DGND 8 Figure 2. CS8414 Typical Connection Diagram CS8413 CS8414 0.1 µ MCK 11 Audio 12 SCK Data 26 Processor 25 ERF 14 INT Audio 24 CS Data 23 Processor or A0-A4 Microcontroller 0.1 µF ...
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... As a master, SCK is always MCK divided by four, producing a frequency of 64xF FSYNC can be programmed divided version of MCK or it can be generated directly from the in- coming data stream. In the CS8414, FSYNC is al- ways generated from the incoming data stream. When FSYNC is generated from the data, its edges ), and FSYNC (F ...
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... FSYNC from MCK instead of from the incoming data. CS8413 DESCRIPTION The CS8413 is more flexible than the CS8414 but requires a microcontroller or DSP to load internal registers. The CS8414 does not have internal regis- ters so it may be used in a stand-alone mode where a microprocessor or DSP is not available ...
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... Further information, including timing, on the flags can be found in the Buffer Memory section. The next five CRCE/CRC1, and CSDIF/CRC2, are latches which are set when their corresponding conditions occur, and are reset when SR1 is read. Interrupt CS8413 CS8414 11 FSYNC Audio 12 Serial SCK ...
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... Block boundary violations also cause CRC1,2 or CRCE to be set. IEnable register 1, which occupies the same ad- dress space as status register 1, contains interrupt enable bits for all conditions in status register 1. A “1” bit location enables the same bit location in CS8413 CS8414 ...
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... In control register 1, when RST is low, all outputs are reset except MCK (FSYNC and SCLK are high impedance). The CS8413 should be reset imediate- ly after power-up and any time the user performs a CS8413 CS8414 Sample Frequency 0 0 Out of Range ...
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... SDATA can have a variety of relationships to each other, and the polarity of SCK can be controlled. The large variety of audio data formats provides an 12 CS8413 CS8414 easy interface to most DSPs and other audio pro- cessors. SDATA is normally just audio data, but special modes are provided that output received bi- phase data, or received NRZ data with zeros substi- tuted for preamble ...
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... MSB LSB 24 Bits, Incl. Aux LSB 24 Bits, Incl. Aux LSB 16 Bits LSB 32 Bits AUX MSB VUCP LSB Bi-Phase Mark Data CS8413 CS8414 32 Bits 32 Clocks 32 Clocks Right Sample 24 Bits, Incl. Aux LSB MSB 24 Bits, Incl. Aux LSB MSB 16 Bits MSB LSB 18 Bits ...
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... CS8413, the serial port will eventually be re- read or a sample will be missed. When this occurs, the SLIP bit in SR1 will be set. 14 CS8413 CS8414 SDATA can take on five formats in the normal se- rial port modes. The first format (see Figure 10), MSB First, has the MSB aligned with the start of a sample frame ...
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... FLAG0 will generate a low pulse on the interrupt pin. The level of FLAG0 indicates DS240F1 CS8413 CS8414 which two bytes the part will write next, thereby in- dicating which two bytes are free to be read. FLAG1 is buffer mode dependent and is discussed in the individual buffer mode sections ...
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... The CS2/CS1 bit in CR1 selects which channel is stored in the buffer typical system sending stereo data, the channel sta- tus data for each channel would be identical. CS8413 CS8414 ...
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... CS8413 is four times larger allowing FLAG0 to be used to monitor both. Block (384 Audio Samples (Expanded (Addresses are in Hex CS8413 CS8414 ...
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... CS data for channel A and locations 10H to 17H con- taining CS data for channel B. Both CS buffers can be monitored using FLAG1 and FLAG2 as de- scribed in the BUFFER MODE 1 section. CS8413 CS8414 (Addresses are in Hex ...
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... SCED = 1 Figure 15. RAM/Buffer - Write and Interrupt Timing DS240F1 CS8413 CS8414 rupt line, flags, and the RAM write line. SCK is 64 times the incoming sample frequency, and is the same SCK output in master mode. The FSYNC shown is valid for all master modes except the I compatible mode ...
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... Status and IEnable Reg- isters section. CS8414 DESCRIPTION The CS8414 does not need a microprocessor to handle the non-audio data (although a micro may be used with the C and U serial ports). Instead, ded- icated pins are available for the most important channel status bits ...
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... Figure 18 illus- trates formats 12 and 13. Format 14 is reserved and not presently used, and format 15 causes the CS8414 to go into a reset state. While in reset all outputs will be inactive except MCK. The CS8414 comes out of reset at the first block boundary after ...
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... Left MSB LSB Left LSB MSB LSB 16 Bits Left LSB LSB MSB 18 Bits Left MSB LSB MSB Figure 17. CS8414 Audio Serial Port Formats CS8413 CS8414 Right MSB LSB MSB Right MSB LSB MSB Right MSB LSB MSB Right MSB LSB Right ...
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... SCK (out) SDATA (out) * Error flags are not accurate in these modes Figure 18. Special Audio Port Formats 12 and 13 leaving the reset state. The CS8414 should be reset immediately after power-up and any time the user performs a system-wide reset. See Appendix B for a suggested reset circuit. ...
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... This error is indicated when the CS8414 calculated CRC value does not match the CRC byte of the channel status block or when a block boundary changes (as in re- moving samples while editing). The parity error oc- curs when the incoming sub-frame does not have even parity as specified by the standards ...
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... C9, is the inverse of channel status bit 9, which gives some indication of channel mode. (Bit 9 is also defined as bit 1 of byte 1.) When Ce, defined as CRCE, is low, the CS8414 calculated CRC value does not match the received CRC value. This signal may be used to qualify Ca through Cd through Ce are being displayed, Ce going low can indicate not to update the display ...
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... L bit to 1 (original). To support this feature, Ce, in the consumer mode, is defined as IGCAT (ignorant category) which is low for the “general” (0000000) and “A/D converter without copyright information” (01100xx) catego- ries. 26 CS8413 CS8414 DS240F1 ...
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... A0 SCK A4/FCK INT CS8413 CS8414 DATA BUS BIT 1 DATA BUS BIT 0 SERIAL OUTPUT DATA ERROR FLAG CHIP SELECT READ/WRITE SELECT ANALOG POWER ANALOG GROUND FILTER MASTER CLOCK ADDRESS BUS BIT 0 ADDRESS BUS BIT 1 ADDRESS BUS BIT 2 ADDRESS BUS BIT 3 ...
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... Parallel port address bus that selects the internal memory location to be read from or written to. Note that A4 is the dual function pin A4/FCK as described above. D0-D7 - Data Bus, PINS 27-28, 1-6. Parallel port data bus used to check status, read or write control words, or read internal buffer memory. 28 CS8413 CS8414 DS240F1 ...
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... RS422 compatible line receivers. Described in detail in Appendix A. Phase Locked Loop MCK - Master Clock, PIN 19. Low jitter clock output of 256 times the received sample frequency. FILT - Filter, PIN 20. An external 470 resistor and 0.068µF capacitor are required from the FILT pin to analog ground. DS240F1 CS8413 CS8414 29 ...
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... PIN DESCRIPTIONS: CS8414 CHANNEL STATUS OUTPUT CS d/FREQ REPORT 1 CS c/FREQ REPORT 0 CS b/ERROR CONDITION 2 CS a/ERROR CONDITION 1 CS 0/ERROR CONDITION 0 DIGITAL POWER DIGITAL GROUND RECEIVE POSITIVE RECEIVE NEGATIVE FRAME SYNC SERIAL DATA CLOCK CHANNEL SELECT/FCLOCK USER DATA OUTPUT Power Supply Connections VD+ - Positive Digital Power, PIN 7 ...
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... The channel status block output is high for the first four bytes of channel status and low for the last 20 bytes. SEL - Select, PIN 16. Control pin that selects either channel status information (SEL = 1) or error and frequency information (SEL = displayed on six of the following pins. DS240F1 CS8413 CS8414 31 ...
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... RS422 compatible line receivers. Phase Locked Loop MCK - Master Clock, PIN 19. Low jitter clock output of 256 times the received sample frequency. FILT - Filter, PIN 20. An external 470 resistor and 0.068µF capacitor is required from FILT pin to analog ground. 32 CS8413 CS8414 DS240F1 ...
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... SEATING PLANE e DIM DS240F1 D INCHES MIN MAX 0.093 0.104 0.004 0.012 0.013 0.020 0.009 0.013 0.697 0.713 17.70 0.291 0.299 0.040 0.060 0.394 0.419 10.00 0.016 0.050 0° 8° CS8413 CS8414 MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 18.10 7.40 7.60 1.02 1.52 10.65 0.40 1.27 0° 8° 33 ...
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... APPENDIX A: RS422 RECEIVER INFORMATION The RS422 receivers on the CS8413 and CS8414 are designed to receive both the professional and consumer interfaces, and meet all specifications listed in the digital audio standards. Figure A20 il- lustrates the internal schematic of the receiver por- tion of both chips. The receiver has a differential input ...
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... RS422 receivers or TTL/CMOS logic drive the CS8413/14 receiver section. Transformers Please refer Application Note AN134: AES and S/PDIF Recommended Transformers for further information. CS8413/14 0.01 µF RXP RXN 0.01 µF CS8413 CS8414 TTL/CMOS CS8413/14 Gate 0.01 µF RXP RXN 0.01 µF Figure 24. TTL/CMOS Interface 35 ...
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... APPENDIX B: SUGGESTED RESET CIRCUIT FOR CS8414 CS8414 The CS8414 should be reset immediately after power-up and any time the user issues a system- wide reset. This is accomplished by pulling all four Figure 25. CS8414 Reset Circuit Mode Select pins high. Figure 25 shows a simple circuit to implement this ...
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Notes • ...
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