CS8416CS Cirrus Logic, Inc., CS8416CS Datasheet
CS8416CS
Available stocks
Related parts for CS8416CS
CS8416CS Summary of contents
Page 1
... De-emphasis Filter AES3 C & U bit S/PDIF Data Buffer Decoder Format Detect SDA/ SCL/ CDOUT CCLK Copyright © Cirrus Logic, Inc. 2007 (All Rights Reserved) CS8416 ® Control Port Software Mode and General Description and Ordering Information 2. VL DGND OMCK Serial Audio ...
Page 2
General Description The CS8416 is a monolithic CMOS device that receives and decodes one of eight stereo pairs of digital audio data according to the IEC60958, S/PDIF, EIAJ CP1201, or AES3 interface standards. The CS8416 has a serial digital audio ...
Page 3
TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 6 SPECIFIED OPERATING CONDITIONS ............................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 6 DC ELECTRICAL CHARACTERISTICS................................................................................................. 7 DIGITAL INPUT CHARACTERISTICS ................................................................................................... 7 DIGITAL INTERFACE SPECIFICATIONS.............................................................................................. 7 SWITCHING CHARACTERISTICS ........................................................................................................ 8 SWITCHING CHARACTERISTICS - SERIAL ...
Page 4
Control2 (02h) ............................................................................................................................. 38 14.5 Control3 (03h) ............................................................................................................................. 39 14.6 Control4 (04h) ............................................................................................................................. 39 14.7 Serial Audio Data Format (05h) ................................................................................................... 40 14.8 Receiver Error Mask (06h) ......................................................................................................... 41 14.9 Interrupt Mask (07h) .................................................................................................................... 41 14.10 Interrupt Mode MSB ...
Page 5
LIST OF FIGURES Figure 1. Audio Port Master Mode Timing ................................................................................................... 9 Figure 2. Audio Port Slave Mode and Data Input Timing............................................................................. 9 Figure 3. SPI Mode Timing ........................................................................................................................ 10 Figure 4. I²C Mode Timing ......................................................................................................................... 11 Figure 5. Typical ...
Page 6
CHARACTERISTICS AND SPECIFICATIONS All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and T = 25°C. A SPECIFIED OPERATING CONDITIONS (AGND, DGND ...
Page 7
DC ELECTRICAL CHARACTERISTICS (AGND = DGND = 0 V; all voltages with respect to 0 V.) Parameters Power-Down Mode (Notes 2, 4) Supply Current in power-down Normal Operation (Notes 3, 4) Supply Current at 48 kHz frame rate Supply Current ...
Page 8
SWITCHING CHARACTERISTICS (Inputs: Logic Logic 1 = VL; C Parameter RST Pin Low Pulse Width PLL Clock Recovery Sample Rate Range RMCK Output Jitter RMCK Output Duty-Cycle RMCK/OMCK Maximum Frequency Notes: 5. Typical RMS cycle-to-cycle jitter. ...
Page 9
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS (Inputs: Logic Logic 1 = VL; C Parameter OSCLK/OLRCK Active Edge to SDOUT Output Valid Master Mode RMCK to OSCLK active edge delay RMCK to OLRCK delay OSCLK and OLRCK ...
Page 10
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (Inputs: Logic Logic 1 = VL; C Parameter CCLK Clock Frequency CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN ...
Page 11
SWITCHING CHARACTERISTICS - CONTROL PORT- I²C FORMAT (Inputs: Logic Logic 1 = VL; C Parameter SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock ...
Page 12
PIN DESCRIPTION - SOFTWARE MODE 2.1 TSSOP Pin Description RXP3 RXP2 RXP1 RXP0 RXN VA AGND FILT RST RXP4 RXP5 RXP6 RXP7 AD0 / CS Pin Pin # Name Analog Power (Input) - Analog power supply. Nominally +3.3 V. ...
Page 13
Pin Pin # Name Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or S/PDIF encoded digital data. Used along with RXP[7:0] to form an AES3 differential input. In single- RXN 5 ended operation this should be ...
Page 14
QFN Pin Description RXP0 RXN VA AGND FILT RST RXP4 Pin Pin # Name Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little noise possible since noise on this ...
Page 15
Pin Pin # Name RXP0 1 RXP1 28 Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or RXP2 27 S/PDIF encoded digital data. The RXP[7:0] inputs comprise the 8:2 S/PDIF Input Multiplexer. The select RXP3 26 ...
Page 16
PIN DESCRIPTION - HARDWARE MODE 3.1 TSSOP Pin Description RXP3 RXP2 RXP1 RXP0 RXN VA AGND FILT RST RXSEL1 RXSEL0 TXSEL1 TXSEL0 NV / RERR Pin Name Pin # Analog Power (Input) - Analog power supply. Nominally +3.3 V. ...
Page 17
Pin Name Pin # System Clock (Input) - OMCK System Clock Mode is enabled by a transition (rising edge active) on OMCK 25 OMCK after reset. When enabled, the clock signal input on this pin is automatically output through RMCK ...
Page 18
QFN Pin Description RXP0 RXN VA AGND FILT RST RXSEL1 Pin Name Pin # Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little VA 3 noise as possible since noise on this ...
Page 19
Pin Name Pin # Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or S/PDIF encoded digital data. Used along with RXP[3:0] to form an AES3 differential input. In single- RXN 2 ended operation this should be ...
Page 20
TYPICAL CONNECTION DIAGRAMS * Ferrite Bead +3.3 V Analog Supply * 10 F μ 0.1 F μ AES3 / S/PDIF Sources VL Microcontroller * A separate analog supply is only necessary in applications where RMCK is used ...
Page 21
Ferrite Bead +3.3 V Analog Supply ** μ μ 0 AES3 / S/PDIF *** Sources VL Hardware Control * These pins must be pulled high low to DGND through ...
Page 22
APPLICATIONS 5.1 Reset, Power-Down and Start-Up When RST is low, the CS8416 enters a low power mode and all internal states are reset, including the con- trol port and registers, and the outputs are muted. In Software Mode, when ...
Page 23
GENERAL DESCRIPTION The CS8416 is a monolithic CMOS device that receives and decodes audio data according to the AES3, IEC60958, S/PDIF, and EIAJ CP1201 interface standards. The CS8416 provides an 8:2 multiplexer to select between eight inputs for decoding ...
Page 24
When in slave mode, the serial audio output port cannot be set for right-justified data. The CS8416 allows immediate mute of the serial audio output port audio data by the MUTESAO bit of Control Register ...
Page 25
Slip/Repeat Behavior When using the serial audio output port in slave mode with an OLRCK input that is asynchronous to the incoming AES3 data, the interrupt bit OSLIP (bit 5 in the Interrupt 1 Status register, 0Dh) is provided ...
Page 26
AES11 Behavior When OLRCK is configured as a master, the positive or negative edge of OLRCK (depending on the setting of SOLRPOL in register 05h) will be within -1.0%(1/Fs) to 1.1%(1/Fs) from the start of the preamble X/Z. In ...
Page 27
S/PDIF RECEIVER The CS8416 includes an AES3/SPDIF digital audio receiver. The receiver accepts and decodes bi-phase encoded audio and digital data according to the AES3, IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. The re- ceiver consists of an analog ...
Page 28
The second output of the input multiplexer is used to provide the selected input as a source to be output on a GPO pin. This pass through signal is selected by TXSEL[2:0] in control port register 04h. This single- ended ...
Page 29
GENERAL PURPOSE OUTPUTS Three General Purpose Outputs (GPO) are provided to allow the equipment designer flexibility in configuring the CS8416. Fourteen signals are available to be routed to any of the GPO pins. The outputs of the GPO pins ...
Page 30
AND STATUS REPORTING 10.1 General While decoding the incoming bi-phase encoded data stream, the CS8416 has the ability to identify various error conditions. 10.1.1 Software Mode Software Mode allows the most flexibility in reading errors. When unmasked, bits in ...
Page 31
Non-Audio Detection An AES3 data stream may be used to convey non-audio data, thus it is important to know whether the in- coming AES3 data stream is digital audio or not. This information is typically conveyed in channel status ...
Page 32
STATUS AND USER-DATA HANDLING “Channel Status Buffer Management” on page 51 11.1 Software Mode In Software Mode, several options are available for accessing the Channel Status and User data that is en- coded in the received AES3/SPDIF stream. The ...
Page 33
PORT DESCRIPTION The control port is used to access the registers, allowing the CS8416 to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio ...
Page 34
I²C Mode In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There pin. Pins AD0 and AD1 form the two least significant bits ...
Page 35
PORT REGISTER QUICK REFERENCE Addr R/W Function 7 (HEX) 00 R/W Control0 01 R/W Control1 SWCLK 02 R/W Control2 DETCI 03 R/W Control3 GPO1SEL3 GPO1SEL2 GPO1SEL1 GPO1SEL0 GPO2SEL3 GPO2SEL2 GPO2SEL1 GPO2SEL0 04 R/W Control4 RUN 05 R/W Serial Audio ...
Page 36
Addr R/W Function 7 (HEX Channel B Status BC0[ Channel B Status BC1[ Channel B Status BC2[ Channel B Status BC3[ Channel B Status BC4[ Burst Preamble PC ...
Page 37
Higher Update Rate Phase Detector - Recovered master clock (RMCK) will have low in-band jitter, but increased wide-band jitter. Use this setting for the best performance when the output is connected to a delta- sigma digital-to-analog converter (DAC). ...
Page 38
RMCKF – Recovered Master Clock Frequency Default = ‘0’ 0 – RMCK output frequency is 256*F 1 – RMCK output frequency is 128*F CHS – Sets which channel's C data is decoded in the Receiver Channel Status register (0Ah). Default ...
Page 39
Gain -10 14.5 Control3 (03h GPO1SEL3 GPO1SEL2 GPO1SEL1 GPO1SEL[3:0] – GPO1 Source select. See Default = ‘0000’ GPO2SEL[3:0] – GPO2 Source select. See Default = ‘0000’ 14.6 Control4 (04h RUN RXD RXSEL2 RUN - ...
Page 40
TX_SEL[2:0] – Selects RXP0 to RXP7 as the input for GPO TX source Default =’001’ 000 – RXP0 001 – RXP1, etc 14.7 Serial Audio Data Format (05h SOMS SOSF SORES1 SOMS - Master/Slave Mode Selector Default = ...
Page 41
SOLRPOL - OLRCK clock polarity Default = ‘0’ SDOUT data is valid for the left channel when OLRCK is high SDOUT data is valid for the right channel when OLRCK is high. 14.8 Receiver Error Mask ...
Page 42
Receiver Channel Status (0Ah AUX3 AUX2 AUX1 The bits in this register can be associated with either channel the received data. The desired chan- nel is selected with the CHS bit of the ...
Page 43
DTS_CD – DTS_CD data was detected. Reserved – This bit may change state depending on the input audio data. DGTL_SIL – Digital Silence was detected: at least 2047 consecutive constant samples of the same 24-bit audio data on both channels. ...
Page 44
Interrupt 1 Status (0Dh PCCH OSLIP For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register was last read. A “0” means the associated interrupt ...
Page 45
OMCK/RMCK Ratio (18h ORR7 ORR6 ORR5 This register allows the calculation of the incoming sample rate by the host microcontroller from the equation ORR=Fso/Fsi. The Fso is determined by OMCK, whose frequency is assumed to be 256*Fso. ...
Page 46
MODE The CS8416 has a Hardware Mode that allows the device to operate without a microcontroller. Hardware Mode is selected by connecting the 47 k Ω pull-up/down resistor on the SDOUT pin to ground. Various pins change function in ...
Page 47
TX, which has an internal pull-down) MUST have an external pull-up or pull-down resistor as there are no internal pull-up or pull-down resistors for these startup conditions (set after reset). Pin ...
Page 48
Control4 Register (04h) RUN = 1 RXD = 0 RX_SEL[ RX_SEL[1:0] = RX_SEL[1:0] pins. TX_SEL[ TX_SEL[1:0] = TX_SEL[1:0] pins. Serial Audio Data Format Register (05h) SOMS = set by RCBL pull-up/down after reset. bits[6:0] = Set ...
Page 49
AES3/SPDIF/IEC60958 RECEIVER COMPONENTS 16.1 AES3 Receiver External Components The CS8416 AES3 receiver is designed to accept both the professional and consumer interfaces. The dig- ital audio specifications for professional use call for a balanced receiver, using XLR connectors, with ...
Page 50
RCA Phono 75 Ω 75 Ω Coax 0.01 μF Figure 18. Consumer Input Circuit TTL/CMOS Ω CS8416 7 5 Ω RXP0 7 5 Ω ...
Page 51
STATUS BUFFER MANAGEMENT 17.1 AES3 Channel Status (C) Bit Management The CS8416 contains sufficient RAM to store the first 5 bytes of C data for both A and B channels ( bits). The ...
Page 52
Received From Data AES3 Buffer Receiver D C Data Serial Output Figure 21. Channel Status Data Buffer Structure interrupt occurs Return Figure 22. Flowchart for Reading the E Buffer 8-bits 8-bits 5 words 19 ...
Page 53
FILTER 18.1 General An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming data stream simplified diagram of the PLL. When the PLL is locked to an bi-phase encoded input stream, it ...
Page 54
Capacitor Selection The type of capacitors used for the PLL filter can have a significant effect on receiver performance. Large or exotic film capacitors are not necessary as their leads and the required longer circuit board traces add undesirable ...
Page 55
Jitter Attenuation Shown in Figure 25 is the jitter attenuation plot. The AES3 and IEC60958-4 specifications state a maxi- mum jitter gain or peaking ...
Page 56
DIMENSIONS 28L SOIC (300 MIL BODY) PACKAGE DRAWING 1 b SEATING PLANE e DIM MIN A 0.093 A1 0.004 b 0.013 C 0.009 D 0.697 E 0.291 e 0.040 H 0.394 L 0.016 ∝ 0° INCHES NOM ...
Page 57
TSSOP (4.4 mm BODY) PACKAGE DRAWING TOP VIEW INCHES DIM MIN NOM 0.002 0.004 A2 0.03150 0.035 b 0.00748 0.0096 D 0.378 BSC 0.382 BSC E 0.248 0.2519 E1 0.169 0.1732 ...
Page 58
QFN (5 × BODY) PACKAGE DRAWING D Pin #1 Corner Top View INCHES DIM MIN 0.0000 b 0.0071 D 0.1969 BSC D2 0.1220 E 0.1969 BSC E2 0.1220 e 0.0197 BSC L 0.0197 Notes: ...
Page 59
INFORMATION Product Description 192 kHz Digital Audio CS8416 Interface Receiver Evaluation Board for CDB8416 CS8416 DS578F3 Pb-Free Grade Temp Range -10° to Commercial +70° C YES -40° to Automotive +85° CS8416 Package Container Order# Rail ...
Page 60
... OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. ...