DS2432P Maxim Integrated Products, DS2432P Datasheet

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DS2432P

Manufacturer Part Number
DS2432P
Description
Manufacturer
Maxim Integrated Products
Datasheet

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FEATURES
DESCRIPTION
The DS2432 combines 1024 bits of EEPROM, a 64-bit secret, an 8-byte register/control page with up to 5
user read/write bytes, a 512-bit SHA-1 engine and a fully-featured 1-Wire interface in a single chip. Each
DS2432 has its own 64-bit ROM registration number that is factory lasered into the chip to provide a
guaranteed unique identity for absolute traceability. Data is transferred serially via the 1-Wire protocol,
which requires only a single data lead and a ground return. The DS2432 has an additional memory area
called the scratchpad that acts as a buffer when writing to the main memory, the register page or when
installing a new secret. Data is first written to the scratchpad from where it can be read back. After the
data has been verified, a copy scratchpad command will transfer the data to its final memory location,
provided that the DS2432 receives a matching 160-Bit MAC. The computation of the MAC involves the
secret and additional data stored in the DS2432 including the device’s registration number. Only a new
secret can be loaded without providing a MAC. The SHA-1 engine can also be activated to compute
www.dalsemi.com
1128 bits of 5V EEPROM memory parti-
tioned into four pages of 256 bits, a 64-bit
write-only secret and up to 5 general purpose
read/write registers
On-chip 512-bit SHA-1 engine to compute
160-bit
(MAC) and to generate secrets
Write access requires knowledge of the secret
and the capability of computing and transmit-
ting a 160-bit MAC as authorization
Secret and data memory can be write-pro-
tected (all or page 0 only) or put in EPROM-
emulation mode (“write to 0”, page 1)
Unique, factory-lasered and tested 64-bit reg-
istration number assures absolute traceability
because no two parts are alike
Built-in multidrop controller ensures compati-
bility with other 1-Wire net products
Reduces control, address, data and power to a
single data pin
Directly connects to a single port pin of a mi-
croprocessor and communicates at up to 16.3k
bits per second
Overdrive mode boosts communication speed
to 142k bits per second
Low cost 6-lead TSOC surface mount pack-
age, or solder-bumped Flipchip package
Reads and writes over a wide voltage range of
2.8V to 5.25V from -40°C to +85°C
Message
Authentication
Codes
1 of 30
PIN ASSIGNMENT
See
specifications of packages.
ORDERING INFORMATION
DS2432P
DS2432P/T&R
DS2432X
EEPROM with SHA-1 Engine
www.dalsemi.com
1k-Bit Protected 1-Wire
1-WIRE
side view
GND
NC
TSOC (150mil)
6-lead TSOC package
Tape & Reel DS2432P
Flipchip package, tape & reel
top view
1
2
3
for mechanical
6
5
4
top view
NC
NC
NC
Preliminary
DS2432
040201

Related parts for DS2432P

DS2432P Summary of contents

Page 1

... Codes NC side view See www.dalsemi.com specifications of packages. ORDERING INFORMATION DS2432P DS2432P/T&R DS2432X Preliminary DS2432 ™ top view top view for mechanical 6-lead TSOC package Tape & Reel DS2432P Flipchip package, tape & reel 040201 ...

Page 2

PRELIMINARY 160-bit message authentication codes (MAC) when reading a memory page or to compute a new secret, instead of loading it. Applications of the DS2432 include intellectual property security, after-market management of consumables, and taper proof data carriers. OVERVIEW The ...

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PRELIMINARY 64-BIT LASERED ROM Each DS2432 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last eight bits are a ...

Page 4

PRELIMINARY 1-WIRE CRC GENERATOR Figure STAGE STAGE STAGE MEMORY MAP The DS2432 has four memory areas: data memory, secrets memory, register page with special function registers ...

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PRELIMINARY The secret can be installed either by copying data from the scratchpad to the secrets memory or by computation using the current secret and the scratchpad contents as partial secret. The secret cannot be read directly; only the SHA ...

Page 6

PRELIMINARY number of data bits sent by the master is not an integer multiple the data in the scratchpad is not valid due to a loss of power. A valid write to the scratchpad will clear ...

Page 7

PRELIMINARY 8 bytes, especially if the data loaded as a secret. If the master sends less than eight data bytes and does not read back the scratchpad for verification, parts of the new secret may be random ...

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PRELIMINARY Memory and SHA Functions Flow Chart Figure 7 Bus Master TX Memory TA1 (T7:T0), TA2 (T15:T8) N Bus Master RX “1”s N Master TX Reset ? Y Function Command 0Fh N Write Scratch- pad ? Y Bus Master TX ...

Page 9

PRELIMINARY Memory and SHA Functions Flow Chart (continued) Figure 7 From Figure Part DS2432 Increments Byte Counter Bus Master RX “1”s To Figure Part AAh N Read Scratch- Pad ? Y Bus Master RX ...

Page 10

PRELIMINARY Memory and SHA Functions Flow Chart (continued) Figure 7 From Figure 7 5Ah nd 2 Part Load First Secret ? Bus Master TX TA1 (T7:T0), TA2 (T15:T8) and E/S Byte Auth. Code Match ? Bus Master RX “1”s Master ...

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PRELIMINARY Memory and SHA Functions Flow Chart (continued) Figure 7 From Figure Part Compute Next Bus Master TX TA1 (T7:T0), TA2 (T15:T8) N Valid Data Address ? Bus Master RX “1”s Master TX Reset ? Y To ...

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PRELIMINARY Memory and SHA Functions Flow Chart (continued) Figure 7 From Figure 7 th 55h 4 Part Copy Scratch- pad ? Bus Master TX TA1 (T7:T0), TA2 (T15:T8), E/S Byte N Auth. Code Match ? Write- Protected ? Bus Master ...

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PRELIMINARY Memory and SHA Functions Flow Chart (continued) Figure 7 From Figure Part Bus Master RX “1”s N Master TX Reset ? Y To Figure Part A5h N Read Auth. Page ? Y Bus ...

Page 14

PRELIMINARY Memory and SHA Functions Flow Chart (continued) Figure 7 From Figure 7 th F0h 6 Part Read Memory ? Bus Master TX TA1 (T7:T0), TA2 (T15:T8) Address < 98h ? To Figure Part ...

Page 15

PRELIMINARY Compute Next Secret [33h] Some applications may require a higher level of security than can be achieved by a single, directly written secret. For additional security the DS2432 can compute a new secret based on the current secret, the ...

Page 16

PRELIMINARY not write-protected the SHA engine will start and within 2.0 ms compute a new secret that is then automatically copied to the secrets register. Replacing the secret takes maximum 10 ms. During this time and the computation of the ...

Page 17

PRELIMINARY Special attention is required when copying data to the register page. In order to prevent unintentional locking of a special function register or user byte it is recommended to first read the register page and then write it all ...

Page 18

PRELIMINARY that happens to reside in the scratchpad from a previous command as a challenge. The 160-bit MAC is transmitted in the same way as with the Copy Scratchpad command, Table 2, but the data flows from the DS2432 to ...

Page 19

PRELIMINARY Read Memory [F0h] The read memory command may be used to read all memory except for the secret. Attempting to read the secret will not reveal any data. After issuing the command, the master must provide the 2-byte target ...

Page 20

PRELIMINARY The variables are initialized as follows 67452301h B := EFCDAB89h C := 98BADCFEh D := 10325476h E := C3D2E1F0h The 160-bit MAC is the concatenation and E ...

Page 21

PRELIMINARY HARDWARE CONFIGURATION Figure 8 BUS MASTER RX TX Open Drain Port Pin TRANSACTION SEQUENCE The protocol for accessing the DS2432 via the 1-Wire port is as follows: Initialization ROM Function Command Memory or SHA Function Command Transaction/Data INITIALIZATION All ...

Page 22

PRELIMINARY ROM FUNCTIONS FLOW CHART Figure 9 From Memory Functions Flow Chart (Figure 9) Bus Master TX ROM Function Command 33h N Read ROM Match ROM Command ? Command ? DS2432 TX Family Code Master TX ...

Page 23

PRELIMINARY ROM FUNCTIONS FLOW CHART (continued) Figure Figure 9, 1 Part From Figure Part A5h Resume Command ? From Figure Part To Figure 9 st ...

Page 24

PRELIMINARY Search ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their 64-bit registration numbers. The search ROM command allows the bus master to use ...

Page 25

PRELIMINARY 1-WIRE SIGNALING The DS2432 requires strict protocols to ensure data integrity. The protocol consists of four types of sig- naling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read Data. Except ...

Page 26

PRELIMINARY Read/Write Time Slots The definitions of write and read time slots are illustrated in Figure 11. The master initiates all time slots by driving the data line low. The falling edge of the data line synchronizes the DS2432 to ...

Page 27

PRELIMINARY Read-data Time Slot V PULLUP V PULLUP MIN V IH MIN V IL MAX 0V Waveform Legend: RESISTOR MASTER DS2432 *The optimal sampling point for the master is as close as possible to the end time of the t ...

Page 28

PRELIMINARY With the Read Scratchpad command the CRC is generated by first clearing the CRC generator and then shifting in the command code, the Target Addresses TA1 and TA2, the E/S byte, and the scratchpad data, which may have been ...

Page 29

PRELIMINARY ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in ...

Page 30

PRELIMINARY AC ELECTRICAL CHARACTERISTICS OVERDRIVE SPEED PARAMETER Time Slot Write 1 Low Time Write 0 Low Time Read Low Time Read Data Valid Release Time Read Data Setup Recovery Time Reset High Time Reset Low Time Presence Detect High Presence ...

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