EPM7032TC44-10 Altera Corporation, EPM7032TC44-10 Datasheet
EPM7032TC44-10
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EPM7032TC44-10 Summary of contents
Page 1
... CO1 f (MHz) 151.5 151.5 CNT Altera Corporation DS-MAX7000-6.7 ® High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices – ISP circuitry compatible with IEEE Std. 1532 Includes 5 ...
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... Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations EPM7160S EPM7192S 3,200 3,750 160 192 10 12 104 124 6 7.5 3.4 4.1 2.5 3 3.9 4.7 149.3 125.0 Altera Corporation EPM7256S 5,000 256 16 164 7.5 3.9 3 4.7 128.2 ...
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... EPM7192E EPM7192S EPM7256E EPM7256S Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Additional design entry and simulation support provided by EDIF and netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from ...
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... Available only in EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices only. The MultiVolt I/O interface is not available in 44-pin packages. EPM7032 All EPM7064 MAX 7000E EPM7096 Devices Altera Corporation All MAX 7000S Devices ...
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... The devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times. Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Note (1) 68- ...
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... Quartus Programmable Logic Development System & Software Data Functional The MAX 7000 architecture includes the following elements: Description ■ ■ ■ ■ ■ 6 Logic array blocks Macrocells Expander product terms (shareable and parallel) Programmable interconnect array I/O control blocks MAX+PLUS II and the Sheet. Altera Corporation ...
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... Control I/O pins Block Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet The MAX 7000 architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin ...
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... PIA LAB Macrocells to16 6 to16 6 Output Enables LAB B 6 to16 6 to16 Macrocells I I/O Pins Control Block 6 LAB D 6 to16 6 to16 Macrocells I I/O Pins Control Block 6 Figures 1 Altera Corporation and 2. ...
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... Logic Array 36 Signals 16 Expander from PIA Product Ter Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Each LAB is fed by the following signals: ■ 36 signals from the PIA that are used for general logic inputs ■ Global controls that are used for secondary register functions ■ ...
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... Shareable expanders, which are inverted product terms that are fed back into the logic array Parallel expanders, which are product terms borrowed from adjacent macrocells Fast Input Programmable Select Register Register Bypass PRN D/T Q Clock/ Enable ENA CLRN Select VCC to PIA Altera Corporation from I/O pin to I/O Control Block ...
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... Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Each programmable register can be clocked in three different modes: ■ global clock signal. This mode achieves the fastest clock-to- output performance. ■ global clock signal and enabled by an active-high clock enable ...
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... OR logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB. 12 Shareable expanders can be shared by any or all macrocells in an LAB. 36 Signals 16 Shared from PIA Expanders ) is incurred when SEXP Figure 5 shows how shareable expanders Product-Term Select Matrix Altera Corporation Macrocell Product-Term Logic Macrocell Product-Term Logic ...
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... Figure 6. Parallel Expanders Unused product terms in a macrocell can be allocated to a neighboring macrocell. 36 Signals 16 Shared from PIA Expanders Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet ). For example macrocell requires 14 product terms, the PEXP . PEXP Figure 6 ...
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... The I/O control block of MAX 7000E and MAX 7000S devices has six global output enable signals that are driven by the true or complement of two output enable signals, a subset of the I/O pins subset of the I/O macrocells. 14 PIA Signals Figure 7 shows how To LAB . Figure 8 shows the I/O CC Altera Corporation ...
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... Figure 8. I/O Control Block of MAX 7000 Devices EPM7032, EPM7064 & EPM7096 Devices MAX 7000E & MAX 7000S Devices Note: (1) Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet VCC OE1 OE2 GND From Macrocell To PIA PIA To Other I/O Pins From Macrocell Fast Input to ...
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... Altera offers devices tested with a constant algorithm. Devices tested to the constant algorithm have an “F” suffix in the ordering code. The Jam used to program MAX 7000S devices with in-circuit testers, PCs, or embedded processor Standard Test and Programming Language (STAPL) can be , the output is CC Altera Corporation ...
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... Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Enter ISP. The enter ISP stage ensures that the I/O pins transition smoothly from user mode to ISP mode. The enter ISP stage requires 1 ms. Check ID. Before any program or verify process, the silicon ID is checked ...
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... Sum of the fixed times to erase, program, and PPULSE verify the EEPROM cells Cycle = Number of TCK cycles to program a device PTCK f = TCK frequency TCK Cycle VTCK = t + -------------------------------- VPULSE f TCK = Verify time VER t = Sum of the fixed times to verify the EEPROM cells VPULSE Cycle = Number of TCK cycles to verify a device VTCK Altera Corporation ...
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... Table 8. MAX 7000S Stand-Alone Verification Times for Different Test Clock Frequencies Device 10 MHz 5 MHz EPM7032S 0.05 0.07 EPM7064S 0.06 0.09 EPM7128S 0.08 0.14 EPM7160S 0.09 0.16 EPM7192S 0.11 0.18 EPM7256S 0.13 0.24 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Values TCK Programming t (s) Cycle PPULSE PTCK 4.02 342,000 4.50 504,000 5.11 832,000 5.35 1,001,000 5.71 1,192,000 6.43 1,603,000 ...
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... SEXP ACL CPPW level, input voltage thresholds are at TTL levels, and CCINT is connected to a 3.3-V supply, the output high is CCIO levels lower than 4.75 V incur a nominally greater CCIO instead of t OD2 TM option turned on) ) for the t LPA LAD parameters. . OD1 Altera Corporation , LAC IC ...
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... Programming with External Hardware f f Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet By using an external 5.0-V pull-up resistor, output pins on MAX 7000S devices can be set to meet 5.0-V CMOS input voltages. When V is 3.3 V, setting the open drain option will turn off the output ...
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... IDCODE to be serially shifted out of TDO. These instructions are used when programming MAX 7000S devices via the JTAG ports with the MasterBlaster, ByteBlasterMV, BitBlaster download cable, or using a Jam File (.jam), Jam Byte-Code file (.jbc), or Serial Vector Format file (.svf) via an embedded processor or test equipment. Altera Corporation ...
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... Table 11. 32-Bit MAX 7000 Device IDCODE EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S Notes: (1) (2) Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet 11 show the boundary-scan register length and device IDCODE Table 10. MAX 7000S Boundary-Scan Register Length Device EPM7032S EPM7064S EPM7128S EPM7160S ...
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... JSZX t Update register valid output to high impedance JSXZ Application Note 39 (IEEE 1149.1 (JTAG JPH JPSU t JPCO t JSH t t JSCO JSXZ Min 100 Devices). Altera Corporation t JPXZ Max Unit ...
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... For detailed information and carrier dimensions, refer to the & Development Socket Data 1 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure Power supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be avoided for accurate measurement ...
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... For industrial use Min Max Unit –2.0 7.0 V –2.0 7.0 V – –65 150 ° C –65 135 ° C 150 ° C 135 ° C Min Max Unit 4.75 5.25 V (4.50) (5.50) 4.75 5.25 V (4.50) (5.50) 3.00 3.60 V (3.00) (3.60) 4.75 5.25 V –0.5 ( 0.5 V CCINT CCIO 0 70 ° C –40 85 ° ° C –40 105 ° Altera Corporation ...
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... IN C I/O pin capacitance I/O Table 18. MAX 7000 5.0-V Device Capacitance: MAX 7000S Devices Symbol Parameter C Dedicated input pin capacitance IN C I/O pin capacitance I/O Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Note (9) Conditions = – 4.75 V (10) OH CCIO = – 3.00 V (10) OH ...
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... POR is 4.5 V. The CCINT Table 14 on page parameter refers OH parameter refers to OL pin has a maximum capacitance of 20 pF. 150 I OL 120 3 CIO Room Temperature 3 Output Voltage (V) O Figure 12. MAX 7000 Altera Corporation 26. 5 ...
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... External timing parameters, which represent pin-to-pin timing delays, can be calculated as the sum of internal parameters. relationship of internal and external delay parameters. f For more infomration, see Timing). Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Internal Output Enable Delay t (1) IOE ...
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... PIA Clock into Logic Array Clock at Register Data from Logic Array t to Logic Array to Pin t PIA t SEXP LAC LAD t PEXP t COMB ACL PIA CLR t OD Altera Corporation PIA PRE t OD ...
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... Minimum array clock period ACNT f Maximum internal array clock ACNT frequency f Maximum clock frequency MAX Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Tables 19 through 26 show the MAX 7000 and MAX 7000E AC operating conditions. Conditions -6 Speed Grade Min ...
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... Min ( ( ( 3.0 1.5 (2) 2.5 (2) 0.5 (8) Note (1) Speed Grade -7 Max Min Max 0.4 0.5 0.4 0.5 0.8 1.0 3.5 4.0 0.8 0.8 2.0 3.0 2.0 3.0 2.0 2.0 2.0 2.5 2.5 7.0 7.0 4.0 4.0 4.5 4.5 9.0 9.0 4.0 4.0 3.0 2.0 3.0 0.5 0.8 1.0 0.8 1.0 2.5 3.0 2.0 3.0 0.8 1.0 2.0 2.0 2.0 2.0 0.8 1.0 10.0 10.0 Altera Corporation Unit ...
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... Maximum internal global clock CNT frequency t Minimum array clock period ACNT f Maximum internal array clock ACNT frequency Maximum clock frequency f MAX Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Note (1) Conditions MAX 7000E (-10P) MAX 7000 (-10) Min 7.0 0.0 (2) 3.0 (2) ...
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... MAX 7000E (-10P) MAX 7000 (-10) Min ( 2.0 3.0 (2) 3.0 (2) 0.5 (8) Speed Grade Unit MAX 7000E (-10) Max Min Max 0.5 1.0 ns 0.5 1.0 ns 1.0 1.0 ns 5.0 5.0 ns 0.8 0.8 ns 5.0 5.0 ns 5.0 5.0 ns 2.0 2.0 ns 1.5 2.0 ns 2.0 2.5 ns 5.5 6.0 ns 5.0 5.0 ns 5.5 5.5 ns 9.0 9.0 ns 5.0 5.0 ns 3.0 ns 3.0 ns 3.0 ns 0.5 ns 2.0 1.0 ns 2.0 1.0 ns 5.0 5.0 ns 5.0 5.0 ns 1.0 1.0 ns 3.0 3.0 ns 3.0 3.0 ns 1.0 1.0 ns 11.0 11.0 ns Altera Corporation ...
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... Maximum internal global clock CNT frequency t Minimum array clock period ACNT f Maximum internal array clock ACNT frequency Maximum clock frequency f MAX Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Note (1) Conditions MAX 7000E (-12P) Min 7.0 0.0 (2) 3.0 (2) ...
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... ( ( ( ( 1.0 6.0 (2) 4.0 (2) 0.0 (8) Speed Grade Unit MAX 7000 (-12) MAX 7000E (-12) Max Min Max 1.0 2.0 ns 1.0 2.0 ns 1.0 1.0 ns 7.0 7.0 ns 1.0 1.0 ns 7.0 5.0 ns 5.0 5.0 ns 2.0 2.0 ns 1.0 3.0 ns 2.0 4.0 ns 5.0 7.0 ns 6.0 6.0 ns 7.0 7.0 ns 10.0 10.0 ns 6.0 6.0 ns 4.0 ns 4.0 ns 2.0 ns 2.0 ns 2.0 1.0 ns 2.0 1.0 ns 5.0 5.0 ns 7.0 5.0 ns 2.0 0.0 ns 4.0 3.0 ns 4.0 3.0 ns 1.0 1.0 ns 12.0 12.0 ns Altera Corporation ...
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... Minimum global clock period CNT f Maximum internal global clock CNT frequency t Minimum array clock period ACNT f Maximum internal array clock ACNT frequency f Maximum clock frequency MAX Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Conditions -15 Min Max 15 15.0 11.0 0.0 (2) 3.0 (2) 0 ...
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... 6 (7) 7 (2) 10 6.0 4.0 4.0 (2) 2.0 (2) 2.0 1.0 1.0 6.0 6.0 1.0 4.0 4.0 2.0 (8) 13.0 Note (1) Speed Grade -15T -20 Min Max Min Max 2.0 3.0 2.0 3.0 – 4.0 10.0 9.0 1.0 2.0 6.0 8.0 6.0 8.0 – 4.0 4.0 5.0 – 6.0 – 9.0 6.0 10.0 – 11.0 – 14.0 6.0 10.0 4.0 4.0 4.0 5.0 – 4.0 – 3.0 1.0 1.0 1.0 1.0 6.0 8.0 6.0 8.0 1.0 3.0 4.0 4.0 4.0 4.0 2.0 3.0 15.0 15.0 Altera Corporation Unit ...
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... ODH clock t Minimum global clock period CNT f Maximum internal global clock CNT frequency t Minimum array clock period ACNT Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet = 3.3 V ± 10% for commercial and industrial use LAD LAC IC EN SEXP Tables 27 ...
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... 4 ( 4.0 0.8 1.0 1.7 2.0 1.9 1.8 0.6 0.7 1.2 0.9 2.7 2.6 1.6 2.0 2.0 Note (1) Speed Grade -6 -7 -10 116.3 100.0 166.7 125.0 Speed Grade -6 -7 -10 Max Min Max Min Max 0.2 0.3 0.2 0.3 2.1 2.5 3.8 4.6 1.1 1.4 3.3 4.0 3.3 4.0 0.8 1.0 0.3 0.4 0.8 0.9 5.3 5.4 4.0 4.0 4.5 4.5 9.0 9.0 4.0 4.0 1.3 2.0 2.5 3.0 1.7 3.0 0.8 0.5 1.6 1.9 1.1 1.4 3.4 4.2 3.3 4.0 1.4 1.7 2.4 3.0 2.4 3.0 Altera Corporation Unit MHz MHz Unit 0.5 ns 0.5 ns 1.0 ns 5.0 ns 0.8 ns 5.0 ns 5.0 ns 2.0 ns 1.5 ns 2.0 ns 5.5 ns 5.0 ns 5.5 ns 9 2.0 ns 2.0 ns 5.0 ns 5.0 ns 1.0 ns 3.0 ns 3.0 ns ...
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... CO1 t Global clock high time CH t Global clock low time CL t Array clock setup time ASU t Array clock hold time AH Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Note (1) Conditions -5 Min Max (7) 1.1 (8) 12.0 = 3.3 V ± 10% for commercial and industrial use ...
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... ( ( 4.0 0.8 1.0 1.7 2.0 Note (1) Speed Grade -6 -7 -10 6.7 7.5 10.0 3.0 4.0 3.0 4.0 3.0 4.0 1.0 1.0 7.1 8.0 10.0 125.0 100.0 7.1 8.0 10.0 125.0 100.0 166.7 125.0 Note (1) Speed Grade -6 -7 -10 0.2 0.5 0.2 0.5 2.6 1.0 3.8 4.0 1.1 0.8 3.2 3.0 3.2 3.0 0.8 2.0 0.3 2.0 0.8 2.5 5.3 7.0 4.0 4.0 4.5 4.5 9.0 9.0 4.0 4.0 3.0 2.0 2.0 3.0 Altera Corporation Unit MHz ns MHz MHz Unit 0.5 ns 0.5 ns 1.0 ns 5.0 ns 0.8 ns 5.0 ns 5.0 ns 2.0 ns 1.5 ns 2.0 ns 5.5 ns 5.0 ns 5.5 ns 9 ...
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... PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0 the PIA timing value. (8) The t parameter must be added to the t LPA running in the low-power mode. Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Conditions -5 Min Max Min Max Min Max Min Max 1.9 0.6 1 ...
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... Min Max Min Max Min Max Min Max 6 6.0 3.4 6.0 0.0 0.0 2.5 3.0 0.0 0 4.0 3.0 3.0 3.0 3.0 0.9 3.0 1.8 2 6.5 3.0 3.0 3.0 3.0 (2) 3.0 3 (3) 1.0 1.0 6.8 (4) 147.1 125.0 6.8 (4) 147.1 125.0 (5) 166.7 166.7 Speed Grade -7 -10 -15 7.5 10.0 15.0 7.5 10.0 15.0 7.0 11.0 0.0 0.0 3.0 3.0 0.5 0.0 4.5 5.0 8.0 4.0 5.0 4.0 5.0 2.0 4.0 5.0 4.0 7.5 10.0 15.0 4.0 6.0 4.0 6.0 4.0 6.0 1.0 1.0 8.0 10.0 13.0 100.0 76.9 8.0 10.0 13.0 100.0 76.9 125.0 100.0 Altera Corporation Unit MHz ns MHz MHz ...
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... EN t Global control delay GLOB t Register preset time PRE t Register clear time CLR t PIA delay PIA t Low-power adder LPA Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Note (1) Conditions -6 Min Max Min Max Min Max Min Max 0.2 0.2 2.6 3.7 1.1 3.0 3 (6) 0 ...
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... (3) 1.0 6.7 (4) 149.3 Table 14. See Figure 13 LPA parameter into the signal LAD , t , and t parameters for macrocells ACL CPPW Note (1) Speed Grade -7 -10 -15 7.5 10.0 7.5 10.0 4.2 7.0 11.0 0.0 0.0 0.0 3.0 3.0 3.0 0.0 0.5 0.0 4.8 5 3.0 4.0 5.0 3.0 4.0 5.0 1.1 2.0 4.0 2.1 3.0 4.0 7.9 10.0 3.0 4.0 6.0 3.0 4.0 6.0 3.0 4.0 6.0 1.0 1.0 1.0 8.2 10.0 122.0 100.0 76.9 Altera Corporation for more parameter Unit 15 13.0 ns MHz ...
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... COMB t Array clock delay IC t Register enable time EN t Global control delay GLOB t Register preset time PRE Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Conditions -6 Min Max Min Max Min Max Min Max 6.7 (4) 149.3 122.0 (5) 166.7 166.7 Conditions ...
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... Note (1) Speed Grade -7 -10 -15 3.0 3.0 2.0 1.0 10.0 11.0 Table 14. See Figure 13 parameter into the signal LAD , t , and t parameters for macrocells ACL CPPW Note (1) Speed Grade -10 -15 Max Min Max Min 7.5 10.0 7.5 10.0 7.0 11.0 0.0 0.0 3.0 3.0 0.5 0.0 4.7 5.0 4.0 5.0 4.0 5.0 2.0 4.0 Altera Corporation Unit 4.0 ns 2.0 ns 13.0 ns for more parameter LPA Unit Max 15 ...
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... OD3 t Output buffer enable delay ZX1 t Output buffer enable delay ZX2 t Output buffer enable delay ZX3 t Output buffer disable delay XZ t Register setup time SU Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Conditions -7 Min Max 1 7.8 3.0 3.0 (2) 3 (3) 1.0 8 ...
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... LAD LAC IC EN SEXP Note (1) Speed Grade -7 -10 -15 Max Min Max Min 3.0 4.0 3.0 2.0 0.5 1.0 1.4 2.0 1.2 2.0 3.2 5.0 3.1 5.0 2.5 1.0 2.7 3.0 2.7 3.0 2.4 1.0 10.0 11.0 Table 14. See Figure 13 parameter into the signal LAD , t , and t parameters for macrocells ACL CPPW Altera Corporation Unit Max 1.0 ns 1.0 ns 6.0 ns 6.0 ns 1.0 ns 4.0 ns 4.0 ns 2.0 ns 13.0 ns for more parameter LPA ...
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... Maximum internal global clock CNT frequency t Minimum array clock period ACNT f Maximum internal array clock ACNT frequency f Maximum clock frequency MAX Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet and 38 show the EPM7256S AC operating conditions. Note (1) Conditions -7 Min Max 7 ...
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... LPA 52 Note (1) Conditions -7 Min Max ( ( 1.1 1.6 2.4 0.6 (7) (8) 10.0 Speed Grade -10 -15 Min Max Min Max 0.3 0.5 2.0 0.3 0.5 2.0 3.4 1.0 2.0 3.9 5.0 8.0 1.1 0.8 1.0 2.6 5.0 6.0 2.6 5.0 6.0 0.8 2.0 3.0 0.5 1.5 4.0 1.0 2.0 5.0 5.5 5.5 8.0 4.0 5.0 6.0 4.5 5.5 7.0 9.0 9.0 10.0 4.0 5.0 6.0 2.0 4.0 3.0 4.0 3.0 2.0 0.5 1.0 1.1 2.0 1.0 1.1 2.0 1.0 2.9 5.0 6.0 2.6 5.0 6.0 2.8 1.0 1.0 2.7 3.0 4.0 2.7 3.0 4.0 3.0 1.0 2.0 11.0 13.0 Altera Corporation Unit ...
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... I CCINT A × MC The parameters in this equation are shown below MAX tog Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet = 3.3 V ± 10% for commercial and industrial use LAD LAC IC EN SEXP × ...
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... Equation Constants CC Device A EPM7032 1.87 EPM7064 1.63 EPM7096 1.63 EPM7128E 1.17 EPM7160E 1.17 EPM7192E 1.17 EPM7256E 1.17 EPM7032S 0.93 EPM7064S 0.93 EPM7128S 0.93 EPM7160S 0.93 EPM7192S 0.93 EPM7256S 0.93 estimate based on typical conditions 0.52 0.144 0.74 0.144 0.74 0.144 0.54 0.096 0.54 0.096 0.54 0.096 0.54 0.096 0.40 0.040 0.40 0.040 0.40 0.040 0.40 0.040 0.40 0.040 0.40 0.040 values should be verified during Altera Corporation ...
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... Typical Active (mA) 55.5 MHz 1 50 Low Power Frequency (MHz) Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 14 shows typical supply current versus frequency for MAX 7000 devices. EPM7064 151.5 MHz High Speed Typical I Active (mA) 100 ...
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... Room Temperature 400 100 MHz 300 High Speed 200 47.6 MHz 100 Low Power 0 50 100 150 Frequency (MHz) 750 Room Temperature 600 90.9 MHz 450 High Speed 300 43.4 MHz 150 Low Power 100 Frequency (MHz) Altera Corporation 200 125 ...
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... CC 160 Active (mA 56.2 MHz 80 Low Power 100 Frequency (MHz) Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet shows typical supply current versus frequency for MAX 7000S EPM7064S 142.9 MHz Typical I CC High Speed Active (mA) 150 200 EPM7160S 147.1 MHz ...
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... See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information. Pin-Outs 58 EPM7256S 125.0 MHz High Speed Typical I CC Active (mA) 55.6 MHz 75 100 125 Room Temperature 40 0 High Speed 30 0 200 56.2 MHz Low Power 100 100 Frequency (MHz) Altera Corporation 128.2 MHz 125 ...
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... The pin functions shown in parenthesis are only available in MAX 7000E and MAX 7000S devices. (2) JTAG ports are available in MAX 7000S devices only. Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet through 22 show the package pin-out diagrams for MAX 7000 ...
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... PLCC The pin functions shown in parenthesis are only available in MAX 7000E and MAX 7000S devices. JTAG ports are available in MAX 7000S devices only. 60 I/O 59 I/O 58 GND I/O/(TDO) ( I/O 55 I/O 54 I/O 53 VCCIO 52 I/O 51 I/O EPM7064 50 I/O/(TCK) (2) 49 I/O EPM7096 48 GND 47 I/O 46 I/O 45 I/O 44 I/O Altera Corporation ...
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... Pins 6, 39, 46, and 79 are no-connect (N.C.) pins on EPM7096, EPM7160E, and EPM7160S devices. (2) The pin functions shown in parenthesis are only available in MAX 7000E and MAX 7000S devices. (3) JTAG ports are available in MAX 7000S devices only. Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet I/O 12 VCCIO ...
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... View 160-Pin PGA 62 Pin 81 Pin 1 Pin 51 Pin 26 Pin 1 Pin 41 Pin 76 EPM7064S EPM7128S EPM7160S Pin 51 100-Pin TQFP EPM7128E EPM7128S EPM7160E EPM7160S EPM7192E EPM7192S EPM7256E 160-Pin PQFP Altera Corporation Pin 121 Pin 81 ...
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... Figure 21. 192-Pin Package Pin-Out Diagram Package outline not drawn to scale. Figure 22. 208-Pin Package Pin-Out Diagram Package outline not drawn to scale. Pin 1 Pin 53 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet EPM7256E K Bottom J View ...
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... ISP & ICR via an Embedded Processor. Added Tables 6 through 8. Added “Programming Sequence” section on page 17 “Programming Times” section on page 18. Updated text on page 16. Added Note (5) on page 28. Updated the “Open-Drain Output Option (MAX 7000S Devices Only)” section on page 20. and Altera Corporation ...
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... Notes: Altera Corporation 65 ...
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... MAX 7000 Programmable Logic Device Family Data Sheet Copyright © 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U ...