HIP0045 Intersil Corporation, HIP0045 Datasheet
HIP0045
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HIP0045 Summary of contents
Page 1
... Power Low Side Driver. The serial peripheral interface (SPI) utilized by the HIP0045 is a serial synchronous bus compatible with Intersil CDP68HC05, or equivalent, microcomputers. As shown in the Block Diagram for the HIP0045, each of the open drain MOS Output Drivers have individual protection for over- voltage and over-current. Each output channel has separate output latch control with fault unlatch and diagnostic or status feedback ...
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... Input to Output Control Tables TABLE 1. OUTPUT 0 SPI BIT 0 IN0 TABLE 2. OUTPUT 1 SPI BIT 1 IN1 4-2 HIP0045 Q0, 1 ON/OFF OVERLOAD LATCH LATCH FAULT LATCH S Q DIAG STATUS/ FAULT RESET Q0-7 8-BIT OVERLOAD LATCH OUTPUT LATCH ON/OFF S ...
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... Turn-Off Voltage Slew-Rate, OUT0 - 7 Turn-Off Voltage Slew-Rate, OUT0 - 7 FAULT PARAMETERS Reverse Current Drive, OUT0 - 7 Reverse Voltage Drop, OUT0 - 7 I during Reverse Current Drive CC 4-3 HIP0045 Thermal Information Thermal Resistance (Typical, Note PSOP Package . . . . . . . . . . . . . . . . . . SC LIM Maximum Junction Temperature, T Maximum Storage Temperature Range, T Maximum Lead Temperature (Soldering 10s .265 ...
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... MOSI Data Valid) Data Hold Time (MOSI Data Hold Time SCK Change from High to Low) Enable Time from CE = Low to Data at MISO Disable Time (Time for CE Low to High to Output Data Float) 4-4 HIP0045 4.5V to 5.5V - 125 C, Unless Otherwise Specified (Continued) ...
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... LAST BIT TRANSMITTED HIGH Z MISO (OUTPUT xxxxxxxx xxxxxxxx MOSI xxxxxxxx (INPUT) xxxxxxxx DRIVER OLD OUTPUT 4-5 HIP0045 (MOSI, MISO Load Capacitor = 100pF, See Figure 1) SYMBOL TEST CONDITION 0. SCK_LEAD t SCK_LAG MSB INTERNAL STROBE FOR DATA CAPTURE FIGURE 1A ...
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... The CPHA bit in general selects the clock edge which captures data and allows it to change states. For the HIP0045, the CPOL bit must be set to a logic zero and the CPHA bit to a logic one. Configured in this manner, MISO (output) data will appear ...
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... Serial output and input data are simultaneously transferred to and from the SPI bus. The serial input data is parallel latched into the 8-Bit Output Latch of the HIP0045 at the end of a data transfer. Diagnostic data, Diag0-7 is transferred to the shift register when CE goes low at the beginning of a data transfer cycle ...
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... Open Load. REF Refer to the Electrical Specification for the V 4-8 HIP0045 Special Conditions for Channel 0, 1 Referring to the Detailed Block Diagram, Channel’ are configured to externally provide control of the ON/OFF state. The inputs, IN0 and IN1, are ORed with the SPI ON/OFF control bit. In this confi ...
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... Power Small Outline Plastic Package (PSOP PLACES -B- E 3.10 REF. 0.15 REF. A3 HEAT SLUG DETAIL "A" SECTION "B-B" 4-9 HIP0045 SEATING PLANE - - 0.10 C SEATING PLANE SEE DETAIL "A" GAUGE L1 PLANE ...
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... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 4-10 HIP0045 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd ...