K4J55323QF-GC14 Samsung, K4J55323QF-GC14 Datasheet
K4J55323QF-GC14
Available stocks
Related parts for K4J55323QF-GC14
K4J55323QF-GC14 Summary of contents
Page 1
... K4J55323QF-GC 256Mbit GDDR3 SDRAM with Uni-directional Data Strobe and DLL Samsung Electronics reserves the right to change products or specification without notice 32Bit x 4 Banks Graphic Double Data Rate 3 Synchronous DRAM (144 - Ball FBGA) Revision 1.7 January 2005 - 1 - 256M GDDR3 SDRAM Rev 1.7 (Jan. 2005) ...
Page 2
... Changed VDD/VDDQ from 1.9V+ 0.1V to 2.0V+ 0.1V in all frequencies changes : Refer to the DC characteristics of page 45. Revision 1.1 (January 29 , 2004) - Typo corrected Revision 1.0 (January 15 , 2004) - Changed VDD/VDDQ of K4J55323QF-GC12 from 2.1V+ 0.1V to 1.9V+ 0.1V - Changed VDD/VDDQ of K4J55323QF-GC14/16/20 from 1.8V+ 0.1V to 1.9V+ 0.1V - Changed tCK(max) from 3.0ns to 3.3ns - DC spec finalized. Typo corrected 256M GDDR3 SDRAM - 2 - Rev 1.7 (Jan. 2005) ...
Page 3
... Revision 0.5 (January 7 , 2004) - Added "Dummy MRS" command during the power-up sequence. Typo corrected Revision 0.4 (December 10 , 2003) - Typo corrected - Added K4J55323QF-GC12 (800MHz) in the spec - Key AC parameter changes : Refer to the AC spec table on page 46,47 . Added tDAL in the AC characteristics table, . Added AC parameter of -GC12 in the AC characteristics table, ...
Page 4
... Programmable Write latency : and 6 (clock) • Single ended READ strobe (RDQS) per byte • Single ended WRITE strobe (WDQS) per byte ORDERING INFORMATION Part NO. K4J55323QF-GC14 K4J55323QF-GC15 K4J55323QF-GC16 K4J55323QF-GC20* *K4J55323QF-GL20/VL20 : VDD & VDDQ = 1.8V+0.1V(1.7V ~ 1.9V) *K4J55323QF-V is the Lead Free package part number ...
Page 5
... K4J55323QF-GC PIN CONFIGURATION Normal Package (Top View WDQS0 RDQS0 VSSQ C DQ4 DM0 VDDQ D DQ6 DQ5 VSSQ E DQ7 RFU3 VDD F DQ17 DQ16 VDDQ G DQ19 DQ18 VDDQ H WDQS2 RDQS2 VDDQ J DQ20 DM2 VDDQ K DQ21 DQ22 VDDQ L DQ23 A3 VDD VREF A2 A10 M A0 ...
Page 6
... K4J55323QF-GC INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the positive CK, CK Input edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buff- ers and output drivers ...
Page 7
... K4J55323QF-GC BLOCK DIAGRAM (2Mbit x 32I Bank) Bank Select iCK ADDR LCKE LRAS LCBR iCK CKE * iCK : internal clock WDQS Input Buffer Input Buffer Data Input Register Serial to parallel Column Decoder Latency & Burst Length ...
Page 8
... K4J55323QF-GC FUNCTIONAL DESCRIPTION Simplified State Diagram Power Applied Power On Precharge PREALL MRS EMRS Write A PREALL = Precharge All Banks MRS = Mode Register Set EMRS = Extended Mode Register Set REFS = Enter Self Refresh REFSX = Exit Self Refresh REFA = Auto Refresh REFS REFSX MRS ...
Page 9
... K4J55323QF-GC INITIALIZATION GDDR3 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. 1. Apply power and keep CKE/RESET at low state ( All other inputs may be undefined) - Apply VDD and VDDQ simultaneously - Apply VDDQ before Vref. ( Inputs are not recognized as valid until after V 2 ...
Page 10
... K4J55323QF-GC MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of GDDR3 SDRAM. It programs CAS latency, addressing mode, test mode and various vendor specific options to make GDDR3 SDRAM useful for variety of dif- ferent applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation ...
Page 11
... K4J55323QF-GC PROGRAMMABLE IMPEDANCE OUTPUT BUFFER AND ACTIVE TERMINATOR The GDDR3 SDRAM is equipped with programmable impedance output buffers and Active Terminators. This allows a user to match the driver impedance to the system. To adjust the impedance, an external precision resistor(RQ) is connected between the ZQ pin and Vss. The value of the resistor must be six times the desired output impedance. ...
Page 12
... K4J55323QF-GC CAS LATENCY (READ LATENCY) The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 5~9 clocks READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n+m ...
Page 13
... K4J55323QF-GC WRITE LATENCY The Write latency (WL) is the delay, in clock cycles, between the registration of a WRITE command and the availability of the first bit of input data. The latency can be set from clocks depending in the operating frequency and desired current draw. When the write latencies are set clocks, the input receivers never turn off when the WRITE command is registered ...
Page 14
... K4J55323QF-GC TEST MODE The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7 set to zero, and bits A0-A6 and A8- A11 set to the desired values. Test mode is entered by issuing a MODE REGISTER SET command with bit A7 set to one, and bits A0- A6 and A8-A11 set to the desired values. Test mode functions are specific to each Dram Manufacturer and its exact functions are hidden from the user ...
Page 15
... K4J55323QF-GC EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data output driver strength and on-die termination options. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The GDDR3 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode regis- ter) ...
Page 16
... K4J55323QF-GC DLL ENABLE/DISABLE The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after disabling the DLL for debugging or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 20K clock cycles must occur before a READ command can be issued ...
Page 17
... K4J55323QF-GC LOW POWER MODE Low power mode can be enabled by A11="H" during the EMRS command and in this case, Precharge Power Down command activates LP mode1 and Self Refresh command activates LP mode2. In case that A11 set to "L" during the EMRS, Low Power mode is disabled and Precharge Power Down command and Self Refresh command will do normal operation ...
Page 18
... K4J55323QF-GC COMMANDS Below Truth table-COMMANDs provides a quick reference of available commands. This is followed by a verbal descrip- tion of each command. Two additional Truth Tables appear following the operation section : these tables provide current state/next state information. TRUTH TABLE - COMMANDs Name (Function) DESELECT (NOP) ...
Page 19
... K4J55323QF-GC DESELECT The DESELECT function (/CS high) prevents new commands from being executed by the DDR(x32). The GDDR3(x32) SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to instruct selected GDDR3(x32) to perform a NOP (/CS LOW). This pre- vents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected ...
Page 20
... K4J55323QF-GC AUTO PRECHARGE Auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. This is accomplished by using A8 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is auto- matically performed upon completion of the READ or WRITE burst ...
Page 21
... K4J55323QF-GC ON-DIE TERMINATION Bus snooping for READ commands other than /CS is used to control the on-die termination. The GDDR3 SDRAM will dis- able the on-die termination when a READ command is detected, regardless of the state of /CS. The on-die termination is disabled x clocks after the READ command where x equals CL-1 and stay off for a duration of BL below figure, Data Termination Disable Timing ...
Page 22
... K4J55323QF-GC OPERATIONS BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a banks within the GDDR3 SDRAM, a row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. After a row is opened with an ACTIVE command, a READ or WRITE command may be issued ...
Page 23
... K4J55323QF-GC READs READ bursts are initiated with a READ command, as below figure. The start- ing column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto pre- charge is enabled, the row being accessed is prechrged at the completion of the burst after t has been met ...
Page 24
... K4J55323QF-GC Data Output Timing ( CK# CK 1.6 RDQS DQ(Last data valid) DQ(First data no longer valid) 5 All DQs and RDQS, collectively Data Output Timing ( CK# CK 1.6 RDQS 5 All DQs and RDQS, collectively 1.6 RDQS 5 All DQs and RDQS, collectively Note : 1. t represents the skew between the 8 DQ lines and the respective RDQS pin. ...
Page 25
... K4J55323QF-GC READ Burst T0 /CK CK COMMAND READ Bank a, ADDRESS Col RDQS DQ T0 /CK CK COMMAND READ ADDRESS Bank a, Col RDQS n=data-out from column n. NOTE : 2. Burst length = 4 3. Three subsequent elements of data-out appear in the programmed order following Shown with nominal t 5 ...
Page 26
... K4J55323QF-GC Consecutive READ Bursts T0 /CK CK COMMAND READ Bank a, ADDRESS Col n RDQS DQ NOTE : ( data-out from column n (or column b). 2. Burst length = 4 3. Three subsequent elements of data-out appear in the programmed order following Three subsequent elements of data-out appear in the programmed order following DQ b. ...
Page 27
... K4J55323QF-GC Nonconsecutive READ Bursts T0 /CK CK COMMAND READ Bank a, ADDRESS Col RDQS ( data-out from column n (or column b). NOTE : 2. Burst length = 4 3. Three subsequent elements of data-out appear in the programmed order following Three subpsequent elements of data-out appear in the programmed order following DQ b. ...
Page 28
... K4J55323QF-GC Random READ Accesses T0 /CK CK COMMAND READ Bank a, ADDRESS Col n RDQS DQ T0 /CK CK COMMAND READ Bank a, ADDRESS Col n RDQS ( data-out from column n (or column x or column x or column b or column g). NOTE : 2. Burst length = 4 3. n’ b’ or g’ indicates the next data-out following respectively 4 ...
Page 29
... K4J55323QF-GC READ to WRITE READ to WRITE T0 /CK CK COMMAND READ Bank ADDRESS Col n RDQS WDQS Termination data-out from column n. NOTE : data-in from column b. 3. Burst length = 4 4. One subsequent element of data-out appears in the programmed order following Data-in elements are applied following the programmed order. ...
Page 30
... K4J55323QF-GC READ to PRECHARGE T0 /CK CK COMMAND READ Bank a, ADDRESS Col n RDQS DQ NOTE ( data-out from column n (or column b Burst length = 4 3. Three subsequent elements of data-out appear in the programmed order following Read to precharge equals two clocks, which enables two data pairs of data-out. ...
Page 31
... K4J55323QF-GC WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is pre- charged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled ...
Page 32
... K4J55323QF-GC WRITE Burst T0 /CK CK COMMAND WRITE Bank a, ADDRESS Col b t (NOM) t DQSS DQSS WDQS (MIN) t DQSS DQSS WDQS (MAX) t DQSS DQSS WDQS DQ DM NOTE data-in for column Three subsequent elements of data-in are applied in the programmed order following DI b. ...
Page 33
... K4J55323QF-GC Consecutive WRITE to WRITE T0 CK# CK COMMAND WRITE NOP Bank ADDRESS Col b t (NOM) DQSS WDQS etc. = data-in for column b, etc. NOTE : 2. Three subsequent elements of data-in are applied in the programmed order following Three subsequent elements of data-in are applied in the programmed order following DI n. ...
Page 34
... K4J55323QF-GC Nonconsecutive WRITE to WRITE T0 /CK CK COMMAND WRITE NOP Bank, ADDRESS Col b t (NOM) DQSS WDQS etc. = data-in for column b, etc. NOTE : 2. Three subsequent elements of data-in are applied in the programmed order following Three subsequent elements of data-in are applied in the programmed order following DI n. ...
Page 35
... K4J55323QF-GC Random WRITE Cycles T0 /CK CK COMMAND WRITE NOP Bank ADDRESS Col b t (NOM) DQSS WDQS etc. = data-in for column b, etc. NOTE : 2. b: etc. = the next data - in following DI b. etc., according to the programmed burst order. 3. Programmed burst length = 4 cases shown. ...
Page 36
... K4J55323QF-GC WRITE to READ T0 T1 /CK CK COMMAND WRITE NOP Bank ADDRESS Col (NOM) DQSS DQSS WDQS DQ DM RDQS t t (MIN) DQSS DQSS WDQS DQ DM RDQS t t (MAX) DQSS DQSS WDQS DQ DM RDQS data-in for column b. NOTE : 2. Three subsequent elements of data-in the programmed order following DI b. ...
Page 37
... K4J55323QF-GC WRITE to PRECHARGE T0 T1 /CK CK COMMAND WRITE NOP Bank ADDRESS Col (NOM) DQSS DQSS WDQS (MIN) DQSS DQSS WDQS (MAX) DQSS DQSS WDQS DQ DM NOTE data-in for column Three subsequent elements of data-in the programmed order following DI b. ...
Page 38
... K4J55323QF-GC PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (t CHARGE command is issued. Input A8 determines whether one or all banks are to be precharged, and in the case where only one bank precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as " ...
Page 39
... K4J55323QF-GC TRUTH TABLE - Clock Enable (CKE) CKEn-1 CKEn CURRENT STATE Power-Down L L Self Refresh Power-Down L H Self Refresh All Banks Idle H L Bank(s) Active All Banks Idle NOTES : 1. CKEn is the logic state of CKE at clock edge n; CKEn-1was the state of CKE at the previous clock edge. ...
Page 40
... K4J55323QF-GC TRUTH TABLE - CURRENT STATE BANK n CURRENT STATE /CS /RAS /CAS H X Any Idle Row Active Read (Auto-Precharge L H Disable Write (Auto-Precharge L H Disabled NOTES : 1. This table applies when CKE n-1 (if the previous state was self refresh) ...
Page 41
... K4J55323QF-GC Read w/ Auto- : Starts with registration of an READ command with auto precharge enabled and ends Precharge Enabled when tRP has been met. Once t Write w/ Auto- : Starts with registration of a WRITE command with auto precharge enabled and ends Precharge Enabled when The following states must not be interrupted by any executable command ...
Page 42
... K4J55323QF-GC TRUTH TABLE - CURRENT STATE BANK n CURRENT STATE /CS /RAS /CAS H X Any Idle Row Activating Active Prechrging Read L H (Auto-Precharge L H Disable Write L H (Auto-Precharge L H Disabled Read L H (With ...
Page 43
... K4J55323QF-GC 3. Current state definitions : Idle : The bank has been precharged, and t Row Active : A row in the bank has been activated, and t No data bursts/accesses and no register accesses are in progress. Read : A READ burst has been initiated, with auto precharge disabled. Write : A WRITE burst has been initiated, with auto precharge disabled. ...
Page 44
... K4J55323QF-GC ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on V supply relative to Vss DD Voltage on V supply relative to Vss DDQ MAX Junction Temperature Storage temperature Power dissipation Short Circuit Output Current Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
Page 45
... K4J55323QF-GC CLOCK INPUT OPERATING CONDITIONS Recommended operating conditions ( Parameter/ Condition Clock Input Mid-Point Voltage ; CK and /CK Clock Input Voltage Level; CK and /CK Clock Input Differential Voltage ; CK and /CK Clock Input Differential Voltage ; CK and /CK Clock Input Crossing Point Voltage ; CK and /CK Note : 1. This provides a minimum of 1.16V to a maximum of 1.36V, and is always 70% of VDDQ 2 ...
Page 46
... K4J55323QF-GC DC CHARACTERISTICS (Recommended operating conditions unless otherwise noted, Parameter Symbol Operating Current I (One Bank Active) Precharge Standby Current I CC2 in Power-down mode Precharge Standby Current I CC2 in Non Power-down mode Active Standby Current I CC3 power-down mode Active Standby Current in I CC3 in Non Power-down mode ...
Page 47
... K4J55323QF-GC AC CHARACTERISTICS - I Parameter DQS out access time from CK CK high-level width CK low-level width CL=9 CK cycle time CL=8 CL=7 WRITE Latency DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS Active termination setup time Active termination hold time DQS input high pulse width ...
Page 48
... K4J55323QF-GC AC CHARACTERISTICS - II Parameter Row active time Row cycle time Refresh row cycle time RAS to CAS delay for Read RAS to CAS delay for Write Row precharge time Row active to Row active Last data in to Row precharge @ Normal pre- charge Last data in to Row precharge @ Auto precharge t ...
Page 49
... K4J55323QF-GC PACKAGE DIMENSIONS (FBGA) 0.45 0.35 1.40 A1 INDEX MARK 12.0 <Top View> 0.8x11=8.8 0.10 Max 0 ± 0. ± 0.05 Max <Bottom View> 256M GDDR3 SDRAM 12.0 A1 INDEX MARK 0.8 0.40 0.40 Rev 1.7 (Jan. 2005) Unit : mm ...