K9F1G08U0B Samsung, K9F1G08U0B Datasheet
K9F1G08U0B
Available stocks
Related parts for K9F1G08U0B
K9F1G08U0B Summary of contents
Page 1
... K9F1G08U0B INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. ...
Page 2
... K9F1G08U0B Document Title 128M x 8 Bit NAND Flash Memory Revision History Revision No History 0.0 1. Initial issue 1.0 1. 1.8V device is eliminated The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office ...
Page 3
... Serial Access : 25ns(Min.) GENERAL DESCRIPTION Offered in 128Mx8bit, the K9F1G08U0B is a 1G-bit NAND Flash Memory with spare 32M-bit. Its NAND cell provides the most cost- effective solution for the solid state application market. A program operation can be performed in typical 200µs on the (2K+64)Byte page and an erase operation can be performed in typical 1 ...
Page 4
... RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C PACKAGE DIMENSIONS 48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220F #1 #24 0~8° 0.45~0.75 0.018~0.030 K9F1G08U0B-PCB0/PIB0 48-pin TSOP1 11 12 Standard Type 13 14 12mm x 20mm ...
Page 5
... K9F1G08U0B PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS I/O ~ I/O The I/O pins are used to input command, address and data, and to output data during read operations. The pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE CLE The CLE input controls the activating path for commands sent to the command register ...
Page 6
... K9F1G08U0B Figure 1. K9F1G08U0B Functional Block Diagram Command CE Control Logic RE & High Voltage WE CLE Figure 2. K9F1G08U0B Array Organization 64K Pages (=1,024 Blocks) 2K Bytes Page Register I/O 0 1st Cycle A 0 2nd Cycle A 8 3rd Cycle A 12 4th Cycle ...
Page 7
... The memory array consists of 1,024 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F1G08U0B. The K9F1G08U0B has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design ...
Page 8
... Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND, K9F1G08U0B-XCB0 Parameter Supply Voltage ...
Page 9
... Refer to the attached technical notes for appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is guaranteed valid block program/erase cycles with 1bit/512Byte ECC. AC TEST CONDITION (K9F1G08U0B-XCB0 :TA=0 to 70°C, K9F1G08U0B-XIB0:TA=-40 to 85°C, K9F1G08U0B : Vcc=2.7V~3.6V unless otherwise noted) Parameter Input Pulse Levels ...
Page 10
... K9F1G08U0B Program / Erase Characteristics Parameter Program Time Dummy Busy Time for Two-Plane Page Program Number of Partial Program Cycles Block Erase Time NOTE : 1. Typical value is measured at Vcc=3.3V Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc and 25 ...
Page 11
... K9F1G08U0B AC Characteristics for Operation Parameter Data Transfer from Cell to Register ALE to RE Delay CLE to RE Delay Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time CE Access Time RE High to Output Hi-Z CE High to Output Hi-Z CE High to ALE or CLE Don’t Care RE High to Output Hold ...
Page 12
... K9F1G08U0B NAND Flash Technical Notes Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...
Page 13
... K9F1G08U0B NAND Flash Technical Notes Error in write or read operation Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...
Page 14
... K9F1G08U0B NAND Flash Technical Notes Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Erase Error I Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. ...
Page 15
... EDC, the copy-back program operation could also accumulate bit errors. K9F1G08U0B supports copy-back with EDC to prevent cumulative bit errors. To make EDC valid, the page program operation should be performed on either whole page(2112byte) or sector(528byte). Modifying the data of a sector by Random Data Input before Copy-Back Program must be performed for the whole sector and is allowed only once per each sector ...
Page 16
... K9F1G08U0B System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2,112byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of µ ...
Page 17
... K9F1G08U0B NOTE Device K9F1G08U0B I I/O 7 Command Latch Cycle CLE CE WE ALE I/Ox Address Latch Cycle t CLS CLE ALE I/Ox I/O DATA I/Ox Data In/Out Col. Add1 ~2112byte t t CLS CLH ALS ALH Command ...
Page 18
... K9F1G08U0B Input Data Latch Cycle CLE CE ALE t WE I/Ox * Serial Access Cycle after Read R/B NOTES : Transition is measured at ±200mV from steady state voltage with load ALS DIN 0 DIN 1 (CLE=L, WE=H, ALE= REH t t REA ...
Page 19
... K9F1G08U0B Serial Access Cycle after Read REA t CEA I/ R/B NOTES : Transition is measured at ±200mV from steady state voltage with load. Status Read Cycle & EDC Status Read Cycle CLE I/Ox (EDO Type, CLE=L, WE=H, ALE=L) t REH t REA t RLOH Dout This parameter is sampled and not 100% tested. ...
Page 20
... K9F1G08U0B Read Operation CLE ALE RE I/Ox 00h Col. Add1 Column Address R/B Read Operation (Intercepted by CE) CLE CE WE ALE RE I/Ox 00h Col. Add1 Column Address R Row Add2 30h Col. Add2 Row Add1 Row Address Row Add2 Col. Add2 Row Add1 30h ...
Page 21
... K9F1G08U0B FLASH MEMORY 21 ...
Page 22
... K9F1G08U0B Page Program Operation CLE ALE RE I/Ox 80h Co.l Add1 Col. Add2 SerialData Column Address Input Command R/B NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle ADL Din Din Row Add1 ...
Page 23
... K9F1G08U0B ≈ ≈ ≈ ≈ ≈ ≈ 23 FLASH MEMORY ≈ ...
Page 24
... K9F1G08U0B ≈ ≈ ≈ 24 FLASH MEMORY ≈ ≈ ...
Page 25
... K9F1G08U0B Block Erase Operation CLE ALE RE I/Ox 60h Row Add1 Row Address R/B Auto Block Erase Setup Command t t BERS WB Row Add2 D0h Busy Erase Command 25 FLASH MEMORY t WHR 70h I/O 0 I/O =0 Successful Erase 0 Read Status I/O =1 Error in Erase 0 Command ...
Page 26
... K9F1G08U0B Read ID Operation CLE CE WE ALE RE I/Ox 90h Read ID Command Device Device Code (2nd Cycle) K9F1G08U0B REA 00h ECh Maker Code Device Code Address 1cycle 3rd Cycle F1h 00h 26 FLASH MEMORY Device 3rd cyc. 4th cyc. Code 4th Cycle 5th Cycle 95h 5th cyc ...
Page 27
... K9F1G08U0B ID Definition Table Access command = 90H Description 1 st Byte Maker Code nd 2 Byte Device Code 3 rd Byte Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc th Page Size, Block Size,Redundant Area Size, Organization, Serial Access Minimum 4 Byte Plane Number, Plane Size ...
Page 28
... K9F1G08U0B 5th ID Data 1 2 Plane Number 4 8 64Mb 128Mb 256Mb Plane Size 512Mb (w/o redundant Area) 1Gb 2Gb 4Gb 8Gb Reserved Description I/ FLASH MEMORY I/O6 I/O5 I/O4 I/O3 I/ I/O1 I/ ...
Page 29
... K9F1G08U0B Device Operation PAGE READ Page read is initiated by writing 00h-30h to the command register along with four address cycles. After initial power up, 00h command is latched. Therefore only four address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data within the selected page are transferred to the data registers in less than 20µ ...
Page 30
... K9F1G08U0B Figure 7. Random Data Output In a Page R/B RE Address I/Ox 00h 4Cycles Col. Add.1,2 & Row Add.1,2 PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programming of a word or consecutive bytes up to 2,112 single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for a single page ...
Page 31
... K9F1G08U0B Figure 9. Random Data Input In a Page R/B I/Ox 80h Address & Data Input Col. Add.1,2 & Row Add1,2 Data Note: 1. For EDC operation, only one time random data input is possible at the same address. Copy-Back Program The Copy-Back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory. ...
Page 32
... K9F1G08U0B EDC OPERATION Note that for the user who use Copy-Back with EDC mode, only one time random data input is possible at the same address during Copy-Back program or page program mode. For the user who use Copy-Back without EDC, there is no limitation for the random data input at the same address. Figure 12. Page Copy-Back Program Operation with EDC & ...
Page 33
... K9F1G08U0B READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired ...
Page 34
... Address. 1cycle Device Device Code (2nd Cycle) K9F1G08U0B F1h RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased ...
Page 35
... K9F1G08U0B READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis- ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
Page 36
... K9F1G08U0B Data Protection & Power up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at V during power-up and power-down. A recovery time of minimum 100µs is required before internal circuit gets ready for any command sequences as shown in Figure 21 ...