LPC1768 NXP Semiconductors, LPC1768 Datasheet
LPC1768
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LPC1768 Summary of contents
Page 1
... Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching. The peripheral complement of the LPC1768/66/65/64 includes up to 512 kB of flash memory data memory, Ethernet MAC, USB Device/Host/OTG interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, ...
Page 2
... Split APB bus allows high throughput with few stalls between the CPU and DMA. I Serial interfaces: N Ethernet MAC with RMII interface and dedicated DMA controller (LPC1768/66/64 only). N USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. The LPC1764 includes a device controller only ...
Page 3
... Code Read Protection (CRP) with different security levels. I Available as 100-pin LQFP package (14 3. Applications I eMetering I Lighting I Industrial networking I Alarm systems I White goods I Motor control LPC1768_66_65_64_2 Objective data sheet 32-bit ARM Cortex-M3 microcontroller 14 1.4 mm). Rev. 02 — 11 February 2009 LPC1768/66/65/64 © NXP B.V. 2009. All rights reserved ...
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... Total Ethernet USB SRAM 64 kB yes Device/ Host/OTG 64 kB yes Device/ Host/OTG Device/ Host/OTG 32 kB yes Device only Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller CAN I S DAC Package 2 yes yes 100 pins 2 yes ...
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... SSP0 UART2/3 (1) I2S I2C2 RI TIMER TIMER2/3 EXTERNAL INTERRUPTS SYSTEM CONTROL MOTOR CONTROL PWM (1) DAC QUADRATURE ENCODER (1) LPC1768/66/65 only (2) LPC1768/66/64 only (3) LPC1764 USB device only 002aad944 © NXP B.V. 2009. All rights reserved. CLKOUT SCK0 SSEL0 MISO0 MOSI0 RXD2/3 TXD2/3 3 I2SRX 3 I2STX TX_MCLK ...
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... P0[4] — General purpose digital input/output pin. I2SRX_CLK — Receive Clock driven by the master and received by the slave. Corresponds to the signal SCK in the I (LPC1768/66/65 only). RD2 — CAN2 receiver input. CAP2[0] — Capture input for Timer 2, channel 0. Rev. 02 — 11 February 2009 ...
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... SCK0 — Serial clock for SSP0. SCK — Serial clock for SPI. Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller 2 S-bus specification . (LPC1768/66/65 2 S-bus specification . 2 S-bus specification . 2 S-bus specification . (LPC1768/66/65 2 S-bus specification . © NXP B.V. 2009. All rights reserved ...
Page 8
... TXD3 — Transmitter output for UART3. Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller 2 C-bus compliant open-drain pin). 2 C-bus compliant open-drain pin). 2 S-bus specification . 2 S-bus specification . (LPC1768/66/65 2 S-bus specification . © NXP B.V. 2009. All rights reserved ...
Page 9
... ENET_REF_CLK — Ethernet reference clock. (LPC1768/66/64 only). P1[16] — General purpose digital input/output pin. ENET_MDC — Ethernet MIIM clock (LPC1768/66/64 only). P1[17] — General purpose digital input/output pin. ENET_MDIO — Ethernet MIIM data input and output. (LPC1768/66/64 only). Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller 2 C-bus compliance) ...
Page 10
... SSEL0 — Slave Select for SSP0. P1[22] — General purpose digital input/output pin. MC0B — Motor control PWM channel 0, output B. USB_PWRD — Power Status for USB port (host power switch, LPC1768/66/65 only). MAT1[0] — Match output for Timer 1, channel 0. P1[23] — General purpose digital input/output pin. ...
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... Objective data sheet Description P1[27] — General purpose digital input/output pin. CLKOUT — Clock output pin. USB_OVRCR — USB port Over-Current status. (LPC1768/66/65 only). CAP0[1] — Capture input for Timer 0, channel 1. P1[28] — General purpose digital input/output pin. MC2A — Motor control PWM channel 2, output A. ...
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... P3[25] — General purpose digital input/output pin. MAT0[0] — Match output for Timer 0, channel 0. PWM1[2] — Pulse Width Modulator 1, output 2. Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller 2 S-bus specification . 2 S-bus specification . (LPC1768/66/65 2 S-bus specification . © NXP B.V. 2009. All rights reserved ...
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... TCK — Test Clock for JTAG interface. SWDCLK — Serial wire clock. RTCK — JTAG interface control signal. RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC1768/66/65/64 being in Reset state. External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0 ...
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... The use of two core buses allows for simultaneous operations if concurrent operations target different devices. The LPC1768/66/65/64 use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters ...
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... AHB-Lite buses. 7.4 On-chip SRAM The LPC1768/66/65/64 contain a total on-chip static RAM memory. This includes the main 32 kB SRAM, accessible by the CPU and DMA controller on a higher-speed bus, and two additional 16 kB each SRAM blocks situated on a separate slave port on the AHB multilayer matrix ...
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... AHB SRAM 0x2007 C000 0.5 GB reserved 0x1FFF 2000 8 kB boot ROM 0x1FFF 0000 reserved 0x1000 8000 32 kB local static RAM (LPC1768/6/5) 0x1000 4000 16 kB local static RAM (LPC1764) 0x1000 0000 reserved 0x0008 0000 512 kB on-chip flash (LPC1768) 0x0004 0000 256 kB on-chip flash (LPC1766/65) ...
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... Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down resistor enabled. 7.9 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC1768/66/65/64 peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the AHB master ...
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... The value of the output register may be read back as well as the current state of the port pins. LPC1768/66/65/64 use accelerated GPIO functions: • GPIO registers are a dedicated AHB peripheral and are accessed through the AHB multilayer bus so that the fastest possible I/O timing can be achieved. • ...
Page 19
... Pull-up/pull-down resistor configuration and open-drain configuration can be programmed through the pin connect block for each GPIO pin. 7.11 Ethernet (LPC1768/66/64 only) Remark: The Ethernet controller is not available for part LPC1765. The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration ...
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... All transactions are initiated by the host controller. The LPC1768/66/65/64 USB interface includes a device, Host, and OTG controller with on-chip PHY for device and Host functions. The OTG switching protocol is supported through the use of an external controller. Details on typical USB interfacing solutions can be found in Remark: The LPC1764 includes a device controller only ...
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... Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, the LPC1768/66/65/64 can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints. ...
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... Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • FullCAN messages can generate interrupts. 7.14 12-bit ADC The LPC1768/66/65/64 contain one ADC single 12-bit successive approximation ADC with eight channels and DMA support. 7.14.1 Features • 12-bit successive approximation ADC. ...
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... All UARTs have DMA support. 7.17 SPI serial I/O controller The LPC1768/66/65/64 contain one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. ...
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... DMA transfers supported by GPDMA 2 7.19 I C-bus serial I/O controllers The LPC1768/66/65/64 each contain three I 2 The I C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line (SCL) and a Serial Data Line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e ...
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... Controls include reset, stop and mute options separately for I output. 7.21 General purpose 32-bit timers/external event counters The LPC1768/66/65/64 include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specifi ...
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... Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC1768/66/65/64. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. ...
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... Digital filter with programmable delays for encoder input signals. • Can accept decoded signal inputs (clk and direction). • Connected to APB. LPC1768_66_65_64_2 Objective data sheet 32-bit ARM Cortex-M3 microcontroller Rev. 02 — 11 February 2009 LPC1768/66/65/64 © NXP B.V. 2009. All rights reserved ...
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... System tick timer The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception interval. In the LPC1768/66/65/64, this timer can be clocked from the internal AHB clock or from a device pin. 7.27 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘ ...
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... RTC and backup registers The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. The RTC on the LPC1768/66/65/64 is designed to have extremely low power consumption, i.e. less than 1 A. The RTC will typically run from the main chip power supply, conserving battery power while the rest of the device is powered up ...
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... PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC1768/66/65/64 use the IRC as the clock source. Software may later switch to one of the other available clock sources. ...
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... PLL0, wait for the PLL0 to lock, and then connect to the PLL0 as a clock source. 7.29.3 USB PLL (PLL1) The LPC1768/66/65/64 contain a second, dedicated USB PLL1 to provide clocking for the USB interface. The PLL1 receives its clock input from the main oscillator only and provides a fixed 48 MHz clock to the USB block only ...
Page 32
... Power control The LPC1768/66/65/64 support a variety of power control features. There are four special modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfi ...
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... The Deep power-down mode can only be entered from the RTC block. In Deep power-down mode, power is shut off to the entire chip with the exception of the RTC module and the RESET pin. The LPC1768/66/65/64 can wake up from Deep power-down mode via the RESET pin or an alarm match event of the RTC. 7.29.6.5 Wakeup interrupt controller ...
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... NXP Semiconductors 7.29.8 Power domains The LPC1768/66/65/64 provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup Registers. On the LPC1768/66/65/64, I/O pads are powered by the 3 DD(REG)(3V3) CPU and most of the peripherals. ...
Page 35
... Fig 5. 7.30 System control 7.30.1 Reset Reset has four sources on the LPC1768/66/65/64: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating ...
Page 36
... Code security (Code Read Protection - CRP) This feature of the LPC1768/66/65/64 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated fl ...
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... DMA controllers to the various peripheral functions. 7.30.6 External interrupt inputs The LPC1768/66/65/64 include edge sensitive interrupt inputs combined with up to four level sensitive external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode. ...
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... P R amb – = ambient temperature ( C), = the package junction-to-ambient thermal resistance ( C/W) = sum of internal and I/O power dissipation Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller [1] Min Max [4] - 100 [4] - 100 ) < 100 I ) ...
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... Symbol Parameter R thermal resistance from th(j-a) junction to ambient T maximum junction j(max) temperature LPC1768_66_65_64_2 Objective data sheet Conditions LQFP100 package Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller Min Typ Max - <tbd> 150 © NXP B.V. 2009. All rights reserved. Unit C ...
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... [ [ 0 DD(3V3 DDA < V < DD(3V3) I Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller [1] Min Typ Max 2.4 3.3 3.6 2.4 3.3 3.6 2.7 3.3 3.6 2.1 3.3 3.6 2.7 3.3 V DDA - - 5 DD(3V3) 2.0 - ...
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... V = 3.3 V; DD(REG)(3V3 amb RTC running; V present DD(REG)(3V3) RTC running; V not present DD(REG)(3V3 OLS DD(3V3 Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller [1] Min Typ Max - <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> - [8] - ...
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... V < V < includes V range 1 3 GND L with 33 series resistor; steady state drive SoftConnect = ON drops below 1 grounded. DD(3V3 and D . Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller [1] Min Typ Max - - 5.25 0 0.8 - 2.5 0 ...
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... Conditions active mode entered executing code from flash; all peripherals enabled amb but not configured to run. Regulator supply current at different core voltages in active mode Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller 001aac984 (X) 001aac984 (X) © ...
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... Battery supply current for different core voltages in active mode Typical peripheral current consumption = 25 C; all measurements in A; PCLK = amb CCLK = 10 MHz active mode <tbd> <tbd> <tbd> <tbd> Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller 001aac984 (X) 001aac984 ( RTC running; ...
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... UART1 UART2 UART3 PWM1 Motor control PWM Quadrature encoder 2 I C0-bus 2 I C1-bus 2 I C2-bus 2 I S-interface (LPC1768/66/65 only) <tbd> SPI SSP0 SSP1 CAN1 CAN2 ADC DAC (LPC1768/66/65 only) USB Ethernet (LPC1768/66/64 only) GPDMA controller Table 3 i(VBAT BAT ...
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... LOW-level output <tbd> Measured on pins Pn. x.x V. DD(3V3) current versus HIGH-level output voltage V OH Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller 001aac984 (X) OL 001aac984 (X) © NXP B.V. 2009. All rights reserved ...
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... DD(3V3) versus input voltage <tbd> Measured on pins Pn. x.x V. DD(3V3) versus input voltage V pd Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller 001aac984 (X) i 001aac984 (X) i © NXP B.V. 2009. All rights reserved ...
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... Objective data sheet Conditions + +85 C powered; <100 cycles +85 C [1] over specified ranges. Conditions t t CHCL CLCX i(RMS) Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller Min Typ 10000 100000 100000 - 10 - [2] Min Typ 1 - ...
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... X <tbd> Conditions: <tbd> <tbd> Conditions: <tbd>. Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller [2] Min Typ Max <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> 001aac984 (X) 001aac984 (X) © NXP B.V. 2009. All rights reserved. ...
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... C-bus pins [1] over specified ranges. Conditions LOW HD;STA HIGH SU;DAT Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller [2] Min Typ Max [ 0 <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> ...
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... LPC1768_66_65_64_2 Objective data sheet [1] over specified ranges. Conditions measured in SPI amb Master mode; see Figure 18 t su(SPI_MISO) Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller [2] Min Typ Max - 11 - sampling edges 002aad326 © NXP B.V. 2009. All rights reserved. Unit ...
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... Figure 19 see Figure must reject as EOP; see Figure 19 must accept as EOP; see Figure 19 crossover point crossover point differential data to SE0/EOP skew PERIOD FDEOP Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller Min Typ 8 1.3 - 160 - [1] 40 ...
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... SCK (CPOL = 1) Fig 20. SPI master timing (CPHA = 1) LPC1768_66_65_64_2 Objective data sheet T SPICYC t SPIQV DATA VALID MOSI MISO DATA VALID Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller Min Typ <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> ...
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... SPIQV DATA VALID MOSI t SPIDSU MISO DATA VALID T t SPICYC SPICLKH t SPIDSU DATA VALID t SPIQV DATA VALID Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller t t SPICLKH SPICLKL t SPIOH DATA VALID t SPIDH DATA VALID 002aad987 t SPICLKL t SPIDH DATA VALID t SPIOH ...
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... SPI slave timing (CPHA = 0) LPC1768_66_65_64_2 Objective data sheet T SPICYC t SPIDSU MOSI DATA VALID t SPIQV MISO DATA VALID Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller t t SPICLKH SPICLKL t SPIDH DATA VALID t SPIOH DATA VALID 002aad989 © NXP B.V. 2009. All rights reserved. ...
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... NXP Semiconductors 11.8 Ethernet (LPC1768/66/64 only) Table 16. Dynamic characteristics: Ethernet MAC pins Symbol Parameter Ethernet MAC signals for MIIM T clock cycle time cy(clk) t data output valid time v(Q) t data output high-impedance time QZ t data input set-up time su(D) t data input hold time h(D) Ethernet MAC signals for RMII ...
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... Ethernet MAC MIIM timing ENET_REF_CLK ENET_TX_EN ENET_TXD[1:0] ENET_CRS ENET_RXD[1:0] ENET_RX_ER Fig 25. Ethernet RMII timing LPC1768_66_65_64_2 Objective data sheet T cy(clk) ENET_MDC t v(Q) t d(QV su(D) h(D) Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller su(D) h(D) 002aad990 t h(Q) 002aad991 © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 2 11.9 I S-bus interface (LPC1768/66/65 only) Table 17. Dynamic characteristics +85 C. amb Symbol Parameter Common to input and output T clock cycle time cy(clk) t fall time f t rise time r Output t pulse width HIGH WH t pulse width LOW WL t data output valid time ...
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... NXP Semiconductors I2SRX_CLK I2SRX_SDA I2SRX_WS Fig 27. I LPC1768_66_65_64_2 Objective data sheet T cy(clk S-bus timing (input) Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller su(D) h( su(D) su(D) © NXP B.V. 2009. All rights reserved 002aae159 ...
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... See ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after Figure 28. Figure Figure 28. Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller Min Typ ...
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... Objective data sheet (2) (5) (4) (3) 1 LSB (ideal) 4090 (LSB ) IA ideal ). D ). Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller offset error E O (1) 4091 4092 4093 4094 4095 4096 V V DDA SSA 1 LSB = 4096 002aad948 © NXP B.V. 2009. All rights reserved. ...
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... NXP Semiconductors AD0[y] Fig 29. Suggested ADC interface - LPC1768/66/65/64 AD0[y] pin LPC1768_66_65_64_2 Objective data sheet LPC17XX x k SAMPLE Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller R vsi AD0[y] V EXT 002aad949 © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 13. DAC electrical characteristics (LPC1768/66/65 only) Table 19. DAC electrical characteristics +85 C; unless otherwise specified; DAC frequency <tbd> MHz. DDA amb Symbol Parameter PSRR power supply rejection ratio V output voltage O E differential linearity error D E integral non-linearity ...
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... NXP Semiconductors 14. Application information 14.1 Suggested USB interface solutions LPC17xx Fig 30. LPC1768/66/65/64 USB interface on a self-powered device LPC17xx Fig 31. LPC1768/66/65/64 USB interface on a bus-powered device LPC1768_66_65_64_2 Objective data sheet LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller V DD(3V3) USB_UP_LED USB_CONNECT SoftConnect switch R1 1 BUS ...
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... NXP Semiconductors RSTOUT LPC17xx USB_SCL USB_SDA EINTn USB_D+ USB_D Fig 32. LPC1768/66/65 USB OTG port configuration USB_UP_LED USB_D+ USB_D LPC17xx USB_PWRD USB_OVRCR USB_PPWR Fig 33. LPC1768/66/65 USB host port configuration LPC1768_66_65_64_2 Objective data sheet RESET_N ADR/PSW OE_N/INT_N V DD ...
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... NXP Semiconductors USB_UP_LED USB_CONNECT LPC17xx USB_D+ USB_D V BUS Fig 34. LPC1768/66/65/64 USB device port configuration LPC1768_66_65_64_2 Objective data sheet Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller USB-B D connector V BUS 002aad943 © NXP B.V. 2009. All rights reserved. ...
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... scale (1) ( 0.27 0.20 14.1 14.1 16.25 16.25 0.5 0.17 0.09 13.9 13.9 15.75 15.75 REFERENCES JEDEC JEITA MS-026 Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller detail 0.75 1.15 1 0.2 0.08 0.08 0.45 0.85 EUROPEAN PROJECTION SOT407 (1) (1) ...
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... Reduced Media Independent Interface Single Ended Zero Serial Peripheral Interface Serial Synchronous Interface Synchronous Serial Port Tightly Coupled Memory Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Universal Serial Bus Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller © NXP B.V. 2009. All rights reserved ...
Page 69
... LPC1768_66_65_64_2 Objective data sheet Data sheet status Objective data sheet Data sheet descriptive title: added ‘up to 512 kB flash’ Figure 3 “LPC1768/66/65/64 memory map” on page Table 9 “Flash characteristics” on page Objective data sheet Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 11 February 2009 LPC1768/66/65/64 32-bit ARM Cortex-M3 microcontroller © NXP B.V. 2009. All rights reserved ...
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... Nested Vectored Interrupt Controller (NVIC 7.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.7.2 Interrupt sources 7.8 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 17 7.9 General purpose DMA controller . . . . . . . . . . 17 7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.10 Fast general purpose parallel I 7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.11 Ethernet (LPC1768/66/64 only 7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.12 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.12.1 USB device controller . . . . . . . . . . . . . . . . . . . 20 7.12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.12.2 USB host controller (LPC1768/66/65 only 7.12.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.12.3 USB OTG controller (LPC1768/66/65 only 7.12.3.1 Features ...
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... USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.8 Ethernet (LPC1768/66/64 only 11.9 I S-bus interface (LPC1768/66/65 only ADC electrical characteristics . . . . . . . . . . . . 60 13 DAC electrical characteristics (LPC1768/66/65 only Application information 14.1 Suggested USB interface solutions . . . . . . . . 64 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 67 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 68 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 69 18 Legal information Data sheet status . . . . . . . . . . . . . . . . . . . . . . 70 19.1 Defi ...