LPC2378 NXP Semiconductors, LPC2378 Datasheet
LPC2378
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LPC2378 Summary of contents
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... Thumb mode. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty. The LPC2378 is ideal for multi-purpose serial communication applications. It incorporates a 10/100 Ethernet Media Access Controller (MAC), USB full speed device with ...
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... Preliminary data sheet 2 C-bus interfaces (one with open-drain and two with standard port pins (Inter-IC Sound) interface for digital audio input or output. It can be used with Rev. 03 — 27 September 2007 LPC2378 Fast communication chip © NXP B.V. 2007. All rights reserved ...
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... Name LPC2378FBD144 LQFP144 4.1 Ordering options Table 2. Ordering options Type number Flash SRAM (kB) (kB) LPC2378FBD144 512 LPC2378_3 Preliminary data sheet Description plastic low profile quad flat package; 144 leads; body 20 External bus 2 58 MiniBus: 8 data, 16 address, and 2 chip select lines Rev. 03 — ...
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... AD0 A/D CONVERTER D/A CONVERTER AOUT VBAT 2 kB BATTERY RAM power domain 2 RTCX1 RTC RTCX2 OSCILLATOR ALARM WATCHDOG TIMER SYSTEM CONTROL Fig 1. LPC2378 block diagram LPC2378_3 Preliminary data sheet TMS TDI trace signals TRST TCK TDO EXTIN0 32 kB 512 kB TEST/DEBUG FLASH INTERFACE INTERNAL ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. LPC2378 pinning 6.2 Pin description Table 3. Pin description Symbol Pin Type P0[0] to P0[31] I/O [1] P0[0]/RD1/TXD/ 66 I/O SDA1 I O I/O [1] P0[1]/TD1/RXD3/ 67 I/O SCL1 O I I/O [1] P0[2]/TXD0 141 I/O O [1] P0[3]/RXD0 142 I/O I [1] P0[4]/ 116 I/O I2SRX_CLK/ I/O RD2/CAP2[ LPC2378_3 Preliminary data sheet 1 108 LPC2378FBD144 36 002aac584 Description Port 0: Port 32-bit I/O port with individual direction controls for each bit ...
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... It is HIGH when the device is not configured or during global suspend. MOSI1 — Master Out Slave In for SSP1. AD0[7] — A/D converter 0, input 7. Rev. 03 — 27 September 2007 LPC2378 Fast communication chip 2 S-bus specification . 2 S-bus specification . ...
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... I2SRX_CLK — Receive Clock driven by the master and received by the slave. Corresponds to the signal SCK in the I CAP3[0] — Capture input for Timer 3, channel 0. Rev. 03 — 27 September 2007 LPC2378 Fast communication chip 2 S-bus specification . © NXP B.V. 2007. All rights reserved. ...
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... ENET_RXD0 — Ethernet receive data. P1[10] — General purpose digital input/output pin. ENET_RXD1 — Ethernet receive data. P1[14] — General purpose digital input/output pin. ENET_RX_ER — Ethernet receive error. Rev. 03 — 27 September 2007 LPC2378 Fast communication chip 2 S-bus specification . 2 S-bus specification . ...
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... MAT0[0] — Match output for Timer 0, channel 0. P1[29] — General purpose digital input/output pin. PCAP1[1] — Capture input for PWM1, channel 1. MAT0[1] — Match output for Timer 0, channel 0. Rev. 03 — 27 September 2007 LPC2378 Fast communication chip © NXP B.V. 2007. All rights reserved ...
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... TRACEPKT0 — Trace Packet, bit 0. P2[6] — General purpose digital input/output pin. PCAP1[0] — Capture input for PWM1, channel 0. RI1 — Ring Indicator input for UART1. TRACEPKT1 — Trace Packet, bit 1. Rev. 03 — 27 September 2007 LPC2378 Fast communication chip © NXP B.V. 2007. All rights reserved ...
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... D1 — External memory data line 1. P3[2] — General purpose digital input/output pin. D2 — External memory data line 2. P3[3] — General purpose digital input/output pin. D3 — External memory data line 3. Rev. 03 — 27 September 2007 LPC2378 Fast communication chip 2 S-bus specification . 2 S-bus specification . ...
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... A6 — External memory address line 6. P4[7] — General purpose digital input/output pin. A7 — External memory address line 7. P4[8] — General purpose digital input/output pin. A8 — External memory address line 8. Rev. 03 — 27 September 2007 LPC2378 Fast communication chip © NXP B.V. 2007. All rights reserved ...
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... TCK — Test Clock for JTAG interface. RTCK — JTAG interface control signal. Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operate as Trace port after reset. RSTOUT — This is a 1.8 V pin. LOW on this pin indicates LPC2378 being in Reset state. Rev. 03 — 27 September 2007 LPC2378 Fast communication chip © ...
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... RTC power supply: 3 this pin supplies the power to the RTC. 2 C-bus 400 kHz specification compatible pad. It requires an external pull-up to provide output 2 C-bus is floating and does not disturb the I Rev. 03 — 27 September 2007 LPC2378 Fast communication chip , SS but should DD(3V3 lines ...
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... ARM7TDMI-S processor for little-endian byte order. The LPC2378 implements two AHB buses in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the VIC, GPDMA controller, and EMC. ...
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... ARM processor connected to a 16-bit memory system. 7.2 On-chip flash programming memory The LPC2378 incorporates 512 kB flash memory system. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port (UART0). The application program may also erase and/or program the fl ...
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... NXP Semiconductors 3.75 GB Fig 3. LPC2378 memory map 7.5 Interrupt controller The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted ...
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... External memory controller The LPC2378 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals ...
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... Output enable and write enable delays – Extended wait 7.8 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2378 peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination ...
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... The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic in the LPC2378 takes place on a different AHB subsystem, effectively separating Ethernet activity from the rest of the system. The Ethernet DMA can also access off-chip memory ...
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... Physical interface: – Attachment of external PHY chip through standard RMII interface. – PHY register access is available via the MIIM interface. LPC2378_3 Preliminary data sheet Rev. 03 — 27 September 2007 LPC2378 Fast communication chip © NXP B.V. 2007. All rights reserved ...
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... Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, LPC2378 can enter one of the reduced Power-down modes and wake USB activity. • Supports DMA transfers with the DMA RAM all non-control endpoints. ...
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... Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • Full CAN messages can generate interrupts. 7.13 10-bit ADC The LPC2378 contains one ADC single 10-bit successive approximation ADC with eight channels. 7.13.1 Features • 10-bit successive approximation ADC • ...
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... UART3 includes an IrDA mode to support infrared communication. 7.16 SPI serial I/O controller The LPC2378 contains one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master ...
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... The I be controlled by more than one bus master connected to it. 2 The I C-bus implemented in LPC2378 supports bit rates up to 400 kbit/s (Fast I 7.19.1 Features • standard I • ...
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... Controls include reset, stop and mute options separately for I 7.21 General purpose 32-bit timers/external event counters The LPC2378 includes four 32-bit Timer/Counters. The Timer/Counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers ...
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... Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2378. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. ...
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... RTC and battery RAM The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. It uses little power in Power-down mode. On the LPC2378, the RTC can be clocked by a separate 32.768 kHz oscillator programmable prescale divider based on the APB clock ...
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... PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed accuracy. Upon power-up or any chip reset, the LPC2378 uses the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.25.1.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL ...
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... PLL to lock, then connect to the PLL as a clock source. 7.25.3 Wake-up timer The LPC2378 begins operation at power-up and when awakened from Power-down mode by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source ...
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... NXP Semiconductors 7.25.4 Power control The LPC2378 supports a variety of power control features. There are three special modes of processor power reduction: Idle mode, Sleep mode, and Power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, Peripheral Power Control allows shutting down the clocks to individual on-chip peripherals, allowing fi ...
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... System control 7.26.1 Reset Reset has four sources on the LPC2378: the RESET pin, the Watchdog reset, power-on reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable ...
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... AHB2 are the ARM7 and the Ethernet block. 7.26.5 External interrupt inputs The LPC2378 includes edge sensitive interrupt inputs combined with up to four level sensitive external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode. ...
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... The DCC data and control registers are mapped in to addresses in the EmbeddedICE logic. 7.27.2 Embedded trace Since the LPC2378 have significant amounts of on-chip memories not possible to determine how the processor core is operating simply by observing the external pins. The ETM provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to a trace port. A software debugger allows confi ...
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... V DD(3V3) supply voltage is present [2][3] other I/O pins per supply pin per ground pin based on package heat transfer, not device power consumption human body model; all pins Rev. 03 — 27 September 2007 LPC2378 Fast communication chip Min Max Unit 3.0 3.6 V 3.0 3.6 V 0.5 +4.6 V 0.5 +4 ...
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... 0 DD(3V3 0 DDA < V < DD(3V3) I Rev. 03 — 27 September 2007 LPC2378 Fast communication chip [1] Min Typ Max 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3.6 [2] 2.0 3.3 3.6 2.5 3.3 V DDA - - 100 ...
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... CCLK = 10 MHz CCLK = 72 MHz all peripherals enabled; PCLK = CCLK CCLK = 10 MHz CCLK = 72 MHz V = 3.3 V; DD(DCDC)(3V3 amb OLS DD(3V3 < V < 3 Rev. 03 — 27 September 2007 LPC2378 Fast communication chip [1] Min Typ Max - 125 - - 150 ...
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... and D . Conditions Rev. 03 — 27 September 2007 Fast communication chip [1] Min Typ 0.2 - 0 [11 1.1 - Min Typ [1][2][ [1][ [1][ [1][ [1][ [ LPC2378 Max Unit - V 2.5 V 2.0 V 0. 44.1 1.9 k Max Unit V V DDA LSB 2 LSB 3 LSB 0 LSB 40 k © NXP B.V. 2007. All rights reserved ...
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... See ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after Figure 4. Figure Figure 4. Rev. 03 — 27 September 2007 Fast communication chip 4. LPC2378 Figure 4. © NXP B.V. 2007. All rights reserved ...
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... LSB (ideal (LSB ) ia ideal ). D ). Rev. 03 — 27 September 2007 Fast communication chip (1) 1018 1019 1020 1021 1022 1023 V V DDA SSA 1 LSB = 1024 LPC2378 offset gain error error 1024 002aab136 © NXP B.V. 2007. All rights reserved ...
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... NXP Semiconductors AD0[y] Fig 5. Suggested ADC interface - LPC2378 AD0[y] pin LPC2378_3 Preliminary data sheet LPC2378 20 k SAMPLE Rev. 03 — 27 September 2007 LPC2378 Fast communication chip R vsi AD0[y] V EXT 002aac610 © NXP B.V. 2007. All rights reserved ...
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... Figure 9 see Figure must reject as EOP; see Figure 9 must accept as EOP; see Figure 9 over specified ranges. DD(3V3) Conditions Rev. 03 — 27 September 2007 LPC2378 Fast communication chip Min Typ Max 8.5 - 13.8 7 109 1.3 - 2.0 160 - 175 18.5 - +18 ...
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... WST1)) + cy(CCLK) ( 20) [2][ 20) cy(CCLK cy(CCLK [ WST2) cy(CCLK) [ WST2) cy(CCLK) [ cy(CCLK) [ cy(CCLK) [ cy(CCLK) Rev. 03 — 27 September 2007 LPC2378 Fast communication chip Typ Max - + ...
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... RAM cy CCLK – cy CCLK – CYC WRITE cy CCLK t cy CCLK + INIT cy CCLK – ROM cy CCLK LPC2378 Unit cy(CCLK WST 1 – WST 2 – WST 1 – – © NXP B.V. 2007. All rights reserved. ...
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... Preliminary data sheet t CSLAV OELAV t CHOEL t CSLDV t AVCSL t WELWEH t CSLWEL t BLSLBLSH t t CSLBLSL WELDV t CSLDV Rev. 03 — 27 September 2007 LPC2378 Fast communication chip t CSHOEH t h(D) t OEHANV t CHOEH 002aaa749 t WEHANV t BLSHANV t WEHDNV t BLSHDNV 002aaa750 © NXP B.V. 2007. All rights reserved ...
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... SEO/EOP skew PERIOD FDEOP Rev. 03 — 27 September 2007 Fast communication chip t CHCX t CLCH T cy(clk) 002aaa907 extended source EOP width: t receiver EOP width: t LPC2378 FEOPT , t EOPR1 EOPR2 002aab561 © NXP B.V. 2007. All rights reserved ...
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... NXP Semiconductors 11. Application information 11.1 Suggested USB interface solutions LPC23XX Fig 10. LPC2378 USB interface on a self-powered device LPC23XX Fig 11. LPC2378 USB interface on a bus-powered device LPC2378_3 Preliminary data sheet V DD(3V3) USB_UP_LED USB_CONNECT soft-connect switch R1 1 BUS USB_D USB_D DD(3V3) ...
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... JEDEC JEITA MS-026 Rev. 03 — 27 September 2007 Fast communication chip detail 0.75 1.4 1 0.2 0.08 0.08 0.45 1.1 EUROPEAN PROJECTION LPC2378 SOT486 ( 1.1 0 ISSUE DATE 00-03-14 03-02-20 © NXP B.V. 2007. All rights reserved ...
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... Reduced Media Independent Interface Request To Send Single Ended Zero Serial Peripheral Interface Synchronous Serial Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Universal Serial Bus Rev. 03 — 27 September 2007 LPC2378 Fast communication chip © NXP B.V. 2007. All rights reserved ...
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... Preliminary data sheet Data sheet status Preliminary data sheet and 11: changed incorrect character font Preliminary data sheet . DD(1V8) Preliminary data sheet Rev. 03 — 27 September 2007 LPC2378 Fast communication chip Change notice Supersedes - LPC2378_2 - LPC2378_1 - - © NXP B.V. 2007. All rights reserved ...
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... I C-bus — logo is a trademark of NXP B.V. SoftConnect — trademark of NXP B.V. GoodLink — trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 03 — 27 September 2007 LPC2378 Fast communication chip © NXP B.V. 2007. All rights reserved ...
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... Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11 Application information . . . . . . . . . . . . . . . . . 47 11.1 Suggested USB interface solutions . . . . . . . . 47 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 48 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 49 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 50 15 Legal information . . . . . . . . . . . . . . . . . . . . . . 51 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 51 15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 15.3 Disclaimers 15.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Rev. 03 — 27 September 2007 LPC2378 Fast communication chip continued >> © NXP B.V. 2007. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC2378 All rights reserved. Date of release: 27 September 2007 Document identifier: LPC2378_3 ...