LPC2458FET180 NXP Semiconductors, LPC2458FET180 Datasheet

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LPC2458FET180

Manufacturer Part Number
LPC2458FET180
Description
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
2. Features
NXP Semiconductors designed the LPC2458 microcontroller around a 16-bit/32-bit
ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and
embedded trace. The LPC2458 has 512 kB of on-chip high-speed flash memory. This
flash memory includes a special 128-bit wide memory interface and accelerator
architecture that enables the CPU to execute sequential instructions from flash memory at
the maximum 72 MHz system clock rate. This feature is available only on the LPC2000
ARM microcontroller family of products. The LPC2458 can execute both 32-bit ARM and
16-bit Thumb instructions. Support for the two instruction sets means engineers can
choose to optimize their application for either performance or code size at the sub-routine
level. When the core executes instructions in Thumb state it can reduce code size by
more than 30 % with only a small loss in performance while executing instructions in ARM
state maximizes core performance.
The LPC2458 microcontroller is ideal for multi-purpose communication applications. It
incorporates a 10/100 Ethernet Media Access Controller (MAC), a USB full-speed
Device/Host/OTG Controller with 4 kB of endpoint RAM, four UARTs, two Controller Area
Network (CAN) channels, an SPI interface, two Synchronous Serial Ports (SSP), three I
interfaces, and an I
interfaces are the following feature components; an on-chip 4 MHz internal precision
oscillator, 98 kB of total RAM consisting of 64 kB of local SRAM, 16 kB SRAM for
Ethernet, 16 kB SRAM for general purpose DMA, 2 kB of battery powered SRAM, and an
External Memory Controller (EMC). These features make this device optimally suited for
communication gateways and protocol converters. Complementing the many serial
communication controllers, versatile clocking capabilities, and memory features are
various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, two PWM units, four external
interrupt pins, and up to 136 fast GPIO lines. The LPC2458 connects 64 of the GPIO pins
to the hardware based Vector Interrupt Controller (VIC) that means these external inputs
can generate edge-triggered interrupts. All of these features make the LPC2458
particularly suitable for industrial control and medical systems.
LPC2458
Single-chip 16-bit/32-bit micro; 512 kB flash, ethernet, CAN,
ISP/IAP, USB 2.0 device/host/OTG, external memory interface
Rev. 01 — 6 July 2007
ARM7TDMI-S processor, running at up to 72 MHz.
512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. Flash program memory is on the ARM
local bus for high performance CPU access.
98 kB on-chip SRAM includes:
64 kB of SRAM on the ARM local bus for high performance CPU access.
16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
2
S interface. Supporting this collection of serial communications
Preliminary data sheet
2
C

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LPC2458FET180 Summary of contents

Page 1

... ISP/IAP, USB 2.0 device/host/OTG, external memory interface Rev. 01 — 6 July 2007 1. General description NXP Semiconductors designed the LPC2458 microcontroller around a 16-bit/32-bit ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and embedded trace. The LPC2458 has 512 kB of on-chip high-speed flash memory. This ...

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... NXP Semiconductors ‹ SRAM for general purpose DMA use also accessible by the USB. ‹ SRAM data storage powered from the Real-Time Clock (RTC) power domain. „ Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet DMA, USB DMA, and program execution from on-chip flash with no contention. ...

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... Protocol converter „ Communications 4. Ordering information Table 1. Ordering information Type number Package Name Description LPC2458FET180 TFBGA180 plastic thin fine-pitch ball grid array package; 180 balls; body 0.8 mm SOT570-2 4.1 Ordering options Table 2. Ordering options Type number Flash SRAM (kB) (kB) LPC2458FET180 512 ...

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... NXP Semiconductors 5. Block diagram LPC2458 P0, P1, P2 P3, P4 SRAM HIGH-SPEED GPI/O CONTROLLERS 136 PINS TOTAL SRAM AHB2 16 kB ETHERNET SRAM MII/RMII MAC WITH DMA EINT3 to EINT0 EXTERNAL INTERRUPTS P0 CAP0/CAP1/ CAPTURE/COMPARE CAP2/CAP3 TIMER0/TIMER1 MAT2, TIMER2/TIMER3 2 u MAT3, 2 uMAT1/MAT0 6 u PWM0, PWM1 ...

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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. LPC2458 pinning TFBGA180 package Table 3. Pin allocation table Pin Symbol Pin Symbol Row A 1 P3[12]/D12 2 P3[2]/D2 5 P1[1]/ENET_TXD1 6 P3[8]/D8 9 P1[3]/ENET_TXD3 MCICMD/PWM0[2] 13 P0[9]/I2STX_SDA/ 14 P1[12]/ENET_RXD3/ MOSI1/MAT2[3] MCIDAT3/PCAP0[0] Row B 1 TDO 2 P3[11]/D11 5 P1[0]/ENET_TXD0 6 P1[8]/ENET_CRS_DV/ ENET_CRS 9 P4[29]/BLS3/ 10 P1[6]/ENET_TX_CLK/ MAT2[1]/RXD3 ...

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... NXP Semiconductors Table 3. Pin allocation table …continued Pin Symbol Pin Symbol 13 P1[7]/ENET_COL/ 14 P2[1]/PWM1[2]/RXD1/ MCIDAT1/PWM0[5] PIPESTAT0 Row D 1 P0[26]/AD0[3]/ 2 TCK AOUT/RXD3 5 P0[2]/TXD0 6 P3[0]/D0 9 P4[25]/WE 10 P4[28]/BLS2/ MAT2[0]/TXD3 P1[13]/ENET_RX_DV SSIO Row E 1 P0[24]/AD0[1 I2SRX_WS/CAP3[1] 5 DBGEN 6 P3[1]/ DD(DCDC)(3V3) 13 P2[3]/PWM1[4]/ 14 P2[4]/PWM1[5]/ ...

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... NXP Semiconductors Table 3. Pin allocation table …continued Pin Symbol Pin Symbol 9 10 P0[19]/DSR1/ MCICLK/SDA1 13 P0[18]/DCD1 MOSI0/MOSI Row K 1 VBAT 2 P1[31]/USB_OVRCR2/ SCK1/AD0[5] 5 P0[29]/USB_D+1 6 P1[20]/USB_TX_DP1/ PWM1[2]/SCK0 9 P4[3]/A3 10 P4[6]/A6 13 P4[26]/BLS0 14 P0[20]/DTR1/ MCICMD/SCL1 Row L 1 P2[29]/DQMOUT1 2 XTAL1 5 P1[18]/USB_UP_LED1/ 6 P4[0]/A0 PWM1[1]/CAP1[ P0[10]/TXD2/SDA2/ SSIO MAT3[0] ...

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... NXP Semiconductors 6.2 Pin description Table 4. Pin description Symbol Ball Type P0[0] to P0[31] I/O [1] P0[0]/RD1/ M10 I/O TXD3/SDA1 I O I/O [1] P0[1]/TD1/RXD3/ N11 I/O SCL1 O I I/O [1] P0[2]/TXD0 D5 I/O O [1] P0[3]/RXD0 A3 I/O I [1] P0[4]/ A11 I/O I2SRX_CLK/ I/O RD2/CAP2[ [1] P0[5]/ B11 I/O I2SRX_WS/ I/O TD2/CAP2[ [1] P0[6]/ D11 I/O I2SRX_SDA/ I/O SSEL1/MAT2[0] I/O O [1] P0[7]/ B12 I/O I2STX_CLK/ I/O SCK1/MAT2[1] I/O O [1] P0[8]/ C12 I/O I2STX_WS/ ...

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... NXP Semiconductors Table 4. Pin description …continued Symbol Ball Type [1] P0[9]/ A13 I/O I2STX_SDA/ I/O MOSI1/MAT2[3] I/O O [1] P0[10]/TXD2/ L10 I/O SDA2/MAT3[0] O I/O O [1] P0[11]/RXD2/ P12 I/O SCL2/MAT3[1] I I/O O [2] P0[12]/ J4 I/O USB_PPWR2/ O MISO1/AD0[6] I/O I [2] P0[13]/ J5 I/O USB_UP_LED2/ O MOSI1/AD0[7] I/O I [1] P0[14]/ M5 I/O USB_HSTEN2/ O USB_CONNECT2/S O SEL1 I/O [1] P0[15]/TXD1/ H13 I/O SCK0/SCK O I/O I/O [1] P0[16]/RXD1/ H14 I/O SSEL0/SSEL I I/O I/O [1] P0[17]/CTS1/ J12 ...

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... NXP Semiconductors Table 4. Pin description …continued Symbol Ball Type [1] P0[18]/DCD1/ J13 I/O MOSI0/MOSI I I/O I/O [1] P0[19]/DSR1/ J10 I/O MCICLK/SDA1 I O I/O [1] P0[20]/DTR1/ K14 I/O MCICMD/SCL1 O I/O I/O [1] P0[21]/RI1/ K11 I/O MCIPWR/RD1 [1] P0[22]/RTS1/ L14 I/O MCIDAT0/TD1 O I/O O [2] P0[23]/AD0[0]/ F5 I/O I2SRX_CLK/ I CAP3[0] I/O I [2] P0[24]/AD0[1]/ E1 I/O I2SRX_WS/ I CAP3[1] I/O I [2] P0[25]/AD0[2]/ E4 I/O I2SRX_SDA/ I TXD3 ...

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... NXP Semiconductors Table 4. Pin description …continued Symbol Ball Type [4] P0[28]/SCL0 M1 I/O I/O [5] P0[29]/USB_D+1 K5 I/O I/O [5] P0[30]/USB_D1 N4 I/O I/O [5] P0[31]/USB_D+2 N1 I/O I/O P1[0] to P1[31] I/O [1] P1[0]/ B5 I/O ENET_TXD0 O [1] P1[1]/ A5 I/O ENET_TXD1 O [1] P1[2]/ B7 I/O ENET_TXD2/ O MCICLK/ O PWM0[1] O [1] P1[3]/ A9 I/O ENET_TXD3/ O MCICMD/ I/O PWM0[2] O [1] P1[4]/ C6 I/O ENET_TX_EN O [1] P1[5]/ B13 I/O ENET_TX_ER/ O MCIPWR/ O PWM0[3] O [1] P1[6]/ B10 I/O ENET_TX_CLK/ I MCIDAT0/ I/O PWM0[4] ...

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... NXP Semiconductors Table 4. Pin description …continued Symbol Ball Type [1] P1[10]/ A7 I/O ENET_RXD1 I [1] P1[11]/ A12 I/O ENET_RXD2/ I MCIDAT2/ I/O PWM0[6] O [1] P1[12]/ A14 I/O ENET_RXD3/ I MCIDAT3/ I/O PCAP0[0] I [1] P1[13]/ D14 I/O ENET_RX_DV I [1] P1[14]/ D8 I/O ENET_RX_ER I [1] P1[15]/ A8 I/O ENET_REF_CLK/E I NET_RX_CLK [1] P1[16]/ B8 I/O ENET_MDC I [1] P1[17]/ C9 I/O ENET_MDIO I/O [1] P1[18]/ L5 I/O USB_UP_LED1/ O PWM1[1]/ CAP1[ [1] P1[19]/ P5 I/O USB_TX_E1/ O USB_PPWR1/ ...

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... NXP Semiconductors Table 4. Pin description …continued Symbol Ball Type [1] P1[22]/ M6 I/O USB_RCV1/ I USB_PWRD1/ I MAT1[0] O [1] P1[23]/ N7 I/O USB_RX_DP1/ I PWM1[4]/MISO0 O I/O [1] P1[24]/ P7 I/O USB_RX_DM1/ I PWM1[5]/MOSI0 O I/O [1] P1[25]/ L7 I/O USB_LS1/ O USB_HSTEN1/ O MAT1[1] O [1] P1[26]/ P8 I/O USB_SSPND1/ O PWM1[6]/ O CAP0[0] I [1] P1[27]/ M9 I/O USB_INT1/ I USB_OVRCR1/ I CAP0[1] I [1] P1[28]/ P10 I/O USB_SCL1/ I/O PCAP1[0]/ I MAT0[0] O [1] P1[29]/ N10 I/O USB_SDA1/ ...

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... NXP Semiconductors Table 4. Pin description …continued Symbol Ball Type P2[0] to P2[31] I/O [1] P2[0]/PWM1[1]/ D12 I/O TXD1/ O TRACECLK O O [1] P2[1]/PWM1[2]/ C14 I/O RXD1/ O PIPESTAT0 I O [1] P2[2]/PWM1[3]/ E11 I/O CTS1/ O PIPESTAT1 I O [1] P2[3]/PWM1[4]/ E13 I/O DCD1/ O PIPESTAT2 I O [1] P2[4]/PWM1[5]/ E14 I/O DSR1/ O TRACESYNC I O [1] P2[5]/PWM1[6]/ F12 I/O DTR1/ O TRACEPKT0 O O [1] P2[6]/PCAP1[0]/RI1/ ...

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... NXP Semiconductors Table 4. Pin description …continued Symbol Ball Type [1] P2[9]/ H11 I/O USB_CONNECT1/ O RXD2/ EXTIN0 I I [6] P2[10]/EINT0 M13 I/O I [6] P2[11]/EINT1/ M12 I/O MCIDAT1/ I I2STX_CLK I/O I/O [6] P2[12]/EINT2/ N14 I/O MCIDAT2/ I I2STX_WS I/O I/O [6] P2[13]/EINT3/ M11 I/O MCIDAT3/ I I2STX_SDA I/O I/O [1] P2[16]/CAS P9 I/O O [1] P2[17]/RAS P11 I/O O [1] P2[18]/ P3 I/O CLKOUT0 O [1] P2[19]/ N5 I/O CLKOUT1 O [1] P2[20]/DYCS0 P6 I/O O [1] P2[21]/DYCS1 ...

Page 16

... NXP Semiconductors Table 4. Pin description …continued Symbol Ball Type [1] P2[28]/ M2 I/O DQMOUT0 O [1] P2[29]/ L1 I/O DQMOUT1 O P3[0] to P3[31] I/O [1] P3[0]/D0 D6 I/O I/O [1] P3[1]/D1 E6 I/O I/O [1] P3[2]/D2 A2 I/O I/O [1] P3[3]/D3 G5 I/O I/O [1] P3[4]/D4 D3 I/O I/O [1] P3[5]/D5 E3 I/O I/O [1] P3[6]/D6 F4 I/O I/O [1] P3[7]/D7 G3 I/O I/O [1] P3[8]/D8 A6 I/O I/O [1] P3[9]/D9 A4 I/O I/O [1] P3[10]/D10 B3 I/O I/O [1] P3[11]/D11 B2 I/O I/O [1] P3[12]/D12 A1 I/O I/O [1] P3[13]/D13 C1 I/O I/O [1] P3[14]/D14 F1 I/O I/O [1] P3[15]/D15 G4 I/O I/O LPC2468_1 Preliminary data sheet Description P2[28] — General purpose digital input/output pin. ...

Page 17

... NXP Semiconductors Table 4. Pin description …continued Symbol Ball Type [1] P3[23]/D23/ M4 I/O CAP0[0]/ I/O PCAP1[ [1] P3[24]/D24/ N3 I/O CAP0[1]/ I/O PWM1[ [1] P3[25]/D25/ M3 I/O MAT0[0]/ I/O PWM1[ [1] P3[26]/D26/ K7 I/O MAT0[1]/ I/O PWM1[ P4[0] to P4[31] I/O [1] P4[0]/A0 L6 I/O I/O [1] P4[1]/A1 M7 I/O I/O [1] P4[2]/A2 M8 I/O I/O [1] P4[3]/A3 K9 I/O I/O [1] P4[4]/A4 P13 I/O I/O [1] P4[5]/A5 H10 I/O I/O [1] P4[6]/A6 K10 I/O I/O [1] P4[7]/A7 K12 I/O I/O [1] P4[8]/A8 J11 I/O I/O [1] P4[9]/A9 H12 I/O I/O [1] P4[10]/A10 G12 I/O I/O LPC2468_1 Preliminary data sheet Description P3[23] — ...

Page 18

... NXP Semiconductors Table 4. Pin description …continued Symbol Ball Type [1] P4[11]/A11 F11 I/O I/O [1] P4[12]/A12 F10 I/O I/O [1] P4[13]/A13 B14 I/O I/O [1] P4[14]/A14 E8 I/O I/O [1] P4[15]/A15 C10 I/O I/O [1] P4[16]/A16 N12 I/O I/O [1] P4[17]/A17 N13 I/O I/O [1] P4[18]/A18 P14 I/O I/O [1] P4[19]/A19 M14 I/O I/O [1] P4[24]/OE C8 I/O O [1] P4[25]/WE D9 I/O O [1] P4[26]/BLS0 K13 I/O O [1] P4[27]/BLS1 F14 I/O O [1] P4[28]/BLS2/ D10 I/O MAT2[0]/TXD3 ...

Page 19

... NXP Semiconductors Table 4. Pin description …continued Symbol Ball Type [1] DBGEN E5 I [1] TDO B1 O [1] TDI C3 I [1] TMS C2 I [1] TRST D4 I [1] TCK D2 I [1] RTCK C4 I/O [1] RSTOUT H2 O [7] RESET J1 I [8] XTAL1 L2 I [8] XTAL2 K4 O [8] RTCX1 J2 I [8] RTCX2 H4, I SSIO P4,L9, L13, G13,D13 , C11, [9] B4 ...

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... NXP Semiconductors [ tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled. [ tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled ...

Page 21

... NXP Semiconductors decode mechanism are much simpler than those of microprogrammed complex instruction set computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously ...

Page 22

... NXP Semiconductors Table 5. Address range General use 0x0000 0000 to 0x3FFF FFFF 0x4000 0000 to 0x7FFF FFFF 0x8000 0000 to 0xDFFF FFFF 0xE000 0000 to 0xEFFF FFFF 0xF000 0000 to 0xFFFF FFFF LPC2468_1 Preliminary data sheet LPC2458 memory usage and details Address range details and description ...

Page 23

... NXP Semiconductors 4.0 GB 3.75 GB 3.5 GB 3.0 GB 2.0 GB 1.0 GB 0.0 GB Fig 3. LPC2458 memory map 7.5 Interrupt controller The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted ...

Page 24

... NXP Semiconductors service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs, which include all interrupt requests that are not classified as FIQs, have a programmable interrupt priority ...

Page 25

... NXP Semiconductors – Asynchronous page mode read – Programmable Wait States – Bus turnaround delay – Output enable and write enable delays – Extended wait • Two chip selects for synchronous memory and two chip selects for static memory devices • ...

Page 26

... NXP Semiconductors • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the peripheral. • ...

Page 27

... NXP Semiconductors 7.10 Ethernet The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity ...

Page 28

... NXP Semiconductors – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter. • Physical interface: – Attachment of external PHY chip through standard MII or RMII interface. – PHY register access is available via the MIIM interface. ...

Page 29

... NXP Semiconductors 7.11.2.1 Features • OHCI compliant. • Two downstream ports. • Supports per-port power switching. 7.11.3 USB OTG Controller USB OTG (On-The-Go supplement to the USB 2.0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. ...

Page 30

... NXP Semiconductors • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • Full CAN messages can generate interrupts. 7.13 10-bit ADC The LPC2458 contains one ADC single 10-bit successive approximation ADC with eight channels. 7.13.1 Features • 10-bit successive approximation ADC • ...

Page 31

... NXP Semiconductors • Fractional divider for baud rate control, auto baud capabilities and FIFO control mechanism that enables software flow control implementation. • UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). ...

Page 32

... NXP Semiconductors 7.18.1 Features • The MCI interface provides all functions specific to the SD/MMC memory card. These include the clock generation unit, power management control, and command and data transfer. • Conforms to Multimedia Card Specification v2.11. • Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96. ...

Page 33

... NXP Semiconductors 2 The I S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I master, and one slave. The I and receive channel, each of which can operate as either a master or a slave. 7.20.1 Features • ...

Page 34

... NXP Semiconductors 7.22 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2458. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers ...

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... NXP Semiconductors • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. • ...

Page 36

... NXP Semiconductors 7.24.1 Features • Measures the passage of time to maintain a calendar and clock. • Ultra low power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. • Dedicated 32 kHz oscillator or programmable prescaler from APB clock. ...

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... NXP Semiconductors 7.25.1.3 RTC oscillator The RTC oscillator can be used as the clock source for the RTC and/or the WDT. Also, the RTC oscillator can be used to drive the PLL and the CPU. 7.25.2 PLL The PLL accepts an input clock frequency in the range of 32 kHz to 50 MHz. The input frequency is multiplied high frequency, then divided down to provide the actual clock used by the CPU and the USB block ...

Page 38

... NXP Semiconductors PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, Peripheral power control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application ...

Page 39

... NXP Semiconductors 7.25.4.4 Power domains The LPC2458 provides two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the Battery RAM. On the LPC2458, I/O pads are powered by the 3 DD(DCDC)(3V3) the CPU and most of the peripherals. ...

Page 40

... NXP Semiconductors The second stage of low-voltage detection asserts Reset to inactivate the LPC2458 when the voltage on the V flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below which point the power-on reset circuitry maintains the overall Reset ...

Page 41

... NXP Semiconductors 7.26.5 External interrupt inputs The LPC2458 includes edge sensitive interrupt inputs combined with up to four level sensitive external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode. 7.26.6 Memory mapping control The memory mapping control alters the mapping of the interrupt vectors that appear at the beginning at address 0x0000 0000 ...

Page 42

... NXP Semiconductors Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction. 7.27.3 RealMonitor RealMonitor is a configurable software module, developed by ARM Inc., which enables real-time debug lightweight debug monitor that runs in the background while users debug their foreground application ...

Page 43

... NXP Semiconductors 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter supply voltage DD(DCDC)(3V3) (3 analog 3.3 V pad supply voltage DDA V input voltage on pin VBAT i(VBAT) V input voltage on pin VREF ...

Page 44

... NXP Semiconductors 9. Static characteristics Table 7. Static characteristics + for commercial applications, unless otherwise specified. amb Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter DD(DCDC)(3V3) supply voltage (3 analog 3.3 V pad DDA supply voltage V input voltage on pin i(VBAT) VBAT V input voltage on pin ...

Page 45

... NXP Semiconductors Table 7. Static characteristics …continued  +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter I active mode DC-to-DC DD(DCDC)act(3V3) converter supply current (3 power-down mode DD(DCDC)pd(3V3) DC-to-DC converter supply current (3 active mode battery BATact supply current 2 I C-bus pins (P0[27] and P0[28]) ...

Page 46

... NXP Semiconductors Table 7. Static characteristics …continued  +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter V differential input DI sensitivity V differential common CM mode voltage range V single-ended receiver th(rs)se switching threshold voltage V LOW-level output OL voltage for low-/full-speed V HIGH-level output OH voltage (driven) for ...

Page 47

... NXP Semiconductors [1] Conditions 3.3 V. SSA DDA [2] The ADC is monotonic, there are no missing codes. [3] The differential linearity error ( the difference between the actual step width and the ideal step width. See D [4] The integral non-linearity ( the peak difference between the center of the steps of the actual and the ideal transfer curve after L(adj) appropriate adjustment of gain and offset errors ...

Page 48

... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. ...

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... NXP Semiconductors AD0[y] SAMPLE Fig 5. Suggested ADC interface - LPC2458 AD0[y] pin LPC2468_1 Preliminary data sheet LPC2XXX R vsi 20 k: AD0[ Rev. 01 — 6 July 2007 LPC2458 Fast communication chip V EXT 002aac733 © NXP B.V. 2007. All rights reserved ...

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... NXP Semiconductors 10. Dynamic characteristics Table 9. Dynamic characteristics of USB pins (full-speed pF 1 DD(3V3) Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP FEOPT ...

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... NXP Semiconductors Table 11. External memory interface dynamic characteristics pF amb Symbol Parameter Common to read and write cycles t XCLK HIGH to address valid CHAV time t XCLK HIGH to CS LOW time CHCSL t XCLK HIGH to CS HIGH CHCSH time t XCLK HIGH to address ...

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... NXP Semiconductors Table 11. External memory interface dynamic characteristics pF amb Symbol Parameter t BLS HIGH to data invalid BLSHDNV time t XCLK HIGH to data valid CHDV time t XCLK HIGH to WE LOW CHWEL time t XCLK HIGH to BLS LOW CHBLSL time t XCLK HIGH to WE HIGH ...

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... NXP Semiconductors 10.1 Timing XCLK CS addr data t CSLOEL OE Fig 6. External memory read access XCLK CS BLS/WE addr data OE Fig 7. External memory write access LPC2468_1 Preliminary data sheet t CSLAV OELAV t CHOEL t CSLDV t AVCSL t WELWEH t CSLWEL t BLSLBLSH t t CSLBLSL WELDV t CSLDV Rev. 01 — 6 July 2007 ...

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... NXP Semiconductors V − 0 0.2V 0.2V DD 0.45 V Fig 8. External clock timing t PERIOD crossover point differential data lines differential data to SEO/EOP skew Fig 9. Differential data-to-EOP transition skew and EOP width LPC2468_1 Preliminary data sheet + 0 − 0 CHCL CLCX crossover point extended ...

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... NXP Semiconductors 11. Application information 11.1 Suggested USB interface solutions LPC24XX Fig 10. LPC2458 USB interface on a self-powered device LPC24XX Fig 11. LPC2458 USB interface on a bus-powered device LPC2468_1 Preliminary data sheet V DD(3V3) USB_UP_LED USB_CONNECT soft-connect switch R1 1 BUS USB_D USB_D 002aac737 ...

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... NXP Semiconductors RSTOUT USB_SCL1 USB_SDA1 USB_INT1 USB_D+1 USB_D1 USB_UP_LED1 LPC24XX USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D2 USB_UP_LED2 Fig 12. LPC2458 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host LPC2468_1 Preliminary data sheet RESET_N ADR/PSW OE_N/INT_N V DD ...

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... NXP Semiconductors RSTOUT USB_TX_E1 USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 LPC24XX USB_SCL1 USB_SDA1 USB_INT1 USB_UP_LED1 Fig 13. LPC2458 USB OTG port configuration: VP_VM mode LPC2468_1 Preliminary data sheet V DD RESET_N OE_N/INT_N DAT_VP SE0_VM RCV ISP1301 ADR/PSW SPEED SUSPEND SCL SDA INT_N ...

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... NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC24XX USB_UP_LED2 USB_CONNECT2 USB_D+2 USB_D2 V BUS Fig 14. LPC2458 USB OTG port configuration: USB port 2 device, USB port 1 host LPC2468_1 Preliminary data sheet ENA FLAGA 5 V OUTA LM3526 ...

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... NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC24XX USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D2 USB_UP_LED2 Fig 15. LPC2458 USB OTG port configuration: USB port 1 host, USB port 2 host LPC2468_1 Preliminary data sheet ENA FLAGA 5 V OUTA IN LM3526-L OUTB ...

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... NXP Semiconductors 12. Package outline TFBGA180: thin fine-pitch ball grid array package; 180 balls; body 0.8 mm ball A1 index area ball A1 index area DIMENSIONS (mm are the original dimensions) A UNIT max. ...

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... NXP Semiconductors 13. Abbreviations Table 13. Acronym list Acronym Description ADC Analog-to-Digital Converter AHB Advanced High-performance Bus AMBA Advanced Microcontroller Bus Architecture APB Advanced Peripheral Bus ATX Analog Transceiver BLS Byte Lane Select BOD BrownOut Detection CAN Controller Area Network DAC Digital-to-Analog Converter ...

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... NXP Semiconductors 14. Revision history Table 14. Revision history Document ID Release date LPC2458_1 <tbd> LPC2468_1 Preliminary data sheet Data sheet status Change notice Preliminary data sheet - Rev. 01 — 6 July 2007 LPC2458 Fast communication chip Supersedes - © NXP B.V. 2007. All rights reserved ...

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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...

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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Functional description . . . . . . . . . . . . . . . . . . 23 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 23 7.2 On-chip flash programming memory . . . . . . . 24 7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 25 7.4 Memory map 7.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 26 7.5.1 Interrupt sources 7.6 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 27 7 ...

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... NXP Semiconductors 15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 15.4 Trademarks Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Fast communication chip Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp ...

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