LPC2478FBD208 NXP Semiconductors, LPC2478FBD208 Datasheet
LPC2478FBD208
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LPC2478FBD208 Summary of contents
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... LCD, USB 2.0 device/host/OTG, external memory interface Rev. 01 — 6 July 2007 1. General description NXP Semiconductors designed the LPC2478 microcontroller, powered by the ARM7TDMI-S core highly integrated microcontroller for a wide range of applications that require advanced communications and high quality graphic displays. The LPC2478 microcontroller has 512 kB of on-chip high-speed flash memory. This flash ...
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... NXP Semiconductors „ LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film Transistors (TFT) displays. ‹ Dedicated DMA controller. ‹ Selectable display resolution (up to 1024 u 768 pixels). ‹ Supports up to 24-bit true-color mode. „ Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet DMA, USB DMA, and program execution from on-chip flash with no contention. „ ...
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... Table 1. Ordering information Type number Package Name Description LPC2478FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 1.4 mm LPC2478FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 0.7 mm LPC2478_1 Preliminary data sheet Rev. 01 — 6 July 2007 ...
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... NXP Semiconductors 4.1 Ordering options Table 2. Ordering options Type number Flash SRAM (kB) (kB) LPC2478FBD208 512 64 16 LPC2478FET208 512 64 16 LPC2478_1 Preliminary data sheet External Ethernet USB bus Full MII/RMII 32-bit Full MII/RMII 32-bit Rev. 01 — 6 July 2007 LPC2478 Fast communication chip ...
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... NXP Semiconductors 5. Block diagram LPC2478 P0, P1, P2 P3, P4 SRAM HIGH-SPEED GPI/O CONTROLLERS 160 PINS TOTAL SRAM AHB2 16 kB ETHERNET SRAM MII/RMII MAC WITH DMA EINT3 to EINT0 EXTERNAL INTERRUPTS P0 CAP0/CAP1/ CAPTURE/COMPARE CAP2/CAP3 TIMER0/TIMER1 MAT2/MAT3, TIMER2/TIMER3 2 u MAT0, 3 uMAT1 6 u PWM0/PWM1 ...
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... Fig 3. LPC2478 pinning TFBGA208 package Table 3. Pin allocation table Pin Symbol Pin Symbol Row A 1 P3[27]/D27 CAP1[0]/PWM1[4] 5 P1[4]/ENET_TX_EN 6 P1[9]/ENET_RXD0 9 P1[17]/ENET_MDIO 10 P1[3]/ENET_TXD3/ MCICMD/PWM0[2] LPC2478_1 Preliminary data sheet 1 156 LPC2478FBD208 52 105 002aac808 ball A1 index area ...
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... NXP Semiconductors Table 3. Pin allocation table …continued Pin Symbol Pin Symbol 13 P3[20]/D20/ 14 P1[11]/ENET_RXD2/ PWM0[5]/DSR1 MCIDAT2/PWM0[6] 17 P1[5]/ENET_TX_ER/ - MCIPWR/PWM0[3] Row B 1 P3[2]/D2 2 P3[10]/D10 5 P1[1]/ENET_TXD1 P4[25]/WE 10 P4[29]/BLS3/MAT2[1]/ LCDVD[7]/LCDVD[11]/ LCDVD[3]/RXD3 P3[19]/D19/ DD(3V3) PWM0[4]/DCD1 17 P2[0]/PWM1[1]/TXD1/ - TRACECLK/LCDPWR Row C 1 P3[13]/D13 2 TDI ...
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... NXP Semiconductors Table 3. Pin allocation table …continued Pin Symbol Pin Symbol 14 P4[11]/A11 15 P3[17]/D17/ PWM0[2]/RXD1 Row G 1 P3[5]/D5 2 P0[24]/AD0[1]/ I2SRX_WS/CAP3[ P4[27]/BLS1 Row H 1 P0[23]/AD0[0]/ 2 P3[14]/D14 I2SRX_CLK/CAP3[ P2[8]/TD2/TXD2/ SSIO TRACEPKT3/ LCDVD[2]/LCDVD[6] Row J 1 P3[6]/ P0[16]/RXD1/ 15 P4[23]/A23/ SSEL0/SSEL RXD2/MOSI1 Row K 1 VREF ...
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... NXP Semiconductors Table 3. Pin allocation table …continued Pin Symbol Pin Symbol 9 P1[23]/USB_RX_DP1 LCDVD[9]/LCDVD[13]/ PWM1[4]/MISO0 13 P2[15]/CS3/ 14 P4[17]/A17 CAP2[1]/SCL1 DD(3V3) Row R 1 P0[12]/USB_PPWR2/ 2 P0[13]/USB_UP_LED2/ MISO1/AD0[6] MOSI1/AD0[7] 5 P3[24]/D24/ 6 P0[30]/USB_D1 CAP0[1]/PWM1[ P1[26]/USB_SSPND1/ SSIO LCDVD[12]/LCDVD[20]/ PWM1[6]/CAP0[0] 13 P2[17]/RAS ...
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... NXP Semiconductors 6.2 Pin description Table 4. Pin description Symbol Pin Ball P0[0] to P0[31] [1] [1] P0[0]/RD1/TXD3/ 94 U15 SDA1 [1] [1] P0[1]/TD1/RXD3/ 96 T14 SCL1 [1] [1] P0[2]/TXD0 202 C4 [1] [1] P0[3]/RXD0 204 D6 [1] [1] P0[4]/I2SRX_CLK/ 168 B12 LCDVD[0]/RD2/ CAP2[0] [1] [1] P0[5]/I2SRX_WS/ 166 C12 LCDVD[1]/TD2/ CAP2[1] [1] [1] P0[6]/I2SRX_SDA/ 164 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P0[7]/I2STX_CLK/ 162 C13 LCDVD[9]/SCK1/ MAT2[1] [1] [1] P0[8]/I2STX_WS/ 160 A15 LCDVD[16]/ MISO1/MAT2[2] [1] [1] P0[9]/I2STX_SDA/ 158 C14 LCDVD[17]/ MOSI1/MAT2[3] [1] [1] P0[10]/TXD2/ 98 T15 SDA2/MAT3[0] [1] [1] P0[11]/RXD2/ 100 R14 SCL2/MAT3[1] [2] [2] P0[12 USB_PPWR2/ MISO1/AD0[6] ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P0[14 USB_HSTEN2/ USB_CONNECT2/ SSEL1 [1] [1] P0[15]/TXD1/ 128 J16 SCK0/SCK [1] [1] P0[16]/RXD1/ 130 J14 SSEL0/SSEL [1] [1] P0[17]/CTS1/ 126 K17 MISO0/MISO [1] [1] P0[18]/DCD1/ 124 K15 MOSI0/MOSI [1] [1] P0[19]/DSR1/ 122 L17 MCICLK/SDA1 [1] [1] P0[20]/DTR1/ ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [2] [2] P0[23]/AD0[0 I2SRX_CLK/ CAP3[0] [2] [2] P0[24]/AD0[1 I2SRX_WS/ CAP3[1] [2] [2] P0[25]/AD0[2 I2SRX_SDA/ TXD3 [2][3] [2][3] P0[26]/AD0[3 AOUT/RXD3 [4] [4] P0[27]/SDA0 50 T1 [4] [4] P0[28]/SCL0 48 R3 [5] [5] P0[29]/USB_D [5] [5] P0[30]/USB_D [5] [5] P0[31]/USB_D+2 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P1[3]/ 177 A10 ENET_TXD3/ MCICMD/ PWM0[2] [1] [1] P1[4]/ 192 A5 ENET_TX_EN [1] [1] P1[5]/ 156 A17 ENET_TX_ER/ MCIPWR/ PWM0[3] [1] [1] P1[6]/ 171 B11 ENET_TX_CLK/ MCIDAT0/ PWM0[4] [1] [1] P1[7]/ 153 D14 ENET_COL/ MCIDAT1/ PWM0[5] [1] [1] P1[8]/ 190 C7 ENET_CRS_DV/ ENET_CRS [1] [1] ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P1[16]/ 180 D10 ENET_MDC [1] [1] P1[17]/ 178 A9 ENET_MDIO [1] [1] P1[18 USB_UP_LED1/ PWM1[1]/CAP1[0] [1] [1] P1[19 USB_TX_E1/ USB_PPWR1/ CAP1[1] [1] [1] P1[20 USB_TX_DP1/ LCDVD[6]/ LCDVD[10]/ PWM1[2]/SCK0 [1] [1] P1[21 USB_TX_DM1/ LCDVD[7]/ LCDVD[11]/ PWM1[3]/SSEL0 [1] [1] ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P1[25]/USB_LS1/ 80 T10 LCDVD[11]/ LCDVD[15]/ USB_HSTEN1/ MAT1[1] [1] [1] P1[26]/ 82 R10 USB_SSPND1/ LCDVD[12]/ LCDVD[20]/ PWM1[6]/CAP0[0] [1] [1] P1[27]/USB_INT1/ 88 T12 LCDVD[13]/ LCDVD[21]/ USB_OVRCR1/ CAP0[1] [1] [1] P1[28]/USB_SCL1/ 90 T13 LCDVD[14]/ LCDVD[22]/ PCAP1[0]/MAT0[0] [1] [1] P1[29]/USB_SDA1/ 92 U14 LCDVD[15]/ ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P2[0]/PWM1[1]/ 154 B17 TXD1/TRACECLK/ LCDPWR [1] [1] P2[1]/PWM1[2]/ 152 E14 RXD1/PIPESTAT0/ LCDLE [1] [1] P2[2]/PWM1[3]/ 150 D15 CTS1/PIPESTAT1/ LCDDCLK [1] [1] P2[3]/PWM1[4]/ 144 E16 DCD1/PIPESTAT2/ LCDFP [1] [1] P2[4]/PWM1[5]/ 142 D17 DSR1/ TRACESYNC/ LCDENAB/LCDM [1] [1] ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P2[8]/TD2/TXD2/ 134 H15 TRACEPKT3/ LCDVD[2]/ LCDVD[6] [1] [1] P2[9]/ 132 H16 USB_CONNECT1/ RXD2/EXTIN0/ LCDVD[3]/ LCDVD[7] [6] [6] P2[10]/EINT0 110 N15 [6] [6] P2[11]/EINT1/ 108 T17 LCDCLKIN/ MCIDAT1/ I2STX_CLK [6] [6] P2[12]/EINT2/ 106 N14 LCDVD[4]/ LCDVD[3]/ LCDVD[8]/ ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P2[16]/CAS 87 R11 [1] [1] P2[17]/RAS 95 R13 [1] [1] P2[18 CLKOUT0 [1] [1] P2[19 CLKOUT1 [1] [1] P2[20]/DYCS0 73 T8 [1] [1] P2[21]/DYCS1 81 U11 [1] [1] P2[22]/DYCS2/ 85 U12 CAP3[0]/SCK0 [1] [1] P2[23]/DYCS3 CAP3[1]/SSEL0 [1] [1] P2[24 CKEOUT0 [1] [1] ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P2[31 DQMOUT3/ MAT3[3]/SCL2 P3[0] to P3[31] [1] [1] P3[0]/D0 197 B4 [1] [1] P3[1]/D1 201 B3 [1] [1] P3[2]/D2 207 B1 [1] [1] P3[3]/ [1] [1] P3[4]/ [1] [1] P3[5]/ [1] [1] P3[6]/ [1] [1] P3[7]/ [1] [1] P3[8]/D8 191 D8 [1] [1] P3[9]/D9 199 C5 [1] [1] P3[10]/D10 205 B2 [1] [1] P3[11]/D11 208 D5 [1] ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P3[16]/D16/ 137 F17 PWM0[1]/TXD1 [1] [1] P3[17]/D17/ 143 F15 PWM0[2]/RXD1 [1] [1] P3[18]/D18/ 151 C15 PWM0[3]/CTS1 [1] [1] P3[19]/D19/ 161 B14 PWM0[4]/DCD1 [1] [1] P3[20]/D20/ 167 A13 PWM0[5]/DSR1 [1] [1] P3[21]/D21/ ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P3[26]/D26 MAT0[1]/ PWM1[3] [1] [1] P3[27]/D27/ 203 A1 CAP1[0]/ PWM1[4] [1] [1] P3[28]/D28 CAP1[1]/ PWM1[5] [1] [1] P3[29]/D29 MAT1[0]/ PWM1[6] [1] [1] P3[30]/D30 MAT1[1]/ RTS1 [1] [1] P3[31]/D31 MAT1[2] P4[0] to P4[31] [1] [1] P4[0]/ [1] ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P4[7]/A7 121 L16 [1] [1] P4[8]/A8 127 J17 [1] [1] P4[9]/A9 131 H17 [1] [1] P4[10]/A10 135 G17 [1] [1] P4[11]/A11 145 F14 [1] [1] P4[12]/A12 149 C16 [1] [1] P4[13]/A13 155 B16 [1] [1] P4[14]/A14 159 B15 [1] [1] P4[15]/A15 173 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P4[23]/A23/ 129 J15 RXD2/MOSI1 [1] [1] P4[24]/OE 183 B8 [1] [1] P4[25]/WE 179 B9 [1] [1] P4[26]/BLS0 119 L15 [1] [1] P4[27]/BLS1 139 G15 [1] [1] P4[28]/BLS2/ 170 C11 MAT2[0]/LCDVD[6]/ LCDVD[10]/ LCDVD[2]/ TXD3 [1] [1] P4[29]/BLS3/ 176 B10 MAT2[1] LCDVD[7]/ ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [7] [7] RESET 35 M2 [8] [8] XTAL1 44 M4 [8] [8] XTAL2 46 N4 [8] [8] RTCX1 34 K2 [8] [8] RTCX2 33, 63, L3, T5, SSIO 77, 93, R9,P12, 114,133, N16, 148,169, H14, 189, E15, [9] 200 A12, B6, [ 32, 84, K4, P10, ...
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... NXP Semiconductors [ tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis. [8] Pad provides special analog functionality. [9] Pad provides special analog functionality. [10] Pad provides special analog functionality. [11] Pad provides special analog functionality. [12] Pad provides special analog functionality. ...
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... NXP Semiconductors Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue ...
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... NXP Semiconductors Table 5. Address range General use 0x0000 0000 to 0x3FFF FFFF 0x4000 0000 to 0x7FFF FFFF 0x8000 0000 to 0xDFFF FFFF 0xE000 0000 to 0xEFFF FFFF 0xF000 0000 to 0xFFFF FFFF LPC2478_1 Preliminary data sheet LPC2478 memory usage and details Address range details and description ...
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... NXP Semiconductors 4.0 GB 3.75 GB 3.5 GB 3.0 GB 2.0 GB 1.0 GB 0.0 GB Fig 4. LPC2478 memory map 7.5 Interrupt controller The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted ...
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... NXP Semiconductors service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs, which include all interrupt requests that are not classified as FIQs, have a programmable interrupt priority ...
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... NXP Semiconductors – Asynchronous page mode read – Programmable Wait States – Bus turnaround delay – Output enable and write enable delays – Extended wait • Four chip selects for synchronous memory and four chip selects for static memory devices • ...
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... NXP Semiconductors • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the peripheral. • ...
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... NXP Semiconductors 7.10 LCD controller The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT panels can be operated. The display resolution is selectable and can 1024 u 768 pixels ...
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... NXP Semiconductors The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic in the LPC2478 takes place on a different AHB subsystem, effectively separating Ethernet activity from the rest of the system. The Ethernet DMA can also access off-chip memory via the EMC, as well as the SRAM located on another AHB ...
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... NXP Semiconductors 7.12 USB interface The Universal Serial Bus (USB 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the host controller ...
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... NXP Semiconductors 7.12.3 USB OTG Controller USB OTG (On-The-Go supplement to the USB 2.0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The OTG Controller integrates the Host Controller, Device Controller, and a master-only ...
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... NXP Semiconductors 7.14 10-bit ADC The LPC2478 contains one ADC single 10-bit successive approximation ADC with eight channels. 7.14.1 Features • 10-bit successive approximation ADC • Input multiplexing among 8 pins • Power-down mode • Measurement range • 10-bit conversion time t 2.44 Ps • ...
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... NXP Semiconductors • UART3 includes an IrDA mode to support infrared communication. 7.17 SPI serial I/O controller The LPC2478 contains one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master ...
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... NXP Semiconductors • Conforms to Multimedia Card Specification v2.11. • Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96. • Can be used as a multimedia card bus or a secure digital memory card bus host. The SD/MMC can be connected to several multimedia cards or a single secure digital memory card. • ...
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... NXP Semiconductors 7.21.1 Features • The interface has separate input/output channels each of which can operate in master or slave mode. • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. • Mono and stereo audio data supported. • The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1, 48) kHz. • ...
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... NXP Semiconductors 7.23 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2478. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers ...
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... NXP Semiconductors • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. • ...
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... NXP Semiconductors 7.25.1 Features • Measures the passage of time to maintain a calendar and clock. • Ultra low power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. • Dedicated 32 kHz oscillator or programmable prescaler from APB clock. ...
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... NXP Semiconductors 7.26.1.3 RTC oscillator The RTC oscillator can be used as the clock source for the RTC and/or the WDT. Also, the RTC oscillator can be used to drive the PLL and the CPU. 7.26.2 PLL The PLL accepts an input clock frequency in the range of 32 kHz to 50 MHz. The input frequency is multiplied high frequency, then divided down to provide the actual clock used by the CPU and the USB block ...
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... NXP Semiconductors PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, Peripheral power control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application ...
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... NXP Semiconductors 7.26.4.4 Power domains The LPC2478 provides two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the Battery RAM. On the LPC2478, I/O pads are powered by the 3 DD(DCDC)(3V3) the CPU and most of the peripherals. ...
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... NXP Semiconductors The second stage of low-voltage detection asserts Reset to inactivate the LPC2478 when the voltage on the V flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below which point the power-on reset circuitry maintains the overall Reset ...
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... NXP Semiconductors 7.27.5 External interrupt inputs The LPC2478 includes edge sensitive interrupt inputs combined with up to four level sensitive external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode. 7.27.6 Memory mapping control The memory mapping control alters the mapping of the interrupt vectors that appear at the beginning at address 0x0000 0000 ...
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... NXP Semiconductors Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction. 7.28.3 RealMonitor RealMonitor is a configurable software module, developed by ARM Inc., which enables real-time debug lightweight debug monitor that runs in the background while users debug their foreground application ...
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... NXP Semiconductors 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter supply voltage DD(DCDC)(3V3) (3 analog 3.3 V pad supply voltage DDA V input voltage on pin VBAT i(VBAT) V input voltage on pin VREF ...
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... NXP Semiconductors 9. Static characteristics Table 7. Static characteristics + for commercial applications, unless otherwise specified. amb Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter DD(DCDC)(3V3) supply voltage (3 analog 3.3 V pad DDA supply voltage V input voltage on pin i(VBAT) VBAT V input voltage on pin ...
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... NXP Semiconductors Table 7. Static characteristics …continued +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter I active mode DC-to-DC DD(DCDC)act(3V3) converter supply current (3 power-down mode DD(DCDC)pd(3V3) DC-to-DC converter supply current (3 active mode battery BATact supply current 2 I C-bus pins (P0[27] and P0[28]) ...
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... NXP Semiconductors Table 7. Static characteristics …continued +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter USB pins I OFF-state output OZ current V bus supply voltage BUS V differential input DI sensitivity voltage V differential common CM mode voltage range V single-ended receiver th(rs)se switching threshold ...
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... NXP Semiconductors Table 8. ADC static characteristics 2 3 +85 DDA amb Symbol Parameter E gain error G E absolute error T R voltage source interface vsi resistance [1] Conditions 3.3 V. SSA DDA [2] The ADC is monotonic, there are no missing codes. [3] The differential linearity error ( the difference between the actual step width and the ideal step width ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. ...
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... NXP Semiconductors AD0[y] SAMPLE Fig 6. Suggested ADC interface - LPC2478 AD0[y] pin LPC2478_1 Preliminary data sheet LPC2XXX R vsi 20 k: AD0[ Rev. 01 — 6 July 2007 LPC2478 Fast communication chip V EXT 002aac733 © NXP B.V. 2007. All rights reserved ...
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... NXP Semiconductors 10. Dynamic characteristics Table 9. Dynamic characteristics of USB pins (full-speed pF 1 DD(3V3) Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP FEOPT ...
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... NXP Semiconductors Table 11. External memory interface dynamic characteristics pF amb Symbol Parameter Common to read and write cycles t XCLK HIGH to address valid CHAV time t XCLK HIGH to CS LOW time CHCSL t XCLK HIGH to CS HIGH CHCSH time t XCLK HIGH to address ...
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... NXP Semiconductors Table 11. External memory interface dynamic characteristics pF amb Symbol Parameter t BLS HIGH to data invalid BLSHDNV time t XCLK HIGH to data valid CHDV time t XCLK HIGH to WE LOW CHWEL time t XCLK HIGH to BLS LOW CHBLSL time t XCLK HIGH to WE HIGH ...
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... NXP Semiconductors 10.1 Timing XCLK CS addr data t CSLOEL OE Fig 7. External memory read access XCLK CS BLS/WE addr data OE Fig 8. External memory write access LPC2478_1 Preliminary data sheet t CSLAV OELAV t CHOEL t CSLDV t AVCSL t WELWEH t CSLWEL t BLSLBLSH t t CSLBLSL WELDV t CSLDV Rev. 01 — 6 July 2007 ...
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... NXP Semiconductors V − 0 0.2V 0.2V DD 0.45 V Fig 9. External clock timing t PERIOD crossover point differential data lines differential data to SEO/EOP skew Fig 10. Differential data-to-EOP transition skew and EOP width LPC2478_1 Preliminary data sheet + 0 − 0 CHCL CLCX crossover point extended ...
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... NXP Semiconductors 11. Application information 11.1 LCD panel signal usage Table 13. LCD panel connections for STN single panel mode External pin 4-bit mono STN single panel LPC2478 pin LCD function used LCDVD[23 LCDVD[22 LCDVD[21 LCDVD[20 LCDVD[19 LCDVD[18 LCDVD[17 LCDVD[16 LCDVD[15 LCDVD[14 LCDVD[13 LCDVD[12] ...
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... NXP Semiconductors Table 14. LCD panel connections for STN dual panel mode External pin 4-bit mono STN dual panel LPC2478 pin LCD function used LCDVD[23 LCDVD[22 LCDVD[21 LCDVD[20 LCDVD[19 LCDVD[18 LCDVD[17 LCDVD[16 LCDVD[15 LCDVD[14 LCDVD[13 LCDVD[12] - [3] LCDVD[11] P4[29] LD[3] [3] LCDVD[10] P4[28] LD[2] [2] LCDVD[9] P2[13] LD[1] [2] LCDVD[8] P2[12] LD[0] LCDVD[ LCDVD[6] ...
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... NXP Semiconductors Table 15. LCD panel connections for TFT panels External TFT 12 bit (4:4:4 mode) TFT 16 bit (5:6:5 mode) pin LPC2478 LCD pin used function [4] LCDVD[23] P1[29] BLUE3 [4] LCDVD[22] P1[28] BLUE2 [4] LCDVD[21] P1[27] BLUE1 [4] LCDVD[20] P1[26] BLUE0 LCDVD[19 LCDVD[18 LCDVD[17 LCDVD[16 [4] LCDVD[15] P1[25] GREEN3 [4] LCDVD[14] P1[24] GREEN2 [4] LCDVD[13] P1[23] GREEN1 [4] LCDVD[12] P1[22] ...
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... NXP Semiconductors 11.2 Suggested USB interface solutions LPC24XX Fig 11. LPC2478 USB interface on a self-powered device LPC24XX Fig 12. LPC2478 USB interface on a bus-powered device LPC2478_1 Preliminary data sheet V DD(3V3) USB_UP_LED USB_CONNECT soft-connect switch R1 1 BUS USB_D USB_D 002aac737 V DD(3V3 USB_UP_LED 1 ...
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... NXP Semiconductors RSTOUT USB_SCL1 USB_SDA1 USB_INT1 USB_D+1 USB_D1 USB_UP_LED1 LPC24XX USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D2 USB_UP_LED2 Fig 13. LPC2478 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host LPC2478_1 Preliminary data sheet RESET_N ADR/PSW OE_N/INT_N V DD ...
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... NXP Semiconductors RSTOUT USB_TX_E1 USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 LPC24XX USB_SCL1 USB_SDA1 USB_INT1 USB_UP_LED1 Fig 14. LPC2478 USB OTG port configuration: VP_VM mode LPC2478_1 Preliminary data sheet V DD RESET_N OE_N/INT_N DAT_VP SE0_VM RCV ISP1301 ADR/PSW SPEED SUSPEND SCL SDA INT_N ...
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... NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC24XX USB_UP_LED2 USB_CONNECT2 USB_D+2 USB_D2 V BUS Fig 15. LPC2478 USB OTG port configuration: USB port 2 device, USB port 1 host LPC2478_1 Preliminary data sheet ENA FLAGA 5 V OUTA LM3526 ...
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... NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC24XX USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D2 USB_UP_LED2 Fig 16. LPC2478 USB OTG port configuration: USB port 1 host, USB port 2 host LPC2478_1 Preliminary data sheet ENA FLAGA OUTA LM3526-L OUTB ...
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... NXP Semiconductors 12. Package outline LQFP208; plastic low profile quad flat package; 208 leads; body 1 156 157 pin 1 index 208 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls; body 0.7 mm ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT ...
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... NXP Semiconductors 13. Abbreviations Table 16. Acronym ADC AHB AMBA APB ATX BLS BOD CAN DAC DCC DMA DSP EOP ETM GPIO JTAG LCD MII OHC OTG PHY PLL PWM RMII SE0 SPI SSI SSP TTL UART USB LPC2478_1 Preliminary data sheet Acronym list ...
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... NXP Semiconductors 14. Revision history Table 17. Revision history Document ID Release date LPC2478_1 20070209 LPC2478_1 Preliminary data sheet Data sheet status Change notice Preliminary data sheet - Rev. 01 — 6 July 2007 LPC2478 Fast communication chip Supersedes - © NXP B.V. 2007. All rights reserved ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 7 Functional description . . . . . . . . . . . . . . . . . . 26 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 26 7.2 On-chip flash programming memory . . . . . . . 27 7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 27 7.4 Memory map 7.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 29 7.5.1 Interrupt sources 7.6 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 30 7 ...
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... NXP Semiconductors 15 Legal information 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 74 15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 15.4 Trademarks Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Fast communication chip Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. ...