MC100EP14

Manufacturer Part NumberMC100EP14
ManufacturerON Semiconductor
MC100EP14 datasheet
 


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MC100EP14
3.3V / 5V 1:5 Differential
ECL/PECL/HSTL Clock Driver
Description
The MC100EP14 is a low skew 1−to−5 differential driver, designed with
clock distribution in mind, accepting two clock sources into an input
multiplexer. The ECL/PECL input signals can be either differential or
single−ended (if the V
output is used). HSTL inputs can be used when
BB
the LVEP14 is operating under PECL conditions.
The EP14 specifically guarantees low output−to−output skew. Optimal
design, layout, and processing minimize skew within a device and from
device to device.
To ensure that the tight skew specification is realized, both sides of
any differential output need to be terminated even if only one output is
being used. If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
The common enable (EN) is synchronous, outputs are enabled/
disabled in the LOW state. This avoids a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. The internal flip flop is clocked on the falling edge of the input
clock, therefore all associated specification limits are referenced to the
negative edge of the clock input.
The MC100EP14, as with most other ECL devices, can be operated
from a positive V
supply in PECL mode. This allows the EP14 to be
CC
used for high performance clock distribution in 5.0 V systems.
Designers can take advantage of the EP14’s performance to distribute
low skew clocks across the backplane or the board.
Features
400 ps Typical Propagation Delay
100 ps Device−to−Device Skew
25 ps Within Device Skew
Maximum Frequency > 2 GHz Typical
The 100 Series Contains Temperature Compensation
PECL and HSTL Mode:
V
= 3.0 V to 5.5 V with V
= 0 V
CC
EE
NECL Mode:
V
= 0 V with V
= −3.0 V to −5.5 V
CC
EE
Open Input Default State
These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 5
http://onsemi.com
TSSOP−20
DT SUFFIX
CASE 948E
MARKING DIAGRAM*
20
EP14
ALYWG
1
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
1
100
G
Publication Order Number:
MC100EP14/D

MC100EP14 Summary of contents