MC100EPT25DT ON Semiconductor, MC100EPT25DT Datasheet

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MC100EPT25DT

Manufacturer Part Number
MC100EPT25DT
Description
Manufacturer
ON Semiconductor
Datasheet

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MC100EPT25
-3.3V / -5V Differential ECL
to +3.3V LVTTL Translator
Description
device requires +3.3 V, −3.3 V to −5.2 V, and ground. The small
outline 8−lead package and the single gate of the EPT25 make it ideal
for applications which require the translation of a clock or data signal.
input mode. In this mode the V
inverting buffer or the D input for a non−inverting buffer. If used, the
V
capacitor.
Features
© Semiconductor Components Industries, LLC, 2008
August, 2008 − Rev. 16
BB
The MC100EPT25 is a Differential ECL to LVTTL translator. This
The V
V
1.1 ns Typical Propagation Delay
Maximum Frequency > 275 MHz Typical
Operating Range: V
24 mA TTL Outputs
Q Output Will Default LOW with Inputs Open or at V
V
Open Input Default State
Safety Clamp on Inputs
Pb−Free Packages are Available
EE
BB
pin should be bypassed to ground with at least a 0.01 mF
= −5.5 V to −3.0 V; GND = 0 V
Output
BB
output allows the EPT25 to also be used in a single−ended
CC
= 3.0 V to 3.6 V;
BB
output is tied to the D input for a
EE
1
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
CASE 506AA
MN SUFFIX
CASE 948R
DT SUFFIX
CASE 751
D SUFFIX
TSSOP−8
*For additional marking information, refer to
8
(Note: Microdot may be in either location)
SOIC−8
Application Note AND8002/D.
DFN8
8
1
ORDERING INFORMATION
1
A
L
Y
W
M
G
http://onsemi.com
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
MARKING DIAGRAMS*
Publication Order Number:
8
1
8
1
ALYWG
KPT25
1
ALYW
KA25
MC100EPT25/D
G
G
4

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MC100EPT25DT Summary of contents

Page 1

MC100EPT25 -3.3V / -5V Differential ECL to +3.3V LVTTL Translator Description The MC100EPT25 is a Differential ECL to LVTTL translator. This device requires +3.3 V, −3 −5.2 V, and ground. The small outline 8−lead package and the single gate ...

Page 2

LVTTL LVECL/ECL Figure 1. 8−Lead Pinout (Top View) and Logic Diagram Table 2. ATTRIBUTES Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out ...

Page 3

Table 3. MAXIMUM RATINGS Symbol Parameter V Positive Power Supply CC V Negative Power Supply EE V Input Voltage Sink/Source Operating Temperature Range A T Storage Temperature Range stg q Thermal Resistance (Junction−to−Ambient) JA ...

Page 4

Table 5. TTL OUTPUT DC CHARACTERISTICS Symbol Characteristic V Output HIGH Voltage OH V Output LOW Voltage OL I Power Supply Current CCH I Power Supply Current CCL NOTE: Device will meet the specifications after thermal equilibrium has been established ...

Page 5

... ORDERING INFORMATION Device MC100EPT25D MC100EPT25DG MC100EPT25DR2 MC100EPT25DR2G MC100EPT25DT MC100EPT25DTG MC100EPT25DTR2 MC100EPT25DTR2G MC100EPT25MNR4 MC100EPT25MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D ...

Page 6

... C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004) ...

Page 7

K 8x REF 0.10 (0.004) 0.15 (0.006 L −U− PIN 1 IDENT 0.15 (0.006 −V− C 0.10 (0.004) D −T− G SEATING PLANE PACKAGE DIMENSIONS TSSOP−8 ...

Page 8

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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