MD80C86-2/B Intersil Corporation, MD80C86-2/B Datasheet
MD80C86-2/B
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MD80C86-2/B Summary of contents
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... CP80C86-2Z CP80C86- +70 (Note) MD80C86-2/883 MD80C86-2/883 -55 to +125 40 Ld CERDIP F40.6 MD80C86-2/B MD80C86-2/B -55 to +125 40 Ld CERDIP F40.6 8405202QA 8405202QA -55 to +125 40 Ld CERDIP *Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications. ...
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Pinout 2 80C86 80C86 (40 LD PDIP, CERDIP) TOP VIEW MAX GND AD14 2 AD15 AD13 3 38 A16/S3 AD12 4 37 A17/S4 AD11 5 36 A18/S5 AD10 6 35 A19/S6 AD9 7 34 BHE/S7 ...
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Functional Diagram EXECUTION UNIT REGISTER FILE DATA POINTER AND INDEX REGS (8 WORDS) 16-BIT ALU FLAGS TEST INTR NMI RQ/GT0 HOLD HLDA INTERFACE UNIT EXECUTION UNIT 3 80C86 BUS INTERFACE UNIT RELOCATION REGISTER FILE SEGMENT REGISTERS AND INSTRUCTION ...
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Pin Descriptions The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers). PIN ...
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Pin Descriptions (Continued) The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers). ...
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Minimum Mode System (Continued) The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/ mode are described; all other pin functions are as described in the following. PIN SYMBOL NUMBER TYPE HOLD 31, 30 ...
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Maximum Mode System (Continued) The following pin function descriptions are for the 80C86 system in maximum mode (i.e., MN/MX - GND). Only the pin functions which are unique to maximum mode are described in the following. PIN SYMBOL NUMBER TYPE ...
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Functional Description Static Operation All 80C86 circuitry is of static design. Internal registers, counters and latches are static and require no refresh as with dynamic circuit design. This eliminates the minimum operating frequency restriction placed on other microprocessors. The CMOS ...
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Word (16-bit) operands can be located on even or odd address boundaries and are thus, not constrained to even boundaries as is the case in many 16-bit computers. For address and data operands, the least significant byte of the word ...
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Status bits S0, S1 and S2 are used by the bus controller, in maximum mode, to identify the type of bus transaction according ...
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FFFFFH RESET BOOTSTRAP PROGRAM JUMP FFFF0H TYPE 225 POINTER 3FFH (AVAILABLE) 3FCH AVAILABLE INTERRUPT POINTERS (224) TYPE 33 POINTER (AVAILABLE) 084H TYPE 32 POINTER (AVAILABLE) 080H TYPE 31 POINTER (AVAILABLE) 07FH RESERVED INTERRUPT POINTERS (27) TYPE 5 POINTER (RESERVED) ...
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CLK ALE S2-S0 BHE, ADDR/ A19-A16 STATUS A15-A0 ADDR/DATA RD, INTA READY DT/R DEN MEMORY ACCESS TIME WR External Interface Processor RESET and Initialization Processor initialization or start up is accomplished with activation (HIGH) of the RESET pin. ...
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Bus Hold Circuitry To avoid high current conditions caused by floating inputs to CMOS devices and to eliminate need for pull-up/down resistors, “bus-hold” circuitry has been used on the 80C86 pins 2-16, 26-32 and 34-39 (see Figures 4A and 4B). ...
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TI ALE LOCK INTA FLOAT AD0- AD15 FIGURE 5. INTERRUPT ACKNOWLEDGE SEQUENCE Halt When a software “HALT” instruction is executed, the processor indicates that it is entering the “HALT” state in one of two ...
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DT/R and DEN are provided by the 80C86. A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO signal is again asserted to indicate ...
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V CC MN/MX M/IO 82C8A/85 INTA CLK CLOCK RD GENERATOR READY WR RES RESET RDY DT/R DEN WAIT ALE GND STATE GENERATOR 80C86 CPU GND AD0-AD15 1 A16-A19 BHE GND ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Capacitance +25°C SYMBOL PARAMETER C Input Capacitance IN C Output Capacitance OUT C I/O Capacitance I/O NOTES: 3. lBHH should be measured after raising V 4. IBHL should be measured after lowering V 5. lCCSB tested during ...
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AC Electrical Specifications tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) SYMBOL PARAMETER (23) TCLLH ALE Active Delay (24) TCHLL ALE Inactive Delay (25) TLLAX Address Hold Time ...
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Waveforms CLK (82C84A OUTPUT) (30) TCHCTV M/IO BHE/S7, A19/S6-A16/S3 (23) TCLLH ALE RDY (82C84A INPUT) SEE NOTE READY (80C86 INPUT) AD15-AD0 RD READ CYCLE (WR, INTA = DT/R DEN NOTE: Signals at 82C84A are shown for reference ...
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Waveforms (Continued) CLK (82C84A OUTPUT) TCLAV AD15-AD0 WRITE CYCLE DEN (RD, INTA, DT TCLAZ AD15-AD0 DT/R INTA CYCLE (SEE NOTE) (RD INTA BHE = DEN SOFTWARE HALT - ...
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AC Electrical Specifications tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. TIMING REQUIREMENTS SYMBOL PARAMETER MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER) Timing Requirements (1) TCLCL CLK Cycle Period ...
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AC Electrical Specifications tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) TIMING REQUIREMENTS SYMBOL PARAMETER (22) TCLSH Status Inactive Delay (Note 15) (23) TCLAV Address Valid Delay (24) ...
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AC Electrical Specifications tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) TIMING REQUIREMENTS SYMBOL PARAMETER (34) TCLDX2 Data Hold Time (35) TCVNV Control Active Delay (Note 11) (36) ...
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Waveforms CLK QS0, QS1 (21) TCHSV S2, S1, S0 (EXCEPT HALT) (23) TCLAV BHE/S7, A19/S6-A16/S3 TSVLH (27) ALE (82C88 OUTPUT) NOTE RDY (82C84 INPUT) READY 80C86 INPUT) READ CYCLE TCLAV AD15-AD0 RD DT/R 82C88 MRDC OR IORC OUTPUTS SEE NOTES ...
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Waveforms (Continued) CLK TCHSV (21) S2, S1, S0 (EXCEPT HALT) WRITE CYCLE AD -AD 15 DEN 82C88 OUTPUTS AMWC OR AIOWC SEE NOTES 18, 19 MWTC OR IOWC INTA CYCLE AD15-AD0 (SEE NOTES 21, 22) (25) TCLAZ AD15-AD0 (28) TSVMCH ...
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Waveforms (Continued) CLK TCLGH (44) (1) TCLCL RQ/GT PREVIOUS GRANT AD15-AD0 RD, LOCK BHE/S7, A19/S0-A16/S3 S2, S1, S0 NOTE: The coprocessor may not drive the busses outside the region shown without risking contention. FIGURE 9. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ...
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Waveforms (Continued) AC Test Circuit DEVICE UNDER TEST NOTE: Includes stay and jig capacitance. AC Testing Input, Output Waveform INPUT NOTE: AC Testing: All input signals (other than CLK) must ...
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... CC/2 27 generated on program card ( 28. Pins input sequenced instruction from internal hold devices. 29 100kHz ±10%. 0 30. Node = a 40µs pulse every 2.56ms 80C86 MD80C86 CERDIP 1 GND RIO 2 AD14 AD15 39 RIO 3 AD13 AD16 ...
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Metallization Topology DIE DIMENSIONS: 249.2 x 290 METALLIZATION: Type: Silicon - Aluminum Thickness: 11kÅ ±2kÅ Metallization Mask Layout AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI 30 80C86 GLASSIVATION: Type: Nitrox Thickness: 10kÅ ...
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Instruction Set Summary MNEMONIC AND DESCRIPTION DATA TRANSFER MOV = Move: Register/Memory to/from Register Immediate to Register/Memory Immediate to Register Memory to Accumulator Accumulator to Memory Register/Memory to Segment Register †† Segment Register to Register/Memory PUSH = Push: Register/Memory Register ...
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Instruction Set Summary (Continued) MNEMONIC AND DESCRIPTION ADC = Add with Carry: Register/Memory with Register to Either Immediate to Register/Memory Immediate to Accumulator INC = Increment: Register/Memory Register AAA = ASCll Adjust for Add DAA = Decimal Adjust for Add ...
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Instruction Set Summary (Continued) MNEMONIC AND DESCRIPTION SAR = Shift Arithmetic Right ROL = Rotate Left ROR = Rotate Right RCL = Rotate Through Carry Flag Left RCR = Rotate Through Carry Right AND = And: Reg./Memory and Register to ...
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Instruction Set Summary (Continued) MNEMONIC AND DESCRIPTION Direct Intersegment Indirect Intersegment RET = Return from CALL: Within Segment Within Seg Adding lmmed to SP Intersegment Intersegment Adding Immediate to SP JE/JZ = Jump on Equal/Zero JL/JNGE = Jump on Less/Not ...
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Instruction Set Summary (Continued) MNEMONIC AND DESCRIPTION STD = Set Direction CLl = Clear Interrupt ST = Set Interrupt HLT = Halt WAIT = Wait ESC = Escape (to External Device) LOCK = Bus Lock Prefix NOTES 8-bit ...
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Dual-In-Line Plastic Packages (PDIP INDEX N/2 AREA -B- -A- D BASE PLANE -C- SEATING PLANE 0.010 (0.25 NOTES: 1. Controlling Dimensions: INCH. In case of conflict between ...
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... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...