ML7204-001 Oki Semiconductor, ML7204-001 Datasheet
ML7204-001
Available stocks
Related parts for ML7204-001
ML7204-001 Summary of contents
Page 1
... The ML7204-001 is a speech CODEC for VoIP. G.729.A/G711 and supports the PLC (Packet Loss Concealment) function. With an echo canceler that handles 32 ms-delay and FSK detection/generation, DTMF detection/generation, and tone detection/generation functions, the ML7204-001 is the most suitable LSI for adding the VoIP function to TAs and routers. FEATURES • ...
Page 2
... OKI Semiconductor • Master clock frequency: 12.288 MHz (crystal; external input) • Supports hardware and software power down • Package: 64-pin plastic QFP (QFP64-P-1414-0.80-BK) 100-pin plastic TQFP (TQFP100-P-1414-0.50-BK) FEDL7204-001DIGEST-01 ML7204-001 (ML7204-001GA) (ML7204V-001TB) 2/42 ...
Page 3
... OKI Semiconductor BLOCK DIAGRAM P/S S/P TS CONT CH2 CH1 CH1 CH2 RXGAIN _CH2 - + FEDL7204-001DIGEST-01 ML7204-001 4 [3:0] GPIO 6 [5:0] GPIO 8 [7:0] GPIOC TST1 TST0 PDNB CLKOUT XO XI 3/42 ...
Page 4
... PIN CONFIGURATION (TOP VIEW) AVDD 49 AIN0P 50 AIN0N 51 GSX0 52 GSX1 53 AIN1N 54 AVREF 55 VFRO0 56 VFRO1 57 AGND 58 DGND2 DVDD2 62 VREGOUT 63 VBG 64 64-Pin Plastic QFP FEDL7204-001DIGEST-01 ML7204-001 D15 32 D14 31 D13 30 D12 29 D11 28 D10 4/42 ...
Page 5
... VFRO1 87 AGND DGND2 DVDD2 VREGOUT 98 VBG 99 NC 100 : Provided for 100-pin packages only 100-Pin Plastic TQFP FEDL7204-001DIGEST-01 ML7204-001 50 NC D15 49 D14 D13 46 D12 D11 43 D10 ...
Page 6
... Receive buffer DMA access request signal output Interrupt request output (primary function) I/O “H” General-purpose I/O port A [6] (secondary function tolerant pin Chip select control input I I Read control input I I Write control input — — Digital ground (0.0 V) FEDL7204-001DIGEST-01 ML7204-001 Description 6/42 ...
Page 7
... Digital power supply I I Address input I I Address input I I Address input I I Address input I I Address input I I Address input I I Address input I I Address input FEDL7204-001DIGEST-01 ML7204-001 Description 7/42 ...
Page 8
... AMP3 output (10 kΩ driving) — — Analog ground (0.0 V) — — (Unused) — — (Unused) — — Digital ground (0 12.288 MHz crystal interface, 12.288 MHz clock input — — (Unused) O “H” 12.288 MHz crystal interface FEDL7204-001DIGEST-01 ML7204-001 Description 8/42 ...
Page 9
... VBG 100 — NC When I/O PDNB = “0” — — Digital power supply — — (Unused) — — (Unused) — — Internal regulator voltage output pin (approx. 2.5 V) — — Internal regulator reference voltage output pin — — (Unused) FEDL7204-001DIGEST-01 ML7204-001 Description 9/42 ...
Page 10
... Fmck MCK Fbclk BCLK (at input) Fsync SYNC (at input) DRCLK MCK, BCLK (at input) tBS BCLK to SYNC (at input) tSB SYNC to BCLK (at input) tWS SYNC (at input) FEDL7204-001DIGEST-01 ML7204-001 Rating Unit –0.3 to +4.6 V –0.3 to +4.6 V –0.3 to AVDD+0.3 V –0.3 to DVDD+0.3 V –0.3 to +6.0 V –0.3 to DVDD+0.3 V –20 to +20 ...
Page 11
... IOH = 0.5 mA (XO pin) IOH = 1 2.0 mA (CLKOUT pin) Digital output pins, I/O pin IOL = –4.0 mA IOL = –0.5 mA (XO pin –12.0 mA (CLKOUT pin) Open drain output pins IOL = –12.0 mA Input pins I/O pins FEDL7204-001DIGEST-01 ML7204-001 Min. Typ. Max. Unit µA — 200 500 — — ...
Page 12
... V, DVDD0 3.0 to 3.6 V, AGND = DGND0 0 –20 to 60°C unless otherwise specified) Condition AIN0N, AIN0P, AIN1N GSX0, GSX1, VFRO0, VFRO1 Analog output pins VFRO0, VFRO1 GSX0, GSX1, VFRO0, VFRO1 RL = 10kΩ, AMP input 1.3 Vpp FEDL7204-001DIGEST-01 ML7204-001 Min. Typ. Max. Unit 10 — — MΩ 10 — ...
Page 13
... Analog input = — AVREF — PCMI = ”1” 1020 0 1020 0 FEDL7204-001DIGEST-01 ML7204-001 Min. Typ. Max. Unit 25 — — dB –0.15 — 0.20 dB Reference — –0.15 — 0. — 0. — ...
Page 14
... V, DVDD0 3.0 to 3.6 V, AGND = DGND0 0 –20 to 60°C unless otherwise specified) Condition — — Echo Canceler Sin Sout Level Meter LPF Rout Rin 5kHz FEDL7204-001DIGEST-01 ML7204-001 Min. Typ. Max. Unit –1.0 — 1.0 dB Min. Typ. Max. Unit –1.5 — ...
Page 15
... –20 to 60°C unless otherwise specified) Condition Min. PDNB pin 250 — — AVREF = 1.4 (90 4.7 µ 0.1 µF (See Figure 9) AVREF = 1.4 (90 2.2 µ 0.1 µF (See Figure 9) t AVREF FEDL7204-001DIGEST-01 ML7204-001 Typ. Max. Unit µs — — 0 — — ns — — — ...
Page 16
... CDL = 20 pF (during output) 1 BCLK = 2.048 MHz At output BCLK to SYNC (during output) SYNC to BCLK (during output) PCMI pin PCMO pin Pull-up resistance RDL = 500Ω CDL = FEDL7204-001DIGEST-01 ML7204-001 Min. Typ. Max. Unit –0.1% 2.048 +0.1% MHz –0.1% 8 +0.1% kHz 45 50 ...
Page 17
... BCLK tBS tSB tWS SYNC tXD1 MSB PCMO Figure 5 PCM Interface Output Timing (Short Frame tXD2 FEDL7204-001DIGEST-01 ML7204-001 tXD3 tXD3 LSB LSB G.711 16-bit linear tXD3 tXD3 LSB LSB G.711 16-bit linear 17/42 ...
Page 18
... V, Ta= –20 to 60°C unless otherwise specified) Condition tWAS tWAH tRAS D1 Input tWDS tWDH tWCS tWCH tCD tRCS tWW Write timing Figure 6 Control Register Interface FEDL7204-001DIGEST-01 ML7204-001 Min. Typ. Max. Unit 10 — — — — — — — ...
Page 19
... –20 to 60°C unless otherwise specified) Condition tF0S tF1S tF1D A1 tWAS tWAH tRAS D1 Input tWDS tWDH tWCS tWCH tCD tRCS tWW Write timing FEDL7204-001DIGEST-01 ML7204-001 Min. Typ. Max. Unit 3 — — ns — — — — — — ...
Page 20
... –20 to 60°C unless otherwise specified) Condition Min tDR0S tDR1S tDR1FD tDR1RD A1 tWAS tWAH tRAS D1 Input tWDS tWDH tAK0S tAK1S tAK1H tAD tWW Write timing FEDL7204-001DIGEST-01 ML7204-001 Typ. Max. Unit 3 — — ns — — — — — — — ...
Page 21
... Gain = R2/R1 <= 32(+30dB Variable R2 : 500k Max. Out : 1.3Vp-p Max. GSX1 R4 10kΩ AIN1N AMP1 VFRO1_SEL 10kΩ C4 VFRO1 AMP3 GSX0 R2 10kΩ AIN0N AIN0P AMP0 VFRO0_SEL 10kΩ C3 VFRO0 AMP2 AVREF VREF C5 + 2.2 to 4.7µF C6 0.1µF Figure 9 Analog Interface FEDL7204-001DIGEST-01 ML7204-001 A/D1 D/A1 A/D0 D/A0 21/42 ...
Page 22
... XI pin, then release the power-down state (PDNB = 0 → this case also, fix PDNB to “0” for 250 µs or more. CR0-B7 To the internal (SPDN) section PDNB XO CLKOUT XI Crystal (12.288 MHz) Kyocera Kinseki Corp. HC-49/U-S [C FEDL7204-001DIGEST-01 ML7204-001 Oscillation starts after To the internal section XO CLKOUT Open 12.288 MHz Provisional MΩ ...
Page 23
... VBG This is a reference output pin for an internal regulator. Connect a laminated ceramic capacitor of about 150 pF between this pin and a ground pin. TST0 and TST1 These are input pins for testing. At normal use, input “0”. FEDL7204-001DIGEST-01 ML7204-001 23/42 ...
Page 24
... Secondary function: GPIOA[6] When the primary function/secondary function selection register (GPFA[6]) of GPIOA[6] is set to “1”, this pin functions as a general-purpose I/O port GPIOA[6]. Table 1 Interrupt Causes Register name ×: Without INTB interrupt generation function FEDL7204-001DIGEST-01 ML7204-001 Rising Falling Remarks edge edge × ...
Page 25
... D8-D15 to either “0” or “1” since they are constantly in an input state. CSB This is a chip select input pin for accessing a frame/control register. RDB This is a read enable input pin for accessing a frame/DMA/control register. WRB This is a write enable input pin for accessing a frame/DMA/control register. FEDL7204-001DIGEST-01 ML7204-001 25/42 ...
Page 26
... GPIOA[0], GPIOA[1], GPIOA[2], and GPIOA[3] These are general-purpose I/O ports A[3:0]. However, the following secondary functions are assigned to GPIOA[0] and GPIOA[2]. Secondary function of GPIOA[0]: Input pin (DPI dial pulse detecter (DPDET) Secondary function of GPIOA[2]: Output pin (DPO dial pulse transmitter (DPGEN) FEDL7204-001DIGEST-01 ML7204-001 26/42 ...
Page 27
... Always input a clock after start of power supply. Input When G.711 is selected, input a clock of 64 kHz to 2.048 (64 kHz to MHz. 2048 kHz) When 16-bit linear is selected, input a clock of 128 kHz to 2.048 MHz. Output At power down, “L” is output. (2.048 MHz) FEDL7204-001DIGEST-01 ML7204-001 Remarks 27/42 ...
Page 28
... RXGENA DTMF_CODE[3:0] TONE_GEN0 RXGENB (TONE A/ B) RXGENB_EN TONE_DET0 TONE0_DET FGEN_FLAG RXGEN FSK_GEN TONE_DET1 TONE1_DET Unused RX_SIG PCM Codec Speech EC Codec RX_SIG FEDL7204-001DIGEST-01 ML7204-001 PCM I/F Encoder G.711 P/S PCMO SYNC BCLK TS PCM Codec CONT CLKSEL RXGAIN_ITS1 Decoder G.711 PCMI S/P RXGAIN_ITS2 ACK1B/ G.729.A TX GPIOA[5] ...
Page 29
... RXGENA DTMF_CODE[3:0] TONE_GEN0 RXGENB (TONE) RXGENB_EN TONE_DET0 TONE0_DET FGEN_FLAG RXGEN TONE_DET1 TONE1_DET FSK_GEN Unused RX_SIG PCM Codec Speech EC Codec RX_SIG FEDL7204-001DIGEST-01 ML7204-001 PCM I/F Encoder G.711 P/S PCMO SYNC BCLK PCM Codec TS CONT CLKSEL RXGAIN_ITS1 Decoder G.711 PCMI S/P RXGAIN_ITS2 ACK1B/ G.729.A TX GPIOA[5] CH1 ...
Page 30
... C/ D) FDET_D[7:0] RXGENA_EN DTMF_DET DTMF_REC TGEN0_EXFLAG RXGENA DTMF_CODE[3:0] TONE_GEN0 RXGENB (TONE A/ B) RXGENB_EN TONE_DET0 TONE0_DET FGEN_FLAG RXGEN TONE_DET1 FSK_GEN TONE1_DET Unused FEDL7204-001DIGEST-01 ML7204-001 PCM I/F Encoder G.711 P/S PCMO SYNC BCLK TS PCM Codec CONT CLKSEL RXGAIN_ITS1 Decoder PCMI G.711 S/P RXGAIN_ITS2 ACK1B/ G.729.A TX ...
Page 31
... PCM Codec (CODEC_B) Linear PCM A-TEL1 Codec (CODEC_A) ML7204 (Configuration example 3) Linear PCM Codec (CODEC_B) Linear A-TEL2 PCM Codec (CODEC_A) ML7204 (Configuration example 3) RX_SIG PCM PCM Codec I/F Speech MCU EC Codec I/F RX_SIG RX_SIG PCM PCM Codec I/F Speech MCU EC Codec I/F RX_SIG FEDL7204-001DIGEST-01 ML7204-001 31/42 ...
Page 32
... FDET_FER/FDET_OER FDET_D[7:0] (TONE C/D) RXGENA_EN DTMF_DET DTMF_REC RXGENA TGEN0_EXFLAG DTMF_CODE[3:0] TONE_GEN0 RXGENB (TONE A/B) RXGENB_EN TONE_DET0 TONE0_DET FGEN_FLAG RXGEN TONE_DET1 FSK_GEN TONE1_DET Unused FEDL7204-001DIGEST-01 ML7204-001 PCM I/F Encoder G.711 P/S PCMO SYNC BCLK PCM Codec TS CONT CLKSEL RXGAIN_ITS1 Decoder G.711 PCMI S/P RXGAIN_ITS2 ACK1B/ G.729.A TX GPIOA[5] ...
Page 33
... Codec (CODEC_B) Linear PCM A-TEL2 Codec (CODEC_A) ML7204 (Configuration example 3) Linear PCM Codec (CODEC_B) Linear A-TEL1 PCM Codec (CODEC_A) ML7204 (Configuration example 4) RX_SIG PCM PCM Codec I/F Speech MCU EC Codec I/F RX_SIG RX_SIG PCM PCM Codec I/F Speech MCU EC Codec I/F RX_SIG FEDL7204-001DIGEST-01 ML7204-001 VoIP-NW 33/42 ...
Page 34
... TGEN0_EXFLAG DTMF_CODE[3:0] TONE_GEN0 RXGENB (TONE A/B) RXGENB_EN TONE_DET0 TONE0_DET FGEN_FLAG RXGEN TONE_DET1 TONE1_DET FSK_GEN Unused RX_SIG PCM Codec Speech EC Codec RX_SIG FEDL7204-001DIGEST-01 ML7204-001 PCM I/F Encoder G.711 P/S PCMO SYNC BCLK TS PCM Codec CONT CLKSEL RXGAIN_ITS1 Decoder G.711 PCMI S/P RXGAIN_ITS2 ACK1B/ G.729.A TX GPIOA[5] Buffer0 ...
Page 35
... DTMF_REC TGEN0_EXFLAG RXGENA DTMF_CODE[3:0] TONE_GEN0 RXGENB (TONE A/ B) RXGENB_EN TONE_DET0 TONE0_DET FGEN_FLAG RXGEN TONE_DET1 TONE1_DET FSK_GEN Unused ML7204 (configuration example 6) I/F A-TEL2 FEDL7204-001DIGEST-01 ML7204-001 PCM I/F Encoder G.711 P/S PCMO SYNC BCLK TS PCM Codec CONT CLKSEL RXGAIN_ITS1 Decoder PCMI G.711 S/P RXGAIN_ITS2 ACK1B/ GPIOA[5] G.729.A ...
Page 36
... TGEN0_EXFLAG DTMF_CODE[3:0] TONE_GEN0 RXGENB (TONE A/ B) RXGENB_EN TONE_DET0 TONE0_DET FGEN_FLAG RXGEN TONE_DET1 FSK_GEN TONE1_DET Unused RX_SIG PCM Codec Speech EC Codec RX_SIG FEDL7204-001DIGEST-01 ML7204-001 Encoder PCM I/F G.711 P/S PCMO SYNC BCLK TS PCM Codec CONT CLKSEL RXGAIN_ITS1 Decoder G.711 PCMI S/P RXGAIN_ITS2 ACK1B/ G.729.A TX GPIOA[5] ...
Page 37
... FR1B PDNB INTB 60 CSB XI 61 RDB XO WRB 1MΩ 8pF VBG +3 DVDD0 VREGOUT 33 DVDD1 62 DVDD2 49 AVDD 16 DGND0 44 DGND1 59 TST1 DGND2 58 TST0 AGND FEDL7204-001DIGEST-01 ML7204-001 MCU ...
Page 38
... V 61 PDNB 12 DVDD0 52 CLKOUT DVDD1 95 DVDD2 76 AVDD 25 TST1 DGND0 67 TST0 DGND1 91 DGND2 88 AGND FEDL7204-001DIGEST-01 ML7204-001 MCU I/F +3 150 µF Power-down control 1 12.288 MHz clock output Conditions 2 • Frame mode • SYNC and BCLK: 3 Configured to be output (CLKSEL = "1") 38/42 ...
Page 39
... The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). FEDL7204-001DIGEST-01 ML7204-001 (Unit: mm) 39/42 ...
Page 40
... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). FEDL7204-001DIGEST-01 ML7204-001 (Unit: mm) Package material Epoxy resin Lead frame material ...
Page 41
... OKI Semiconductor REVISION HISTORY Document No. FEDL7204-001DIGEST-01 Aug. 12, 2004 Page Date Previous Current Edition Edition – – FEDL7204-001DIGEST-01 ML7204-001 Description Final edition 1 41/42 ...
Page 42
... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. FEDL7204-001DIGEST-01 ML7204-001 Copyright 2004 Oki Electric Industry Co., Ltd. 42/42 ...